CHAPTER - 6 T 7B DIGITAL FREQUENCY COUNTER The Digital frequency counter is a highly accurate and has high resolution with

automatic indication of KHz/MHz and decimal point and internal standard time base of 1MHz with 1-PPM accuracy. Basically the circuit of the instrument fall into three main sections, the counting decoders with display, the time base and the input amplifier. The block diagram of the Digital Frequency Counter is shown in Fig. 6 6.1 Input Amplifier and Schmitt Trigger: The input circuit consists of a network of capacitors, resistors and diodes. The functions are as follows: 1. 2. 3. C1 removes any DC component from the input signal. C2 prevents attenuation of high frequency signals and R1, D1 & D2 prevents overload of the input transistors.

Input transistors Q1 and Q2 are direct-coupled with 100% negative feedback to provide wide bandwidth with high input impedance and approximately unity gain. Transistor Q3 is an amplifier with emitter compensation; isolated from the succeeding Schmitt trigger by emitter follower Q4. Schmitt trigger transistors Q5 and Q6 are emitter coupled to current mode operation to produce fast switching times required for the first decoder counter. Emitter follower Q7 prevents the TTL logic in the counter circuit from loading the Schmitt trigger. 6.2 Counting and display circuit (Fig 5.2) a) Start/Stop gate The pulses which are to be counted are fed via amplifier Q1 and differentiated by C2, R3. The transistors Q2, Q3 & Q4 form a gate which is controlled by two bistable circuits FFA & FFB, of IC1. While the gate is open, pulses can pass to the driver stage Q1. Integrated circuits IC2 to IC4 form a decoder counter suitable for frequencies upto 30 MHz. IC2 and IC3 are dual master slave flip flops. IC4 is a quad Nand gate. They are connected together to give binary coded decimal (BCD) output. 6.3 Integrated Decoder and display: The BCD outputs from the high frequency decoder are fed to the integrated decoding and indicator driving package IC5 and additionally the positive going edge of the BCDs output of IC11 drives 1C6 and so on. Each integrated decoder has an associated decoding and read out package to drive the numerical indicator. The decoding IC convert the BCD input to decimal form and drive the display tube cathode indicating the digit.

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Reset Pulse Generator: The Reset circuit which resets all decoder to zero at the end of display period function as follows: When the display time control is switched from the "HOLD position a charging current flows through C8 after a stop pulse has triggered the stop bi-stable FFB and cut off Q10. The charging rate is determined by the setting of the display time potentiometer. As C8 charges, it switches Q8 and causes Q7 to cease conduction. Q7 is directly coupled to Q6 and the switching action regenerates through R11 so that a positive reset pulse occurs on the reset line from the collector of Q6. Q5 acts as an inverter to supply negative pulse necessary for IC 1. The reset pulse resets the 0 output of the stop bi-stable of IC, to the "high" state and bottoms Q10 which therefore discharges C8 through R14 and R12 giving a Reset pulse length of approximately 5 m sec. The circuit containing Q9 enables manual reset to be applied.

6.5

Time base and power circuits: a) 1 MHz OSCILLATOR: Crystal (X-tal) and Transistor Q3 from a conventional piece oscillator circuit. Q4 is an emitter follower, which prevents loading of the oscillator and couples to the next stage via a standard switch to the trigger circuit Q5, Q6 which shapes the 1MHz standard. TIME BASE: The time base consists of IC decoder which divide the frequency down in stages of 10 from 100KHz to 0.1Hz. The circuitry comprised of IC7 is used to re-clock the time base to eliminate propagation errors when delivering start and stop pulses for the counter gates. The start and stop pulses are timed from the BCD 1 output from the first decoder IC 1 as follows. Reset is applied to Q11, which damps the output of one side of the bistable formed by the inter-connection of two gate circuits in IC 7. The first positive going pulse from the output is inverted by one of the NAND gates of the IC 7 and is applied to the bistable formed by TWO NAND gates in the same IC. This negative going pulse from this bistable output is used as start pulse. The selected time units switched by the gate time switch is applied to the 4th NAND gate of IC 7. This NAND gate inverts the pulse and applies it to the bistable. The first positive going edge occurs after a complete count of 10 by the appropriate decoder and then resets the bistable so that the next positive going 1 output from IC2 can cause the bistable to toggle and give a negative stop pulse. The positive going 1 pulses are therefore gated by the required decoder output to give extra gate time.

b)

Transistor Q7 and Q8 form a gate which is closed during reset to prevent pulses passing into the decoders during the reset period and Q9 inverts the signal so that the trailing edge of the reset pulse does not trigger the decoder. 6.6 Power Supplies: Q12 is a series regulator transistor for the main power supply and is controlled by Q1 and Q2 from the reference diode D6 to give a regulated supply of 4.8V. The ICs are operated from 4.8V supply. The 200V DC rectified from D5 supplies, the indicator tubes, 20V DC supply for amplifier board is derived from an additional secondary winding. The heater supply for the crystal oven is derived from one of the secondaries of the transformer. This supply switched by a in-built thermostat maintains the temperature of crystal oven at 60 to 2 C. This is necessary for the stability of crystal frequency upto (1 PPM).