Unit 3: Integrated-circuit amplifiers (contd.

)
COMMON-SOURCE AND COMMON-EMITTER AMPLIFIERS The Common-Source Circuit The most basic IC MOS amplifier is shown in fig.(1). The source of MOS transistor is grounded , also the drain resistor RD replaced by a constant-current source I. The currentsource load can be implemented using a PMOS transistor and is therefore called an active load, and the CS amplifier of Fig. 1(a) is said to be active-loaded. Before we consider the small-signal operation of the active-loaded CS amplifier, it is important to know that Q1 is biased to have ID = I. But the DC voltages at the drain and at the gate are developed by a circuit which is a part of a larger circuit in which negative feedback is utilized to fix the values of VDS and VGS. We shall assume that these circuits are in such a way that they bias the MOSFET in operate in the saturation region.

Fig.1 (a) Active-loaded common-source amplifier, (b) Small-signal analysis of the amplifier in (a), performed both directly on the circuit diagram and using the smallsignal model explicitly. Since we analyse the circuit to obtain input impedance, voltage gain, current gain & output impedance in the view of small-signal, the biasing arrangement in the circuit is not shown. Small-signal analysis of the current-source-loaded CS amplifier is straightforward and is illustrated in Fig. 1(b). Here, along with the equivalent circuit model, we show the transistor with its r0 extracted and displayed separately and with the analysis performed directly on the circuit. From Fig. 1(b) we see that for this CS amplifier,

.. (1)

Rin = , AVO = -gmro (since vi = vgs and vo = - gm rovgs) and R0 =r0. We note that |Avo| is the maximum voltage gain available from a common-source amplifier, namely the intrinsic gain of the MOSFET, A 0 = gm ro Common-Source Amplifier implemented using CMOS A CMOS circuit implementation of the common-source amplifier is shown in Fig. 2(a) This circuit is based on that shown in Fig. 1(a) with the load current-source I implemented using transistor Q2. This is the output transistor of the current mirror formed by Q2 and Q3 and fed with the bias current IREF. We shall assume that Q2 and Q3 are matched; therefore the

Fig.2 The CMOS common-source amplifier : (a) circuit: (b) i-v characteristic of the active-loadQ2 ; (c) graphical construction to determine the transfer characteristic: and (d) transfer characteristic. i-v characteristic of the load device will be as shown in Fig. 2(b). This is simply the iD-vSD characteristic curve of the p-channel transistor Q2 for a constant source-gate 2

voltage VSG. The value of VSG is set by passing the reference bias current IREF through Q3. Observe that, Q2 behaves as a current source when it operates in saturation, which in turn is obtained when v = vSD exceeds (VSG - |Vtp|), which is the magnitude of the overdrive voltage at which Q2 and Q3 are operating. Q2 exhibits a finite incremental resistance ro2, when it is in saturation and is given by,
.. (2)

Where VA2 is the Early voltage of Q2. In other words, the current-source load is not ideal but has a finite output resistance equal to the transistor r0. The circuits transfer characteristic, vo versus vi, needs to be observed before analyzing the circuit to calculate voltage gain. This can be obtained using the graphical construction shown in Fig. 2 (c). Here we have sketched the iD-vDS characteristics of the amplifying transistor Q1 and superimposed the load curve on them. The latter is simply the i-v curve in Fig. 2(b) "flipped around" and shifted VDD volts along the horizontal axis. Now, since vGS1=vi, each of the iD-vDS curves corresponds to a particular value of vi. The intersection of each particular curve with the load curve gives the corresponding value of VDS1, which is equal to v0. Thus, in this way, we can obtain the v0-vi characteristic, point by point. The resulting transfer characteristic is sketched in Fig. 2(d). As indicated, it has four distinct segments, labeled I, II, III, and IV, each of which is obtained for one of the four combinations of the modes of operation of Q1 and Q2, which are also indicated in the diagram. Note also that we have labeled two important break points on the transfer characteristic (A and B) in correspondence with the intersection points (A and B) in Fig. 2 (c). For amplifier operation segment III is the one of interest. Observe that in region III the transfer curve is almost linear and is very steep, indicating large voltage gain. In region III both the amplifying transistor Q1 and the load transistor Q2 are operating in saturation. The end points of region III are A and B: At A, defined by v0 = VDD - V0V2, Q2 enters the triode region, and at B, defined by v0 = vi Vtn, Q1 enters the triode region. When the amplifier is biased at a point in region III, the small-signal voltage gain can be determined by replacing Q1 with its small-signal model and Q2 with its output resistances ro2. The output resistance of Q2 constitutes the load resistance of Q1. The voltage gain Av can be found from Eq. below

 (3)

to obtain
(4)

indicating that, as expected, Av will be lower in magnitude than the intrinsic gain of Q1, gm1ro1. For the case ro2 = rol, Av will be gm1rol/2. The CMOS common-source amplifier can be designed to provide voltage gains ranging from 15 to 100. It offers a very high input resistance; however, its output resistance is also high. Two final comments need to be made before leaving the common-source amplifier: 1. The circuit is not affected by the body effect since the source terminals of both Q1 and Q2 are at signal ground. 2. The circuit is usually part of a larger amplifier circuit and negative feedback is utilized to ensure that the circuit in fact operates in region III of the amplifier transfer characteristic. EXAMPLE Consider the CMOS common-source amplifier in Fig. 2 (a) for the case VDD = 3 V, Vtn = |Vtp| = 0.6 V, nC0X = 200 A / V2, and pC0x = 65 A / V2. For all transistors, L = 0.4 m and W=4 m. Also, VAn = 20 V, | VAp|= 10 V, and IREF = 100 A. Find the smallsignal voltage gain. Also, find the coordinates of the extremities of the amplifier region of the transfer characteristic that is, points A and B in the transfer characteristic. Solution

The extremities of the amplifier region of the transfer characteristic(region III) are found as follows (Fig. 2): First, we determine VSG of Q2 and Q3 corresponding to ID = IREF = 100 A

Where | V0V3| is the magnitude of the overdrive voltage at which Q3 and Q2 are operating, and we have used the fact that, for Q3, VSD = VSG. Thus, VSG = 0.6 + 0.53 = 1.13 V and VOA = VDD |Vov2| = 2.47 V Noting that in region III Q1, and Q2 are in saturation and obviously conduct equal currents, When vin = VIB, vo= VOB,
VDSn=0 and VDSp = VOA-VOB
VOA VOB = VOA (VGSn Vtn) =2.47-VIB+0.6 =3.07 - VIB

The width of the amplifier region is therefore vi = VIB -VIA = 0.05 V and the corresponding output range is V0=VOB - VOA = -2.14 V Thus the "large-signal" voltage gain is

which is very close to the small-signal value of -42, indicating that segment III of the transfer characteristic is quite linear. 7

The Common-Emitter Circuit

FIGURE 3(a) Active-loaded common-emitter amplifier, (b) Small-signal analysis of the amplifier in (a), performed both directly on the circuit and using the hybrid- model explicitly. The active-loaded common-emitter amplifier, in Fig. 3(a), is similar to the active-loaded common-source circuit studied above. Here also, the bias-stabilizing circuit is not shown. Small-signal analysis is similar to that for the MOS case and is shown in Fig. 3(b). The results are Ri = r Avo = -gmro Ro = r o which except for the rather low input resistance r are similar to the MOSFET case. Recall, however, from the comparison, that the intrinsic gain gmr0 of the BJT is much higher than that for the MOSFET. This advantage, however, is counterbalanced by the practically infinite input resistance of the common-source amplifier. HIGH-FREQUENCY RESPONSE OF THE CS AND CE AMPLIFIERS Consider the high-frequency response of the active-loaded common-source and commonemitter amplifiers. Figure4 shows the high-frequency equivalent circuit of the commonsource amplifier. This equivalent circuit applies equally well to the CE amplifier with Cgs being replaced by C, Cgd by C, and Vgs by V. 8
(5)

Figure4: High-frequency equivalent-circuit model of the common-source amplifier. For the common-emitter amplifier, the values of Vsig and Rsig are modified to include the effects of r and rx ; Cgs is replaced by C,Vgs by V and Cgd by C. The input-signal source is represented by Vsig and Rsig. In some cases, Vsig and Rsig would be modified values of the signal-source voltage and internal resistance, taking into account other resistive components such as a bias resistor RG or RB, the BJT resistances rx and r, etc. The load resistance RL represents the combination of an actual load resistance (if connected) and the output resistance of the current-source load. To avoid loss of gain; RL is usually of the same order as r0. We combine RL with r0, and denote their parallel equivalent RL. The load capacitance CL represents the total capacitance between drain (or collector) and ground; it includes the drain-to-body capacitance Cdb (collector-tosubstrate capacitance), the input capacitance of a succeeding amplifier stage, and in some cases, a deliberately introduced capacitance. In IC MOS amplifiers, CL can be relatively a very high value. Analysis Using Miller's Theorem When Rsig is relatively large and CL is relatively small. Miller's theorem can be used to obtain a quick but approximate estimate of the 3-dB frequency fH. Figure5 shows the approximate equivalent circuit obtained for the CS case, from which we see that the amplifier has a dominant pole formed by Rsig and Cin.

gmvgs

FIGURE 5 Approximate equivalent circuit obtained by applying Miller's theorem while neglecting CL and the load current component supplied by Cgd. This model works reasonably well when Rsig is large and amplifier high-frequency response is dominated by the pole formed by Rsig and Cin.

(6)

(7)

(8)

(9)

Analysis Using Open-Circuit Time Constants The method of open-circuit time constants can be applied to the CS equivalent circuit of Fig. 4, as illustrated in Fig. 6 from which we see that the resistance seen by Cgs, Rgs = Rsig and that seen by CL is RL. The resistance Rgd seen by Cgd can be found by analyzing the circuit in Fig. 6(b) with the result that Rgd = Rsig (1+gmRL) + RL
(10)

10

Fig. 6 The open-circuit time constant method to the CS equivalent circuit of Fig.4 Thus the effective time-constant b, or H can be found as
(11)

and the 3-dB frequency fH is

(12)

In those cases in which CL is relatively high, this approach results in a better estimate of fH than that obtained using the Miller equivalence (because in the latter case we completely neglected CL). Exact Analysis The approximate analysis presented above provides insight about the limit in highfrequency gain of the CS (and CE) amplifiers. Nevertheless, given that the circuit of Fig. 4 is relatively simple, it will be good if we perform an exact analysis. This is illustrated in 11

Fig.7. A node equation at the drain provides

(13)

which can be manipulated to the form

(14)

A loop equation at the input yields Vsig = Ii Rsig + Vgs

(15)

in which we can substitute for Ii from a node equation at G, Ii= sCgsVgs + sCgd(Vgs-V0)
(16)

FIGURE 7 Analysis of the CS high-frequency equivalent circuit to obtain Vsig = Vgs [1+s(Cgs+Cgd)Rsig] - sCgdRsigVo
(17)

We can now substitute in this equation for Vgs from Eq. (14) to obtain an equation in V0 and Vsig that can be arranged to yield the amplifier gain as

12

 (18)

The transfer function in Eq. 18 indicates that the amplifier has a second-order denominator, and hence two poles. Now, since the numerator is of the first order, it follows that one of the two transmission zeros is at infinite frequency. This is readily verifiable by noting that as s approaches , (V0 / Vsig) approaches zero. The second zero is at
(19)

That is, it is on the positive real axis of the s-plane and has a frequency wz, z = gm/Cgd
(19a)

Since gm is usually large and Cgd is usually small, fz is normally a very high frequency and thus has negligible effect on the value of fH. It is useful at this point to show a simple method for finding the value of s at which V0= 0that is, sz. Figure 8 shows the circuit at S = sz. By definition, V0 = 0 and a node equation at D yields SzCsdVgs = gmVgs
(20)

we can divide both sides by Vgs to obtain

(21)

We should note that in Eq. (18), as s goes toward zero, V0/Vsig approaches the dc gain (-gmRL) as should be the case. In the denominator polynomial, we observe that the coefficient of the s term is equal to the effective time-constant H obtained using the open-circuit time-constants method as given by Eq. (11).

13

Fig8: The CS Ckt, at s=sz the output voltage Vo=0.

Denoting the frequencies of the two poles p1 and p2, we can express the denominator polynomial D(s) as

(22)

If P2 >P1that is, the pole at PI is dominantwe can approximate D(s) as

(23)

Equating the coefficients of the s term in denominator polynomial of Eq. (18) to that of the S term in Eq. (23) gives
(24)

where the approximation is that involved in Eq. (18). Note that the expression in Eq. (24) is identical to the result obtained using open-circuit time constants and a little different from the result obtained using the Miller equivalence, the difference being the term (C L + Cgd)RL related to the capacitance at the output, which was ignored in the original (simple) Miller derivation. Equating the coefficients of s2 in Eqs. (18) and (23), and using Eq. (24), frequency of the second pole:
(25)

EXAMPLE 14

A CMOS common-source amplifier of the type shown in Fig. 2(a) has W/L = 7.2 m/ 0.36 m for all transistors, n C0x = 387 A/V2, npCox = 86 A/ V2, IREF = 100 A, V'An = 5 V/m and | V'Ap| = 6 V/m. For Q1, Cgs = 20 fF, Cgd = 5 fF, CL = 25 fF. and Rsig = 10k. Assume that CL includes all the capacitances introduced by Q2 at the output node. Find fH using both the Miller equivalence and the open-circuit time constants. Also, determine the exact values of fP1, fP2, and fz and hence provide another estimate for fH. Solution

Thus,

which results in Vov= 0.16 V

Using the Miller equivalence:

15

Using the open-circuit time-constants method:

Thus

which can be summed to obtain H as

from which we find the 3-dB frequency fH,

We note that this is about 25% lower than the estimate obtained using the Miller equivalence. The discrepancy is mostly a result of neglecting CL in the Miller approach. Note that CL here has a substantial magnitude and that its contribution to H is significant (246 ps of the total 1160 ps, or 21%). To determine the exact locations of zero and the poles, we use the transfer function in eq(18) . The frequency of the zero is given by eq(19a) : fz = gm/(2Cgd) = 40 GHz. The frequencies wp1 and wp2 are found as the roots of the equation obtained by equating the denominator polynomial of eq(18) to zero: 1 + 1.16 X 10-9s + 0.0712 X 10-18 s2 =0 and, the result is fp1 = 145.3 MHz 16

And fp2 = 2.45GHz. since fZ, fp2>> fp1, a good estimate for fH fp1=145.3MHz. CE amplifier In the case of CE amplifier, the above formulae are straightaway adapted.

Fig.9: (a) High frequency equivalent circuit of the common-emitter amplifier. (b) equivalent circuit obtained after the Thevenin theorem is employed to simplify the resistive circuit at the input.

Fig.9(a) represent the high frequency equivalent circuit of the common-emitter amplifier. The Vsig and Rsig are modified to take into account the effect of rx and r. Vsig = Vsig r /(Rsig + rx +r)
.. (26)

Rsig= r // (Rsig +rx). The DC gain is given by .. (27) AM = -(r)(gm RL) /(Rsig + rx +r). Using the Millers theorem we get, .. (28) Cin = C + C (1+ gm RL). The 3-dB frequency, fH can be estimated from fH = 1 /(2Cin Rsig ).

.. (29)

17

Using the method of open-circuit time constants yields H = C R + C R + CL RL = C Rsig + C [(1+gm RL) Rsig + RL] + CL RL

.. (30)

fH can be estimated as fH . Exact analysis yields the following zero frequency: fz = gm/ (2C).
.. (31)

Assuming that a dominant pole exists,

.. (32)

.. (33)

The Situation When Rsig is Low In the applications where the CS amplifier is fed with a low-resistance signal source, the high-frequency gain will no longer be limited by the source resistance and the input capacitance. The high-frequency limitation happens at the amplifier output, as shown below: Figure 10(a) shows the high-frequency equivalent circuit of the common-source amplifier in when Rsig is zero. The voltage transfer function Vo/VSig = Vo/Vgs can be found by setting Rsig = 0 in Eq. (18). The result is
.. (34)

Thus, while the dc gain and the frequency of the zero do not change, the high-frequency response is now determined by a pole formed by CL + Cgd together with R'L. Thus the 3dB frequency is now given by

18

.. (35)

To see how this pole is formed, refer to Fig. 10(b), which shows the equivalent circuit with the input signal source set to zero. Observe that the circuit reduces to a capacitance (CL + Cgd) in parallel with a resistance R'L. As we have seen above, the transfer-function zero is usually at a very high frequency and thus does not play a significant role in shaping the high-frequency response. The gain of the CS amplifier will therefore fall off at a rate of-6 dB/octave (-20 dB/decade) and reaches

FIGURE 10 (a) High-frequency equivalent circuit of a CS amplifier fed with a signal source having a very low (effectively zero) resistance, (b) The circuit with Vsig reduced to zero, (c) Bode plot for the gain of the circuit in (a). unity (0 dB) at a frequency ft which is equal to the gain-bandwidth product,

Thus, 19

.. (36)

Figure 10(c) shows a sketch of the high-frequency gain of the CS amplifier. Example: Consider the CS amplifier specified when fed with a signal source having a negligible resistance (i.e. Rsig = 0). Find AM, f3dB, ft , and fz. If the amplifying transistor is to be operated at twice the original overdrive voltage while Wand L remain unchanged, what value of IREF is needed? What are the new values of AM , f3dB, ft and fz ? Solution AM = gm RL = -12.3 V/V The 3-dB frequency can be found using Eq. (35)

and the unity-gain frequency, which is equal to the gain-bandwidth product, can be determined as ft = |AM| fH = 12.3 x 540 = 6.6 GHz The frequency of the zero is

Now, to increase Vov from 0.16 V to 0.32 V, ID must be quadrupled by changing IREF to IREF = 400 A The new values of gm , rol, ro2, and RL can be found as follows:

20

Thus the new value of AM becomes AM = -gm R'L = - 2.5 x 2.45 = -6.15 V/V That of fH becomes

and the unity-gain frequency (i.e., the gain-bandwidth product) becomes ft = 6.15 x 2.16 = 13.3 GHz We note that doubling Vov results in reducing the dc gain by a factor of 2 and increasing the bandwidth by a factor of 4. Thus, the gain-bandwidth product is doubled. THE COMMON-GATE AND COMMON-BASE AMPLIFIERS WITH ACTIVE LOADS The Common-Gate Amplifier Figure 11(a) represents the basic IC MOS common-gate amplifier. The transistor has its gate grounded and its drain connected to an active load, given as an ideal constantcurrent source I. The input signal source vsig with a generator resistance Rs is connected to the source terminal. The MOSFET source is not connected to the substrate, hence the substrate terminal, B, is shown explicitly and indicate that it is connected to the lowest voltage in the circuit, i.e., to ground in this case. We may observe that except for showing the current-source I, which determines the dc bias current ID of the transistor, no other bias detail is shown. How the DC voltage VGS will be established and how VDS is 21

determined are not of concern to us here. However, it should be known that bias stability is assured through the application of negative feedback to the larger circuit of which the CG amplifier is a part. In this case, we assume that the MOSFET is operating in the saturation region and concentrate exclusively on its small-signal operation. The Body Effect: Since the substrate (i.e. body) is not connected to the source, the body effect plays a role in the operation of the common-gate amplifier. However, it turns out, that considering the body effect in the analysis of the CG circuit is very simple.

22

FIGURE 11 (a) Active-loaded common-gate amplifier, (b) MOSFET equivalent circuit for the CG case in wn.ch the body and gate terminals are connected to ground, (c) Small-signal analysis performed directly on the circuit diagram with the T model of (b) used implicitly, (d) Operation with the output open-circuited. Recall that the body terminal acts, in effect, as a second gate for the MOSFET. Thus, just as a signal voltage vgs between the gate and the source gives rise to a drain current signal gmvgs, a signal voltage vbs between the body and the source gives rise to a drain current signal gmbvbs. Thus the drain signal current becomes (gmvgs + gmbvbs) where the body transconductance gmb is a small fraction of gm ; gmb = gm and = 0.1 to 0.2. Since in the CG circuit of Fig. 11(a) both the gate and the body terminals are connected to ground, vbs = vgs, and the signal current in the drain becomes (gm + gmb)vgs. It follows that the body effect in the common-gate circuit can be fully accounted for by simply replacing gm of the MOSFET by (gm + gmb). As an example, Fig. 11(b) shows the MOSFET T-model modified in this way. Small-Signal Analysis The small-signal analysis of the CG amplifier can be performed either on an equivalent circuit obtained by replacing the MOSFET with its T model of Fig. 11(b) or directly on the circuit diagram with the model used implicitly. The latter approach is opted in order to gain greater insight into circuit operation. Figure 11(c) shows the CG circuit prepared for small-signal analysis. Here we observe "extracted" r0 of the MOSFET and shown it separately from the device. The resistance 1 /(gm + gmb), which appears in effect between gate and source looking into the source is also indicated. Note that a resistance RL is shown at the output; it is assumed to include the output resistance of the current-source load I as well as any load resistance if connected. The circuit of Fig. 11(c) is analysed to determine the various parameters that characterize the CG amplifier. The CG amplifier is not a unilateral circuit; the resistance rQ connects the output node to the input node. As a result we should expect the amplifier input resistance Rin to depend on RL and the output resistance Rout to depend on Rs. Input Resistance To determine the input resistance Rin, we must find a way to express ii in terms of vi. Inspection of the circuit in Fig. 11(c) reveals a key observation. The input current ii splits at the source node into two components: the source current i = (gm + gmb) vi and the current through r0, iro These two components combine at the drain to constitute the current io supplied to RL, ; thus io = ii, and vo = i0RL = iiRL. Now we can write at the source node ii=(gm + gmb)vi + ir0
. (37)

23

and express iro as

. (38)

Equations (37) and (38) can be combined to obtain

from which the input resistance Rin can be found as

. (39)

Observe that for r0 = , Rin reduces to 1 /(gm + gmb) which is indeed the input resistance with r0 neglected. When r0 is taken into account, this value of input resistance is obtained approximately only for RL = 0. For the usual case of RL = ro, Rin = 2/(gm + gmb). Interestingly, for large values of RL approaching infinity, Rin = . Operation with RL = Figure 11(d) shows the CG amplifier with RL removed; that is, RL = and the amplifier is operating with the output open-circuited. We note that since io=0, ii, must also be zero; the current i in the source terminal, i = (gm + gmb)vi, simply flows via the drain through ro and back to the source node. It follows that the input resistance with no load, Ri, is infinite: Ri = We can also use the circuit in Fig. 11(d) to determine the open-circuit voltage gain Avo between the input (source) and output (drain) terminals as follows: vo = iro + vi = (gm + gmb) vi ro+ vi Thus, Avo = 1 + (gm + gmb) ro
. (41) . (40)

This is a very important quantity that appears in almost all formulas that characterize the CG amplifier. We observe that Avo differs from the intrinsic gain of the MOSFET in two minor respects: First, there is an additional term of unity, and second, gmb is added to gm. Typically Avo is 10% to 20% larger than A0. 24

We should also note that the gain of the CG circuit is positive. That is, unlike the CS amplifier, the CG amplifier is non-inverting. From Eqs. (39) and (41), we can express the input resistance of the CG amplifier in the form as shown:
. (42)

That is, the CG circuit divides the total resistance (ro + RL) by the open-circuit voltage gain, which is approximately equal to the intrinsic gain of the MOSFET. Furthermore, since Avo= (gm + gmb)r0 A0, the expression for Rin can be simplified to
. (43)

This expression says that taking r0 into account adds a component (RL/A0) to the input resistance. This additional component becomes significant only when RL is large. Another interesting result that follows directly from the fact that ii = 0 in the circuit of Fig. 11(d): The voltage drop across Rs will be zero. Thus Vi = Vsig, and the open-circuit overall voltage gain, vo/vsig will be equal to Avo, Gvo = Avo= 1+(gm + gmb)r0
. (44)

Voltage Gain The voltage gains Av and Gv of the loaded CG amplifier of Fig. 11(c) can be obtained in a number of ways. The most direct approach is to make use, once more, of the fact that io = ii and express v0 as v0=i0 RL=ii RL
. (45)

The voltage vi, can be expressed in terms of ii as vi = ii Rin

. (46)

Dividing Eq. (45) by Eq. (46) yields, for the voltage gain, Av
. (47)

Substituting for Rin from Eq. (42) provides 25

. (48)

In a similar way, we can derive an expression for the overall voltage gain, Gv = vo/vsig vo = ioRL = iiRL vsig = ii (Rs + Rin) . (49) Thus,
. (50)

in which we can substitute for Rin from Eq. (42) to obtain

. (51)

Recalling that Gvo = Avo, we can express Gv as

. (52)

Output Resistance To complete our characterization of the CG amplifier, we find its output resistance. We recall that there are two different output resistances: Ro, which is the output resistance when vi is set to zero, and Rout which is the output resistance when vsig is set to zero. Both are illustrated in Fig. 12. Obviously R0 can be obtained from the expression for Rout by setting Rs = 0. It is important to be clear on the application of Ro and of Rout. Since R0 is the output resistance when the amplifier is fed with an ideal source vi it follows that it is the applicable output resistance for determining Av from Avo,
. (53)

On the other hand, Rout is the output resistance when the amplifier is fed with vsig and its resistance Rs; so it is the applicable output resistance for determining Gv from Gvo,

26

. (54)

Returning to the circuit in Fig. 12(a), we see by inspection that Ro = r o

. (55)

A verification of this result is achieved by substituting Ro = ro in Eq. (53) and then observing that the resulting expression for Av is identical to that in Eq. (48), which we obtained from circuit analysis. An expression for Rout can be derived using the circuit in Fig. 12 (b) where a test voltage Vx is applied at the output. Our aim is to find the current ix drawn from vx. Towards the

FIGURE 12 (a) The output resistance Ro is found by setting vi = 0. (b) The output resistance Rout is obtained by setting vsig=0. Other end we note that the current through Rs is equal to ix ; thus we can express the voltage v at the MOSFET source as v = i xR s
. (56)

Utilizing the analysis indicated on the circuit diagram in Fig. 12(b), we can write for vx

27

vx = [ix + (gm + gmb)v]ro + v

. (57)

Equations (56) and (57) can be combined to eliminate v and obtain vx in terms of ix and hence Rout = vx/ix. Rout = ro +[1+(gm + gmb)ro]Rs
. (58)

We recognize the term multiplying Rs as the open-circuit voltage gain Avo; thus Rout can be expressed in an alternative, more compact form as Rout = ro + AvoRs
. (59)

A verification of the formula for Rout in Eq. (59) can be obtained by substituting it in Eq. (54). The result will be seen to be identical to the gain expression in Eq. (52), which we derive by circuit analysis. The expressions for Rout in Eqs. (58) and (59) are very useful results that we will employ frequently further. These formulas give the output resistance not only of the CG amplifier but also of a CS amplifier with a resistance Rs in the emitter. A first interpretation, immediately available from Eq. (59), is that the CG transistor increases the output resistance by adding to r0 a component Avo Rs . In many cases the latter component would dominate, and one can think of the CG MOSFET as multiplying the resistance Rs in its source by Avo, which is approximately equal to gmr0. Note that this action is the complement of what we saw earlier in regard to Rin where the MOSFET acts to divide RL by Avo. This impedance transformation action of the CG MOSFET is illustrated in Fig. 13 and is a key to number of applications of the CG circuit. One such application involves the use of the CG amplifier as a current buffer. Fig. 14 shows an equivalent circuit that is suitable for such an application. It can be shown that the overall short-circuit current gain Gis is given by
. (60)

Wkt, vo/vsig = Gv = GvoRL / (RL+ro+AvoRs) =>ioRL / isigRs = GvoRL / (RL+ro+AvoRs), => io / isigRs = Gvo / (RL+ro+AvoRs) => io / isig= GvoRs / (RL+ro+AvoRs),When RL=0, 28 => io / isig = Gis = GvoRs / (ro+AvoRs),[short circuit current gain] GvoRs / Rout AvoRs / (ro+AvoRs) 1

The near-unity current gain together with the low input resistance and high output resistance are all characteristics of a good current buffer.Yet another interpretation of the formula for Rout can be obtained by expressing Eq. (58) in the form Rout= Rs + [1 + (gm + gmb) Rs] ro
. (61)

FIGURE 13 The impedance transformation property of the CG configuration.

29

FIGURE 14 Equivalent circuit of the CG amplifier illustrating its application as a current buffer, Rin and Rout are given in Fig. 13, and Gis = Avo (RS/Rout) In this expression the second term often dominates, enabling the following approximation

. (62)

Thus placing a resistance Rs in the source lead, results in multiplying the transistor output resistance ro by a factor (1+gmRs). High-Frequency Response Figure 15(a) shows the CG amplifier with the MOSFET internal capacitances Cgs and Cgd indicated. For generality, a capacitance CL is included at the output node to represent the input capacitance of a succeeding amplifier stage. Capacitance CL also includes the MOSFET capacitance Cdb. Note the CL appears in effect in parallel with Cgd. Therefore, in the following discussion we will lump the two capacitances together. It is important to note that each of the three capacitances in the circuit of Fig. 15(a) has a grounded node. Hence none of the capacitances undergoes the Miller-multiplication effect seen in the CS stage. It follows that the CG circuit can be designed to have a much wider bandwidth than that of the CS circuit, especially when the resistance of the signal generator is large.

30

FIGURE 15 (a) The common-gate amplifier with the transistor internal capacitances shown. A capacitance CL is also included, (b) Equivalent circuit for the case in which ro is neglected. Analysis of the circuit in Fig. 15(a) is greatly simplified if ro can be neglected. In such a case the input side is isolated from the output side, and the high-frequency equivalent circuit takes the form shown in Fig. 15(b). We immediately observe that there are two poles: one at the input side with a frequency fP1

. (63)

and the other at the output side with a frequency fP2.

31

. (64)

The relative locations of the two poles will depend on the specific situation. However, fP2 is usually lower than fP1; thus fP2 can be dominant. The important point to note is that both fPl and fp2 are usually much higher than the frequency of the dominant input pole in the CS stage. In situations when ro has to be taken into account (because Rs and RL are large), the method of open-circuit time constants can be employed to obtain an estimate for the 3-dB frequency fH ,Fig.16 shows the circuits for determining the resistances Rgs and Rgd seen by Cgs and (Cgd + CL), respectively. By inspection we obtain

. (65)

. (66)

. (67)

32

FIGURE 16 Circuits for determining Rgs, and Rgd EXAMPLE : Consider a common-gate amplifier specified as follows: W/L = 7.2 m/0.36 m, nCox = 387A/V2, ro = 18 k, ID = 100 A, gm = 1.25 mA/V, = 0.2 , Rs = 10 k, RL = 100 k, Cgs = 20 fF, Cgd = 5 fF, and CL = 0. Find Avo, Rin, Rout,. Gv, Gis, Gi and fH. Solution

33

It can be noticed that this circuit performs well as a current buffer, raising the resistance level from Rin= 4 k to Rout = 300 k and having an overall short-circuit current gain of 0.94 A/A. Because of the high output resistance, the amplifier bandwidth is determined mainly by the capacitance at the output node. So, additional load capacitance can lower the bandwidth significantly. Exercise: a) For the CG amplifier considered in Example above, find the value of fH when a capacitance CL = 5 fF is connected at the output. Ans. 196 MHz b) Repeat the problem in above Example for the case Rs = 1 k and RL = 10 k . Ans. Avo = 28 V/V; Rin = 1 k; Rout = 46 k; Gv = 5 V/V; Gis = 0.61 A/A; Gi = 0.5 A/A; fH= 2.61 GHz The Common-Base Amplifier Analysis of the common-base amplifier resembles that of the common-gate circuit that we analysed previously, with one major difference: The BJT has a finite , and its base conducts signal current, which gives rise to the resistance r between base and emitter, looking into the base. Figure 17(a) shows the basic circuit for the active-loaded commonbase amplifier without any details of biasing. Note that resistance RL represents the 34

combination

FIGURE 17 (a) Active-loaded common-base amplifier, (b) Small-signal analysis performed directly on the circuit diagram with the BJT T model (c) Small-signal analysis with the output open-circuited. load resistance, if any, and the output resistance of the current source that realizes the active load I. Figure 17(b) shows the small-signal analysis performed directly on the circuit with the T model of the BJT used implicitly. The analysis is very similar to that for the MOS case except that, as a result of the finite base current, vi /r, the current io is related to ii by io = ii -vi/r
. (68)
Of

It can be shown that, neglecting rx, the input resistance at the emitter, Rin is given by
Wkt, ii = vi/re +iro (from the fig. above) . (69) ii = vi/re +(vi-vo)/ro ii = vi/re +vi/ro ioRL/ro ii =vi/re +vi/ro (RL/ro)(ii vi/r) Remember: r=(1+)re

We observe that setting = reduces this expression to that of the MOS case (Eq.39) except that here gmb = 0. Note that, for = , = 1, and re = /gm = 1 /gm. With a slight approximation, the expression in Eq. (69) can be written as
. (70)

35

Note that setting ro = yields Rin = re . Also, for RL = 0, Rin = re. The value of Rin increases as RL is raised, reaching a maximum of ( + 1 )re = r for RL = , that is, with the amplifier operating open-circuited (see Fig. 17c). For RL/( + 1) < r0, Eq. (70) can be approximated as

. (71)

where A0 is the intrinsic gain gmro. This equation is very similar to Eq. (43) in the MOSFET case. The open-circuit voltage gain and input resistance can be easily found from the circuit in Fig. 17(c) as Avo = 1 + gmr0= l + Ao
. (72)

which is identical to Eq. (41) for the MOSFET except for the absence of gmb. The input resistance with no load, Ri , is Ri = r
. (73)

as we have already found out from Eq. (70). As in the MOSFET case, the output resistance Ro is given by Ro = r o
. (74)

The output resistance including the source resistance Re can be found by analysis of the circuit in Fig. 18 to be Rout = ro + (1+ gmro) R'e Where R'e = Re II r

wkt, ix = v/Re v=ix Re vx = v + (ix +gmv)ro . (75) v = v(1 +g r ) + i r x m o x o vx = ix Re (1 +gmro) + ixro Rout=vx/ix = Re (1 +gmro) + ro

Note that the formula in Eq. (75) is very similar to that for the MOS case, namely Eq. (58). However, there are two differences: First, gmb is missing, and second, R'e =Re II r

36

FIGURE 18 Analysis of the CB circuit to determine Rout. Observe that the current ix that enters the transistor must equal the sum of the two currents v/r and v/Re that leave the transistor, that is, ix = v/r + v/Re. Replaces Rs. The reason r appears in the BJT formula is the finite of the BJT. The expression in Eq. (75) can also be written in terms of the open-circuit voltage gain A vo as Rout = ro + Avo R'e
. (76)

which is the BJT counterpart of the MOS expression in Eq. (59). Another useful form for Rout can be obtained from (75), Rout= R'e +(1+gmR'e)r0
. (77)

which is the BJT counterpart of the MOS expression in Eq. (61). In Eq. (77) the second term is much larger than the first, resulting in the approximate expression Rout (1 + gmR'e)r0
. (78)

which corresponds to Eq. (62) for the MOS case. Equation (78) clearly shows that the inclusion of an emitter resistance Re increases the CB output resistance by a factor (1 + gmR'e). Thus, as Re is increased from 0 to , the 37

output resistance increases from ro to (1 +gmr)r0 = (1 + )r0 = r0. This upper limit on the value of Rout dictated by the finite of the BJT, has no counterpart in the MOS case and will have important implications for circuit design. We note that for Re < r, Eq. (78) can be approximated by Rout = (1 + gmRe)ro
. (79)

A useful summary of the formulas for Rin and Rout is provided in Fig. 19. The results above can be used to obtain the overall voltage gain Gv as

. (80)

. (81)

FIGURE 19 Input and output resistances of the CB amplifier. The high-frequency response of the common-base circuit can be evaluated in a manner similar to that used for the MOSFET.

38

EXERCISE Consider the CB amplifier of Fig. 17(a) for the case I = 1 mA, = 100, VA = 100 V, RL = 1 M and Re = 1 k. Find Rin, Avo, Ro, Av, Rout and Gv. Also find vo ,if vsig is a 5-mV peak sine wave. Ans. 250 ; 4001 V/V; 100 k; 3637 V/V; 2.97 M, 722 V/V; 3.61 V peak Note: The common-gate and common-base circuits have open-circuit voltage gains Avo almost equal to those of the common-source and common-emitter circuits. Their input resistance, however, is much smaller and their output resistance much larger than the corresponding values for the CS and CE amplifiers. These two properties, though not usually desirable in voltage amplifiers, make the CG and CB circuits suitable as current buffers. The absence of the Miller effect makes the high-frequency response of the CG and CB circuits far superior to that of the CS and CE amplifiers. The most significant application of the CG and CB circuits is in a configuration known as the cascode amplifier, which we shall study next. THE CASCODE AMPLIFIER A common-gate (common-base) amplifier stage in cascade with a common source (common-emitter) amplifier stage, results in a very useful and versatile amplifier circuit known as the cascode configuration and has been in use in a wide variety of technologies for over three quarters of century. The basic idea behind the cascode amplifier is to combine the high input resistance and large transconductance achieved in a common-source (common-emitter) amplifier with the current-buffering property and the superior high-frequency response of the commongate (common-base) circuit. The cascode amplifier can be designed to obtain a wider bandwidth but equal dc gain as compared to the common-source (common-emitter) amplifier. Alternatively, it can be designed to increase the dc gain while leaving the gainbandwidth product unchanged. In many applications the cascade amplifier is thought of and treated as a single-stage amplifier though it is formed by cascading two amplifier stages.

39

The MOS Cascode Figure 20(a) shows the MOS cascode amplifier. Here transistor Q1 is connected in the common-source configuration and provides its output to the input terminal (i.e., source) of transistor Q2. Transistor Q2 has a constant dc voltage, VB1AS, applied to its gate. Thus the signal voltage at the gate of Q2 is zero, and Q2 is operating as a CG amplifier with a constant-current load, I. Obviously both Q1 and Q2 will be operating at DC drain currents equal to I. As in previous cases, feedback in the overall circuit that incorporates the cascode amplifier establishes an appropriate dc voltage at the gate of Q1 so that its drain current is equal to I. Also, the value of VBIAS has to be chosen so that both Q1 and Q2 operate in the saturation region at all times. Small-Signal Analysis : In response to the input signal voltage vi the common-source transistor Q1 conducts a current signal gm1vi, in its drain terminal and feeds it to the source terminal of the common-gate transistor Q2, called the cascode transistor. Transistor Q2 passes the signal current gm1vi on to its drain, where it is supplied to a load resistance RL (not shown in fig. 20) at a very high output resistance, Rout. The cascode transistor Q2 acts in effect as a buffer, presenting a low input resistance to the drain of Q1 and providing a high resistance at the amplifier output. Characteristic parameters: In Fig. 20(b) shows the cascode circuit prepared for smallsignal analysis and with a resistance RL shown at the output. RL is assumed to include the output resistance of current source I as well as an actual load resistance, if any. The diagram also indicates various input and output resistances obtained using the results of the analysis of the CS and CG amplifiers in previous sections. Note in particular that the CS transistor Q1 provides the cascode amplifier with an infinite input resistance. Also, at the drain of Q1 looking "downward, see the output resistance of the CS transistor Q1, ro1. Looking "upward," we see the input resistance of the CG transistor Q2,
(82)

(83)

(84)

40

FIGURE 20 (a) The MOS cascode amplifier. (b) The circuit prepared for small signal analysis with various input and output resistances indicated. (c) The cascode with the output open-circuited. Figure 20 (b) also indicates that the output resistance of the cascode amplifier, R out, is given by Rout = ro2 + Avo2ro1
(85)

This has been obtained using the formula in Eq. (59) and noting that the resistance Rs in the source of the CG transistor Q2 is the output resistance ro1 of Q1. Substituting for Avo2 from Eq. (83) into Eq.(85) yields. Rout = ro2 + [1+(gm2 + gmb2) ro2] ro1 Approximate value can be written as, Rout = (gm2 ro2) ro1 = A0ro1
(87) (86)

Thus the cascode transistor increases the level of output resistance by a factor equal to its intrinsic gain, from ro1 of the CS amplifier to Aoro1.

41

From the cascode amplifier circuit in Fig. 20 (b), it is clear that when a signal source vsig with an internal resistance Rsig is connected to the input, the infinite input resistance of the amplifier causes. vi = vsig Thus, Gv =Av And the amplifier is unilateral; thus Ro = Rout The open circuit voltage gain Avo of the cascode amplifier can be easily determined from the circuit in Fig. 20(c), which shows the amplifier operating with the output open circuited. Since Rin2 will be infinite, the gain of the CS stage Q1 will be

The signal vo1 will be amplified by the open circuit voltage gain Avo2 of the CG transistor Q2 to obtain. vo = Avo2vo1 Thus, Avo = -A01Avo2 -A01A02
(88)

And for the usual case of equal intrinsic gains, Avo becomes, Avo = -A2o = - (gmro)2
(89)

We conclude that cascading increases the magnitude of the open-circuit voltage gain from Ao of the CS amplifier to Ao2. We are now in a position to derive an expression for the short circuit transconductance Gm of the cascode amplifier. From the definitions we may write, Avo = -GmRo 42
(90)

Substituting for Avo from Eq. (88) and for Ro = Rout from Eq. (85) gives, for Gm,

(91)

This confirms the value obtained earlier in the qualitative analysis. The operation of the cascode amplifier is now clear: In response to vi the CS transistor provides a drain current gm1vi, which the CG transistor passes on to RL and, in the process, increases the output resistance by Ao. It is the increase in Rout to A0ro that increases the open-circuit voltage gain to (gm)(Aor0) = A2o . Figure 21 provides a useful summary of the operation: Two output equivalent circuits are shown in Fig. 21(a) and (b), and an equivalent circuit for determining the voltage gain of the CS stage Q1 is presented in Fig. 21(c). The voltage gain Av can be found from either of the two equivalent circuits in Fig. 21(a) and (b). From Fig. 21(a) we may write,
(92)

We see that if we are to realize the large gain of which the cascode is capable, resistance RL should be large. At the very least, RL should be of the order of A0ro. For
(93)

RL = A0ro,

Av= -A2o/2

The gain of the CS stage is important because its value determines the Miller effect in that stage. From the equivalent circuit in Fig. 21(c), neglecting gmb,

(94)

43

Figure 21 (a) & (b) Two equivalent circuits for the output of cascode amplifier. (c) Equivalent circuit for determining the voltage gain of the CS stage.

Thus we see that when RL is large and the cascode amplifier is realizing a substantial gain, a good part of the gain is obtained in the CS stage. This is not good news considering the Miller effect, as we shall see shortly. To keep the gain of the CS stage relatively low. RL has to be lowered. For instance, for RL = ro, Eq. (94) indicates that

However, in this case the DC gain of the cascode is drastically reduced, as can be seen by substituting RL = ro in Eq. (92), 44

 (95)

That is, the gain of the cascode becomes equal to that realized in a single CS stage. However, it does not mean that the cascode configuration (in this case) is not useful. Frequency Response of the MOS Cascode Figure 22 shows the cascode amplifier with all transistor internal capacitances indicated. Also included is a capacitance CL at the output node to represent the combination of Cdb2, the input capacitance of a succeeding amplifier stage (if any), and a load capacitance (if any). Cdb1 and Cgs2 appear in parallel, and we shall combine them in the following analysis. Similarly, CL and Cgd2 appear in parallel and will be combined. The easiest and, in fact, quite insightful approach to determining the 3-dB frequency fH is to use the open-circuit time-constants method. Capacitance Cgs1 sees a resistance Rsig.

Capacitance Cgd1 sees a resistance Rgd1, which can be obtained by adapting the formula in Eq. (10) to give Rgd1 = (1 + gm1Rd1) Rsig + Rd1
(96)

where Rd1, the total resistance at D1 is given by Eq. (84).

45

FIGURE 22 The cascode circuit with the various transistor capacitances indicated. Capacitance (Cdb1 + Cgs2) sees a resistance Rd1. Capacitance (CL + Cgd2) sees a resistance (RL II Rout). With the resistances determined, the effective time constant H can be computed as H = Cgs1Rsig + Cgd1 [1 + gm1Rd1)Rsig + Rd1] + (Cdb1 + Cgs2) Rd1 + (CL + Cgd2) (RL II Rout) and the 3-dB frequency fH as
(97)

To see what limits the high-frequency gain of the MOS cascode amplifier, we rewrite Eq. (97) in the form H = Rsig [Cgs1 + Cgd1 (1 + gm1Rd1)] + Rd1 (Cgd1 + Cdb1 + Cgs2) + (RL II Rout) (CL + Cgd2)
(98)

46

In the case of a large Rsig, the first term can dominate, especially if the Miller multiplier (1 +gm1Rd1) is large. This in turn happens when the load resistance RL is large (of the order of A0ro), causing Rin2 to be large and requiring the first stage, Q1 to provide a large proportion of the gain. It follows that when Rsig is large, to extend the bandwidth we have to lower RL to the order of r0. This in turn lowers Rin2 and hence Rdl and renders the Miller effect insignificant. However, the dc gain of the cascode will then be A0. Thus, while the dc gain will be the same as (or a little higher than) that achieved in a CS amplifier, the bandwidth will be greater. In the case when Rsig is small, the Miller effect in Q1, will not be of concern. A large value of RL (on the order of A0ro) can then be used to realize the large dc gain possible with a cascode amplifierthat is, a dc gain on the order of A02. Equation (98) indicates that in this case the third term will usually be dominant. To pursue this point a little further, consider the case Rsig = 0, and assume that the middle term is much smaller than the third term. It follows that H = (CL + Cgd2) (RL IIRout) And the 3 dB frequency becomes
(100) (99)

Which is of the same form as the formula for the CS amplifier with Rsig = 0. Here, however, (RL II Rout) is larger by a factor of about A0 compared to RL in CS amplifier. Thus the fH of the cascode will be lower than that of the CS amplifier by the same factor A0. Figure 23 shows a sketch of the frequency response of the cascode and of the corresponding common-source amplifier. We observe that in this case cascoding increases the dc gain by a factor Ao while keeping the unity-gain frequency unchanged at
(101)

47

FIGURE 23 Effect of cascoding on gain and bandwidth in the case Rsig = 0. Cascoding can increase the dc gain by the factor A0 while keeping the unity-gain frequency constant. Note that to achieve the high gain, the load resistance must be increased by the factor AO. This example illustrates the advantages of cascoding by comparing the performance of a cascode amplifier with that of a CS amplifier in two cases: a) The resistance of the signal source is significant, Rsig = 10 k. b) Rsig is negligibly small.

48

Assume all MOSFETs have W/L of 7.2 m/0.36 m and are operating at ID = 100 A, gm = 1.25 mA/V, = 0.2, r0 = 20 k, Cgs = 20 fF, Cgd = 5fF,Cdb= 5 fF, and CL (excluding Cdb= 5 fF. For case (a), let RL= r0= 20 k for both amplifiers. For case (b), let RL = r0 = 20 k for the CS amplifier and RL = Rout for the cascode amplifier. For all cases, determine Av, fH and ft.

49

50

Thus cascoding increases the dc gain from 12.5 to 388 V/V. The unity-gain frequency (i.e., gain-bandwidth product), however, remains nearly constant. The BJT Cascode Figure 24(a) shows the BJT cascode amplifier. The circuit is very similar to the MOS cascode, and the small-signal analysis follows in a similar way, as shown in Fig. 24(b). The various input and output resistances have been shown. Unlike the MOSFET cascode, which has an infinite input resistance, the BJT cascode has an input resistance of r1 (neglecting rx). The formula for Rin2 is the one we found in the analysis of the commonbase circuit. The output resistance Rout =2ro2 found

51

FIGURE 24 (a) The BJT cascode amplifier, (b) The circuit prepared for smallsignal analysis with various input and output resistances indicated. Note that rx is neglected, (c) The cascode with the output open-circuited. by substituting Re2 = rol in Eq. (79) and making the approximation that gmro > . Recall that ro is the largest output resistance that a CB transistor can provide. The open-circuit voltage gain Avo and the no-load input resistance Ri can be found from the circuit in Fig. 24(c), in which the output is open-circuited. Observe that Rin2= r2 which is usually much smaller than r01. As a result the total resistance between the collector of Q1 and ground is approximately r2; thus the voltage gain realized in the CE transistor Q1 is gm1r2 = -. Recalling that the open-circuit voltage gain of a CB amplifier is (l + gmro) = Ao . We see that voltage gain Avo is Avo = - Ao
. (102)

Putting all of these results together we obtain for the BJT cascode amplifier the equivalent circuit shown in Fig. 25(a). We note that compared to the common-emitter amplifier, cascoding increases both the open-circuit voltage gain and the output resistance by a factor equal to the transistor . This should be contrasted with the factor A0 encountered in the MOS cascode. The equivalent circuit can be easily converted to the transconductance form shown in Fig.25(b). It shows that the short-circuit transconductance Gm of the cascode amplifier is equal to the transconductance gm of the BJTs. This should have been expected since Q1 provides a current gm1 vi to the emitter of the cascode transistor Q2, which in turn passes the current on (assuming 2 =1) to its collector and to the load resistance RL. In the process the cascode transistor raises the resistance level from ro at the collector of Q1 to r0 at the collector of Q2. This is the by52

now-familiar current-buffering action of the common-base transistor. The voltage gain of the CE transistor Q1 can be determined from the equivalent circuit in fig-25(c). The resistance between the collector of Q1 and ground is the parallel equivalent

53

FIGURE : 25 (a) Equivalent circuit for the cascode amplifer in terms of the open circuit voltage gain Avo = - Ao. (b) Equivalent circuit in terms of the overall short circuit transconductance Gm = gm . (c) Equivalent circuit for determining the gain of the CE stage Q1.

FIGURE 26: Determining the frequency response of the BJT cascode amplifier. Note that in addition to the BJT capacitances C and C the capacitance between the collector and the substrate Ccs for each transistor are also included. of the output resistance of Q1, ro, and the input resistance of the CB transistor, Q2, namely Rin2 . Note that for RL < ro the latter reduces to re, as expected. However, Rin2 increases as RL is increased. Of particular interest is the value of Rin2 obtained for RL =ro, namely Rin2 = r/2. It follows that for this value of RL the CE stage has a voltage gain of -/2. Finally, in Fig. 26 the circuit and the formulas for determining the high-frequency response of the bipolar cascade are given. The analysis is similar to that studied in the MOSFET case. A Cascode Current Source We know that to realize the high voltage gain of which the cascode amplifier is capable the load resistance RL must be at least of the order of A0ro, for the MOSFET cascode or ro for the bipolar cascode. However, that RL includes the output resistance of the circuit which implements the current-source load I. This implies that the current-source must have output resistance that is at least Aor0 for the MOS case (ro for the BJT case). This means that the simple current-source circuits studied earlier cannot be considered, since 54

their output resistances are equal to r0. Fortunately, there is a conceptually simple and

FIGURE 27 A cascode current-source.

effective solutionnamely, applying the cascoding principle to the current-source implementation. This is illustrated in Fig. 27, where Q1 is the current-source transistor and Q2 is the cascode transistor. VBlAS1 , is a DC voltage that is chosen so that Q1 provides the required value of I. VB1AS2 is chosen to keep Q2 and Q1, in saturation at all times. While the resistance looking into the drain of Q1 is rol, the cascode transistor Q2 multiplies this resistance by (gm2ro2) and provides an output resistance for the current source given approximately by Ro = (gm2ro2)ro1
. (103)

Similar arrangement can be used in the bipolar case also. Double Cascoding The essence of the operation of the MOS cascode is that the CG cascode transistor Q2 multiplies the resistance in its source, which is r0 of the CS transistor Q1, by its intrinsic gain A02 to provide an output resistance A02r01. It follows that we can increase the output resistance further by adding another level of cascoding, as shown in Fig. 28. Here another CG transistor Q3 is added, and this results in increased output resistance

55

FIGURE 28 Double cascoding.

by a factor Ao3 .Thus the output resistance of this double-cascode amplifier is A02ro . An additional bias voltage has to be generated for the additional cascode transistor Q3. A drawback of double cascoding is that an additional transistor is now stacked between the power supply rails. Furthermore, since we are now dealing with output resistances on the order of A0ro, the current source I will also need to be implemented using a double cascode which adds yet one more transistor to the stack. It is appropriate to recall that in modern CMOS process technologies VDD is only a bit more than 1V. Note that, since the largest output resistance possible in a bipolar cascode is r0, adding another level of cascoding does not provide any advantage. The Folded Cascode To avoid the problem of stacking a large number of transistors across a low-voltage power supply, one can use a PMOS transistor for the cascode device, as shown in Fig. 29. Here as before, the NMOS transistor Q1 is operating in the CS configuration, but the CG stage is implemented using the PMOS transistor Q2. An additional current-source I2 is needed to bias Q2 and provide it with its active load. Note that Q1 is now operating at a bias current of (I1 I2). Finally, a DC voltage VBIAS is needed to provide an appropriate dc level for the gate of the cascode transistor Q2. Its value has to be selected so that Q2 and Q1 operate in the saturation region. 56

The small-signal operation of the circuit in Fig. 29 is similar to that of the NMOS cascode. The difference here is that the signal current gmvi is folded down and made to flow into the source terminal of Q2, which gives the circuit the name folded cascode. The folded cascode is a very popular building block in CMOS amplifiers.

FIGURE 29 The folded cascode BiCMOS Cascodes The circuit designer can combine bipolar and MOS transistors in circuit configurations that take advantage of the unique features of each. As an example, Fig. 30 shows two possibilities for the BiCMOS implementation of the cascode amplifier. In the circuit of Fig. 30(a) a MOSFET is used for the input device, thus providing the cascode with an infinite input resistance. On the other hand, a bipolar transistor is used for the cascode device, thus providing a larger output resistance

57

FIGURE 30: BiCMOS cascodes than is possible with a MOSFET cascode. This is because of the BJT is usually larger than Ao of the MOSFET and because ro of the BJT is much larger than r0 of modern submicron MOSFETs. Also, the bipolar CB transistor provides a lower input resistance Rin2 than is usually obtained with a CG transistor, especially when RL is low. The result is a lower total resistance between the drain of Q1 and ground and hence a reduced Miller effect in Q1. The circuit in Fig. 30(b) utilizes a MOSFET to implement the second level of cascoding in a bipolar cascode amplifier. The need for a MOSFET stems from the fact that while the maximum possible output resistance obtained with a BJT is ro, there is no such limit with the MOSFET, and indeed, Q3 raises the output resistance by the factor A03.

58

THE CS AND CE AMPLIFIERS WITH SOURCE (EMITTER) DEGENERATION Inserting a relatively small resistance (i.e. a small multiple of 1/gm) in the source of a CS amplifier (the emitter of a common-emitter amplifier) introduces negative feedback into the amplifier stage. As a result this resistance provides the circuit designer with an additional parameter that can be effectively utilized to obtain certain desirable properties as a trade-off for the gain reduction that source (emitter) degeneration causes. The CS Amplifier with a Source Resistance Figure 31(a) shows an active-loaded CS amplifier with a source resistance Rs. Note that a signal vbs will develop between body and source, and hence the body effect should be taken into account in the analysis. The circuit, prepared for small-signal analysis and with a resistance RL shown at the output, is presented in Fig. 31(b). To determine the output resistance Rout, we reduce vi, to zero, which makes the circuit identical to that of a CG amplifier. Therefore we can obtain Rout by using Eq. (58) as Rout = r0 + [l+(gm + gmb)r0] Rs (104) which for the usual situation (gm + gmb)ro > 1 reduces to Rout ro [1+(gm + gmb)Rs]
(105)

The open-circuit voltage gain can be found from the circuit in Fig. 31(c). Noting that the current in Rs must be zero, the voltage at the source, vs, will be zero and thus vgs = vi and vbs = 0, resulting in i = gmvgs

59

FIGURE 31 (a) A CS amplifier with a source-degeneration resistance Rs (b) Circuit for small signal analysis. (c) Circuit with the output open to determine Avo . (d) Output equivalent circuit (e) Another output equivalent circuit in terms of Gm. and vo = -iro = -gmrovgs = -gmrovi Thus Avo = -gmro = -Ao
(106)

In other words, the resistance Rs has no effect on Avo. Utilizing Avo=-A0 and Rout from Eq. (105) gives us the amplifier output equivalent circuit shown in Fig. 31(d). An alternative equivalent circuit in terms of the short-circuit transconductance Gm is shown in Fig. 31(e), where Gm can be found from

60

 (107)

The effect of Rs is thus obvious: Rs reduces the amplifier transconductance and increases its output resistance by the same factor: [ 1 + (gm + gmb)Rs]. The voltage gain Av can be found as
(108)

Thus, if RL is kept unchanged, AV will decrease, which is the price paid for the performance improvements obtained when Rs is introduced. One such improvement is in the linearity of the amplifier. This comes about because only a fraction vgs of the input signal vi now appears between gate and source. Derivation of an expression for vgs/vi is significantly complicated by the inclusion of r0. The derivation should be done with the MOSFET equivalent-circuit model explicitly used. The result is
(109)

which for ro > RL reduces to the familiar relationship

(110)

Thus the value of Rs can be used to control the magnitude of vgs so as to obtain the desired linearityat the cost of gain reduction. Frequency Response Another advantage of source degeneration is the ability to broaden the amplifier bandwidth. Figure 32(a) shows the amplifier with the internal capacitances Cgs and Cgd indicated. A capacitance CL that includes the MOSFET capacitance Cdb is also shown at the output. The method of open-circuit time constants can be employed to obtain an estimate of the 3-dB frequency fH. We observe in Fig. 32(b) the circuit for determining Rgd, which is the resistance seen by Cgd, We observe that Rgd can be determined by simply adapting the formula in Eq. (10) to the case with source 61

degeneration as follows: Rgd= Rsig (1+ GmRL) + RL where RL= RLII Rout
(112) (111)

The formula for RCL can be simply RCL = RLIIRout =RL

(113)

The formula for Rgs is very difficult to derive, and the derivation should be performed with the hybrid- model explicitly utilized. The result is
(114)

When Rsig is relatively large, the frequency response will be dominated by the Miller multiplication of Cgd. Another way for saying this is that CgdRgd will be the largest of the three open-circuit time constants that result in H.

62

FIGURE 32 (a) The CS amplifier circuit, with a source resistance Rs , prepared for frequency response analysis, (b) Determining the resistance Rgd seen by the capacitance Cgd. H = CgsRgs + CgdRgd + CLRCL H CgdRgd
.. (116) .. (115)

and correspondingly to obtain fH as

.. (117)

63

1 Now, as Rs is increased, the gain magnitude, |AM| = Gm RL will decrease, causing Rgd to decrease (Eq.111), which in turn causes fH to increase (Eq.117). To highlight the trade-off between gain and bandwidth that Rs affords the designer, let us simplify the expression for Rgd in Eq. (111) by assuming that GmRL > 1, and GmRsig>1 Rgd = GmRLRsig= |AM| Rsig
.. (118)

which can be substituted in Eq. (117) to obtain

.. (119)

which very clearly shows the gain-bandwidth trade-off. The gain-bandwidth product remains constant at Gain-bandwidth product
.. (120)

In practice, however, the other capacitances will play a role in determining fH, and ft will decrease somewhat as Rs is increased. The CE Amplifier with an Emitter Resistance Emitter degeneration is even more useful in the CE amplifier than source degeneration is in the CS amplifier. This is because emitter degeneration increases the input resistance of the CE amplifier. Figure 33 (a) shows an active-loaded CE amplifier with an emitter resistance Re usually in the range of 1 to 5 times re. Figure 33(b) shows the circuit for determining the

64

Figure 33 : an active-loaded CE amplifier with an emitter resistance Input resistance Rln, which due to the presence of ro will depend on the value of RL. With the help of the analysis shown in Fig. 33(b), we can express the output voltage v0 as
.. (122)

we can also express vo as

.. (123)

Equating these two expressions of vo yields an equation in vi and i, which can be rearranged to obtain
.. (124) .. (125)

Usually RL is on the order of r0; thus RL/( + 1) < r0. Also, Re < ro. Taking account of these two conditions enables us to simplify the expression for Rin to
.. (126)

This expression indicates that the presence of ro reduces the effect of Re on increasing Rin . This is because ro shunts away some of the current that would have flowed through .. (127) Re. For example, for RL = r0, Rin = ( + 1)(re + 0.5Re ). 65

To determine the open-circuit voltage gain Avo, we utilize the circuit shown in Fig. 33(c). Analysis of this circuit is straightforward and can be shown to yield Avo= -gmr0 .. (128) That is, the open-circuit voltage gain obtained with a relatively small Re (i.e., of the order of re) remains very close to the value without Re. The output resistance Ro is identical to the value of Rout that we derived for the CB circuit (Eq. 78), Ro=ro(1+gmRe)
.. (129)

where R'e = Re // r. Since Re is on the order of re, Re is much smaller than r and R'e = Re. Thus,
.. (130)

R0 = ro(1+gmRe) The expressions for Rin, Avo ,and Ro in Eqs. (127), (128), and (130), respectively, can be used to determine the overall voltage gain for given values of source resistance and load resistance. Finally, we should mention that Avo and Ro can be used to find the effective short-circuit transconductance Gm ,of the emitter-degenerated CE amplifier as follows:
.. (131)

.. (132)

The high-frequency response of the CE amplifier with emitter degeneration can be found in a manner similar to that presented above for the CS amplifier. In summary, including a relatively small resistance Re (i.e.. a small multiple of re) in the emitter of the active-loaded CE amplifier reduces its effective transconductance by the factor ( 1 + gmRe) and increases its output resistance by the same factor, thus leaving the open-circuit voltage gain approximately unchanged. The input resistance Rin is increased by a factor that depends on Re and that is somewhat lower than ( 1 + gmRe). Also, including Re reduces the severity of the Miller effect and correspondingly increases the amplifier bandwidth. Finally, an emitter-degeneration resistance Re increases the linearity of the amplifier. THE SOURCE AND EMITTER FOLLOWERS 66

In the following discussion we consider their IC versions of source and emitter followers, with a special emphasis on their high-frequency response. The Source Follower Figure 34(a) shows an IC source follower biased by a constant-current source I, which is usually implemented using an NMOS current mirror. The source follower would generally be part of a larger circuit that determines the dc voltage at the transistor gate. Here, vi is the input signal appearing at the gate and RL represents the combination of a load resistance and the output resistance and the current-source I. The low-frequency small-signal model of the source follower is shown in Fig- 34(b)Observe that ro appears in parallel with RL and thus can be combined with it. Also, the controlled current-source gmbvbs feeds its current into the source terminal, where the voltage is -vbs. Thus we can use the source-absorption theorem to replace the current source with a resistance 1 /gmb between the source and ground, this can then be combined with RL and r0 . With these two simplifications, the equivalent circuit takes the form shown in Fig. 34(c), where
.. (133)

We now write the output voltage v0 as vo = gmvgsRL vgs is given by, vgs = vi vo
.. (134)

67

FIGURE 34 (a) An IC source follower, (b) Small-signal equivalent-circuit model of the source follower. (c) A simplified version of the equivalent circuit (d) Determining the output resistance of the source follower. Equations (133) and (134) can be combined to obtain the voltage gain

.. (135)

which, as expected, is less than unity. To obtain the open-circuit voltage gain, we set RL in Eq. (133) to , which reduces R'L to ro II (1 /gmb). Substituting this value for R'L in Eq. (135) gives

68

which, for the usual case where (gm + gmb)r0 > 1 simplifies .. to (136)
.. (137)

Thus the highest value possible for the voltage gain of the source follower is limited to l/ (l +), which is typically 0.8 V/V to 0.9 V/V. Finally, we can find the output resistance Ro of the source follower either using the equivalent circuit of Fig. 34(c) or by inspection of the circuit in Fig. 34 (d) as

.. (138)

which can be approximated as Ro = 1/[(1+)gm]

.. (140)

Similar to the discrete source follower, the IC source follower can be used as the output stage of a multistage amplifier to provide a low output resistance for driving lowimpedance loads. It is also used to shift the dc level of the signal by an amount equal to VGS. Frequency Response of the Source Follower A major advantage of the source follower is its excellent high-frequency response. This comes about because, as we shall now see, none of the internal capacitances suffers from the Miller effect. Figure 35(a) shows the high-frequency equivalent circuit of a source follower fed with a signal Vsjg from a source having a resistance Rsig. In addition to the MOSFET capacitances Cgs and Cgd, a capacitance CL is included between the output node and ground to account for the source-to-body capacitance Csb as well as any actual load capacitance. The simplifications performed above on the low-frequency equivalent circuit can be applied to the high-frequency model of Fig. 35(a) to obtain the equivalent circuit in Fig. 35(b), where RL is given by Eq. (133). Although one can derive an expression for the transfer function of this circuit, the resulting expression will be too complicated to yield insight regarding the role that each of the three capacitances plays. Rather, we shall first determine the location of the transmission zeros and then use the method of open-circuit time constants to estimate the 3-dB frequency, f3dB.

69

Although there are three capacitances in the circuit of Fig. 35(b), the transfer function is of the second order. This is because the three capacitances form a continuous loop. To determine the location of the two transmission zeros, refer to the circuit in Fig. 35(b), and note that v0 is zero at the frequency at which CL has a zero impedance and thus acts as a short circuit across the output, which is or s = . Also, vo will be zero at the value of s that causes the current into the impedance RL II CL to be zero. Since this current is (gm + sCgs)vgs -the transmission zero will be at s = sz, where
.. (142)

That is, the zero will be on the negative real-axis of the s-plane with a frequency
.. (143)

FIGURE 35 Analysis of the high-frequency response of the source follower (a) Equivalent circuit (b) simplified equivalent circuit and (c) determining the resistance Rgs seen by Cgs Recalling that the MOSFET's T = gm /(Cgs + Cgd) and that Cgd < Cgs, we see that z, will be very close to T 70

fz = f T

.. (144)

Next, we turn our attention to the poles. Specifically, we will find the resistance seen by each of three capacitances Cgd, Cgs, and CL and then compute the time constant associated with each. With Vsig set to zero and Cgs and CL assumed to be open circuited, we find by inspection that the resistance Rgd seen by Cgd is given by Rgd = Rsig
.. (145)

Next, we consider the effect of Cgs The resistance Rgs seen by Cgs can be determined by straightforward analysis of the circuit in Fig. 35(c) to obtain
.. (146)

We note that the factor (1 + gmRL) in the denominator will result in reducing the effective resistance with which Cgs interacts. In the absence of the two other capacitances, Cgs together with Rgs introduce a pole with frequency l/2CgsRgs. Finally, it is easy to see from the circuit in Fig. 35(b) that CL interacts with RL // Ro that is. RCL = RL II RO
.. (147)

Usually, R0 (Eq. 138) is low. Thus RCL will be low. and the effect of CL will be small. Nevertheless, all three time constants can be added to obtain H and hence fH,
.. (148)

The Emitter Follower Figure 36(a) shows an emitter follower suitable for IC fabrication. It is biased by a constant-current source, I. However, the circuit that sets the DC voltage at the base is not shown. The emitter follower is fed with a signal Vsig from a source with resistance Rsig. The resistance RL shown at the output, includes the output resistance of current source I as well as any actual load resistance. Analysis of the emitter follower of Fig. 36(a) will give low-frequency gain, Av = RL/ (RL + re) (almost equal to 1) .. (149) Input resistance, Rin = (1+)(RL+re) .. (150) 71
Here ro is parallel combination of output resistances of current source transistor and amplifying transistor.

.. (151) Output resistance, Rout = ro(r +Rsig) / [(r +Rsig) + (1+)r o]

The circuit can be used as voltage buffer because of unity gain, high input resistance and low output resistance. Figure 36(b) shows the high-frequency equivalent circuit. Lumping ro together with RL and rx together with Rsig and making a slight change in the way the circuit is drawn results in the simplified equivalent circuit shown in Fig. 36(c). We will follow a procedure for the analysis of this circuit similar to that used above for the source follower. Specifically, to obtain the location of the transmission zero, note that V o will be zero at the frequency sz for which the current fed to R'L is zero:
.. (152)

FIGURE : 36 (a) Emitter follower (b) High frequency equivalent circuit (c) Simplified equivalent circuit which is on the negative real-axis of the s-plane and has a frequency 72

.. (154)

This frequency is very close to the unity gain frequency T of the transistor. The other transmission zero is at s =. This is because at this frequency, C acts as a short circuit, making V zero, and hence Vo will be zero. Next, we determine the resistances seen by C and C. For C , the resistance it sees, R, is the parallel equivalent of Rsig and the input resistance looking into B; that is,
.. (155)

Equation (155) indicates that R will be smaller than Rsig and since c is usually very small, the time constant CR will be correspondingly small. The resistance R seen by C can be determined using an analysis similar to that employed for the determination of Rgs in the MOSFET case. The result is
.. (156)

We observe that the term RL/re will usually make the denominator much greater than unity thus rendering R rather low. Thus, the time constant CR will be small. The end result is that the 3-dB frequency fH of the emitter follower will usually be very high. (6.184) fH = 1/[2 (CR + CR)]
.. (157)

SOME USEFUL TRANSISTOR PAIRINGS The cascode configuration studied above combines CS and CG MOS transistors (CE and CB bipolar transistors) to great advantage. The key to the superior performance is that the transistor pairing is done in a way that maximizes the advantages and minimizes the shortcomings of each of the two individual configurations. In this section we study a number of other such transistor pairings. In each case the transistor pair can be thought of as a compound device; thus the resulting amplifier may be considered as a single stage.

73

The CD-CS, CC-CE and CD-CE Configurations Figure 37(a) shows an amplifier formed by cascading a common-drain (source-follower) transistor Q1 with a common-source transistor Q2. As should be expected, the voltage of the circuit will be a little lower than that of the CS amplifier. The advantage of this circuit

FIGURE 37 (a) CD-CS amplifier (b) CC-CE amplifier (c) CD-CE amplifier configuration, however, lies in its bandwidth, which is much wider than that obtained in a CS amplifier. To see how this comes about, note that the CS transistor Q2 will still exhibit a Millers effect that results in a large input capacitance, Cin2, between its gate and ground. However, the resistance that this capacitance interacts with will be much lower than Rsig the buffering action of the source follower causes a relatively low resistance, approximately equal to a l/(gm1 + gmb1), to appear between the source of Q1 and ground across Cin2. The bipolar counterpart of the CD-CS circuit is shown in Fig. 37(b). Besides achieving a wider bandwidth than that obtained with a CE amplifier, the CC-CE configuration has an important additional advantage: The input resistance is increased by a factor equal to (1 + 1). Finally, we show in Fig. 37(c) the BiCMOS version of this circuit type. Observe that Q1 provides the amplifier with an infinite input resistance. Also, note that Q2 provides the amplifier with a high gm as compared to that obtained in the MOSFET circuit in Fig. 37(a) and hence high gain. EXAMPLE

74

Consider a CC-CE amplifier such as that in Fig. 37(b) with the following specifications: I1 = I2 = 1mA and identical transistors with = 100, fT = 400 MHz, and C = 2 pF. Let the amplifier be fed with a source Vsig having a resistance Rsig = 4 k, and assume a load resistance of 4 k. Find voltage gain AM , and estimate the 3-dB frequency, fH. Compare the results with those obtained with a CE amplifier operating under the same conditions. For simplicity, neglect ro and rx. Solution At an emitter bias current of 1 mA, Q1, and Q2 have

38(a)

To determine fH we use the method of open-circuit time constants. Figure 38(b) shows the circuit with Vsig set to zero and the four capacitances indicated. Capacitance C1 sees a resistance R 1 75

FIGURE 38 Circuits for above Example: (a) The CC-CE circuit prepared for lowfrequency small singal analysis (b) the circuit at high frequencies, with Vsig set to zero to enable determination of the open-ckt time constants and (c) a CE amplifier for comparison. To find the resistance R1 seen by capacitance C 1, we refer to the analysis of the highfrequency response of the emitter follower Section. We may write as follows:

Capacitance C2 sees a resistance R2,

76

Capacitance C2 sees a resistance R2 To determine R 2 we refer to the analysis of the frequency response of the CE amplifier Section to obtain

We now can determine H from

We observe that C 1 and C 2 play a very minor role in determining the high-frequency response. As expected, C2, through the Miller effect plays the most significant role. Also, C1 which interacts directly with (Rsig II Rin), also plays an important role. The 3-dB frequency fH can be found as follows:

For comparison, we evaluate AM and fH of a CE amplifier operating under the same conditions. Refer to Fig. 38(c). The voltage gain AM is given by

77

Thus, including the buffering transistor Q1 increases the gain, |AM|, from 61.5 V/V to 155 V/V a factor of 2.5and increases the bandwidth from 303 kHz to 4.2 MHza factor of 13.9! The gain-bandwidth product is increased from 18.63 MHz to 651 MHza factor of 35! The Darlington Configuration Figure 39(a) shows a popular BJT circuit known as the Darlington configuration. It can be thought of as a variation of the CC-CE circuit with the collector of Q1 connected to that of Q2. Alternatively, the Darlington pair can be thought of as a composite transistor with = 12 . It can therefore be used to implement a high-performance voltage follower, as illustrated in Fig. 39(b). Note that in this application the circuit can be considered as the cascade connection of two common-collector transistors (i.e., a CC-CC configuration).

78

FIGURE 39 (a) The Darlington configuration; (b) voltage follower using the Darlington configuration; and (c) the Darlington follower with a bias current I applied to Q1 to ensure that its remains high.

Since the transistor depends on the dc bias current, it is possible that Q1 will be operating at a very low , rendering the -multiplication effect of the Darlington pair rather ineffective. A simple solution to this problem is to provide a bias current for Q1 as shown in Fig. (39c). The CC-CB and CD-CG Configurations Cascading an emitter follower with a common-base amplifier, as shown in Fig. 40(a) results in a circuit with a low-frequency gain approximately equal to that of the CB but with the problem of the low input resistance of the CB solved by the buffering action of the CC stage. Since neither the CC nor the CB amplifier suffers from the Miller effect, the CC-CB

FIGURE 40 (a) A CC-CB amplifier (b) Another version of the CC-CB circuit with Q2 implemented using a pnp transistor. (c) The MOSFET version of the circuit in (a). configuration has excellent high-frequency performance. Note that the biasing current sources shown in Fig. 40(a) ensure that each of Q1 and Q2 is operating at a bias current I. We are not showing, however, how the dc voltage at the base of Q1 is set or the circuit that determines the dc voltage at the collector of Q2. Both issues are usually looked after in the larger circuit of which the CC-CB amplifier is part. An interesting version of the CC-CB configuration is shown in Fig. 40(b). Here the CB stage is implemented with a pnp transistor. Although only one current source is now 79

needed, observe that we also need to establish an appropriate voltage at the base of Q2. This circuit is part of the internal circuit of the popular 741 op amp. The MOSFET version of the circuit in Fig. 40(a) is the CD-CG amplifier shown in Fig. 40(c). We now briefly analyze the circuit in Fig. 40(a) to determine its gain AM and its highfrequency response. The analysis applies directly to the circuit in Fig. 40(b) and, with appropriate change of component and parameter names, to the MOSFET version in Fig. 40(c). For simplicity we shall neglect rx and ro of both transistors. The input resistance Rin is given by Rin = (1+ 1 )(re1 + re2) which for re1 = re2 = re and 1 = 2 = 3 becomes Rin = 2r
. (159) . (158)

If a load resistance RL is connected at the output, the voltage gain Va/Vi will be
. (160)

Now, if the amplifier is fed with a voltage signal Vsig from a source with a resistance Rsig , the overall voltage gain will be
. (161)

The high-frequency analysis is illustrated in Fig. 41(a). Here we have drawn the hybrid equivalent circuit for each of Q1 and Q2. Recalling that the two transistors are operating at equal bias currents, their corresponding model components will be equal (i.e. r1 = r 2, c1 = c2 etc). With this in mind the reader should be able to see that V 1 = -V 2 and the horizontal line through the node labeled E in Fig. 41(a) can be deleted. Thus the circuit reduces to that in Fig. 41(b). This is a very attractive outcome because the circuit shows clearly the two poles that determine the high-frequency response: The pole at the input, with a frequency fp1 is
. (162)

80

and the pole at the output, with a frequency fP2, is

. (163)

This result is also intuitively obvious: The input impedance at B1 of the circuit in Fig. 41 consists of the series connection of r1 and r 2 in parallel with the series connection of C 1 and C 2. Then there is C in parallel. At the output, we simply have RL in parallel with
C

FIGURE 41 (a) Equivalent circuit for the amplifier in Fig. 40(a). (b) Simplified equivalent circuit Whether one of the two poles is dominant will depend on the relative values of Rsig and RL. If the two poles are close to each other, then the 3-dB frequency fH can be 81
. (164)

determined either by exact analysisthat is, finding the frequency at which the gain is down by 3 dB or by using the approximate formula derived in unit2(last section),

CURRENT-MIRROR CIRCUITS WITH IMPROVED PERFORMANCE Current sources play an important role in the design of IC amplifiers: The constantcurrent source is used both in biasing and as active load. Simple forms of both MOS and bipolar current sources and, more generally, current mirrors are already studied. However, two performance parameters need to be addressed: the accuracy of the current transfer ratio of the mirror and the output resistance of the current source. We may recall that the accuracy of the current transfer ratio suffers particularly from the finite of the BJT. The output resistance, which in the simple circuits is limited to r0 of the MOSFET and the BJT, also reduces accuracy and, much more seriously, severely limits the gain available from cascode amplifiers. In this section we study MOS and bipolar current mirrors with more accurate current transfer ratios and higher output resistances. Cascode MOS Mirrors Figure 42 shows the basic cascode current mirror. Observe that in addition to the diodeconnected transistor Q1, which forms the basic mirror Q1-Q2, another diode-connected transistor, Q4, is used to provide a suitable bias voltage for the gate of the cascode transistor Q3 To determine the output resistance of the cascode mirror at the drain of Q3, we set IREF to zero. Also, since Q1 and Q4 have a relatively small incremental resistance, each of approximately 1/gm, the incremental voltages across them will be small, and we can assume that the gates of Q3 and Q2 are both grounded. Thus the output resistance Ro will be that of the CG transistor Q3, which has a resistance rol in its source. Equation (86) can be adapted to obtain Ro=ro3 + [1+ (gm3 + gmb3 ) ro3]ro2
=

gm3 ro3 ro2

. (165)

Thus, as expected, cascoding raises the output resistance of the current source by the factor gm3ro3 which is the intrinsic gain of the cascode transistor. 82

FIGURE 42 A cascode MOS current mirror. A drawback of the cascode current mirror is that it consumes a relatively large portion of the steadily shrinking supply voltage VDD. While the simple MOS mirror operates properly with a voltage as low as Vov across its output transistor, the cascode circuit of Fig. 42 requires a minimum voltage of Vt+ 2Vov. This is because the gate of Q3 is at 2VGS = 2 Vt + 2Vov. Thus the minimum voltage required across the output of the cascode mirror is 1 V or so. This obviously limits the signal swing at the output of the mirror (i.e.. at the output of the amplifier that utilizes this current source as a load). A Bipolar Mirror with Base-Current Compensation Figure 43 shows a bipolar current mirror with a current transfer ratio that is much less dependent on than that of the simple current mirror. The reduced dependence on is obtained by including transistor Q3, the emitter of which supplies the base currents of Q1 and Q2. The sum of the base currents is then divided by (3 + 1), resulting in a much smaller error current that has to be supplied by IREF. Detailed analysis is shown on the circuit diagram; it is based on the assumption mat Q1 and Q2 are matched and thus have equal collector currents, Ic. A node equation at the node labeled x gives
. (166)

83

Since Io = I c

FIGURE 43 A current mirror with base-current compensation. the current transfer ratio of the mirror will be

. (167)

which means that the error due to finite has been reduced from 2/ in the simple mirror to 2/2, a tremendous improvement. Unfortunately, however, the output resistance remains approximately equal to that of the simple mirror, namely r0 . If a reference current IREF is not available, we simply connect node x to the power supply Vcc through a resistance R. The result is a reference current given by
. (168)

The Wilson Current Mirror , 84 (1 + 2/W

A simple but clever modification of the basic bipolar mirror results in both reducing the dependence and increasing the output resistance. The circuit, known as the Wilson mirror after its inventor, George Wilson, an IC design engineer working for Tektronix, is shown in Fig. 44(a). The analysis to determine the effect of finite on the current transfer

FIGURE 44 The Wilson bipolar current mirror: (a) circuit showing analysis to determine the current transfer ratio: and (b) determining the output resistance. Note that the current ix that enters Q3 must equal the sum of the currents that leave it, 2i. ratio is shown in Fig. 44(a), from which we can write

. (169)

85

This analysis assumes that Q1, and Q2 conduct equal collector currents. However, there is a slight problem with this assumption: The collector-to-emitter voltages of Q 1 and Q2 are not equal, which introduces a current offset or a systematic error. The problem can be solved by adding a diode-connected transistor in series with the collector of Q2, as is shown for the MOS version. Analysis to determine the output resistance of the Wilson mirror is illustrated in Fig. 44(b), from which we see that
. (170)

Ro = ro/2 Finally, we note that the Wilson mirror is preferred over the cascode circuit because the latter has the same dependence on as the simple mirror. However, like the cascode mirror, the Wilson mirror requires an additional VBE drop for its operation; that is, for proper operation we must allow for 1 V or so across the Wilson-mirror output. EXERCISE For = 100 and r0 100 k, contrast the Wilson mirror and the simple mirror by evaluating the transfer-ratio error due to finite and the output resistance. Ans. Transfer-ratio error: 0.02% for Wilson as opposed to 2% for the simple circuit; R0 = 5 M for Wilson compared to 100 k for the simple circuit. The Wilson MOS Mirror Figure 45(a) shows the MOS version of the Wilson mirror. Obviously there is no error to reduce here, and the advantage of the MOS Wilson lies in its enhanced output resistance, The analysis shown in Fig. 45(b) provides Ro ro3 (gm3ro2 + 2) . (171) gm3ro3ro2 where we have neglected, for simplicity, the body effect in Q3. The output resistance is approximately the same as that achieved in the cascode circuit. Finally, to balance the two branches of the mirror and thus avoid the systematic current error

86

FIGURE 45 The Wilson MOS mirror (a) circuit (b) analysis to determine output resistance (c) modified circuit. resulting from the difference in VDS between Q1 and Q2, the circuit can be modified as shown in Fig. 45(c). The Widlar Current Source Our final current-source circuit, known as the Widlar current source, is shown in Fig. 46. It differs from the basic current mirror circuit in an important way: A resistor RE is included at the emitter lead of Q2. Neglecting base currents we can write
. (172)

87

FIGURE 46 The Widlar current source. And

. (173)

where we have assumed that Q1 and Q2 are matched devices. Combining Eqs. (172) and (173) lead to
. (174)

88

But from the circuit we see that

. (175)

Thus
. (176)

The design and advantages of the Widlar current source are illustrated below: EXAMPLE Figure 47 shows two circuits for generating a constant current Io = 10A which operate from 10-V supply. Determine the values of the required resistors assuming that VBE is 0.7 V at a current of l mA and neglecting the effect of finite . Solution For the basic current-source circuit in Fig. 47(a) we choose a value for R1, to result in IREF = 10A. At this current, the voltage drop across Q1 will be

89

FIGURE 47 Circuits for Example above Thus

For the Widlar circuit in Fig. 47(b) we must first decide on a suitable value for IREF. If we select IREF = 1 mA, then VBE1 = 0.7 V and R2 is given by

The value of R3 can be determined using Eq. (176) as follows:

From the above example we observe that using the Widlar circuit allows the generation of a small constant current using relatively small resistors. This is an important advantage which leads to considerable savings in chip area. In fact the circuit of Fig. 47(a), requiring a 942-k resistance, is totally impractical for implementation in IC form. 90

Another important characteristic of the Widlar current source is that its output resistance, is high. The increase in the output resistance, above that achieved in the basic current source, is due to the emitter degeneration resistance RE. To determine the output resistance of Q2, we assume that since the base of Q2 is connected to ground via the small resistance re of Q1, the incremental voltage at the base will be small. Thus we can use the formula derived in the CB amplifier for output resistance and adapt it for our purposes a as follows: R0=[1+gm(RE//r))r0
(177)

Thus the output resistance is increased above r0 by a factor that is very significant.

91