C Design

Dr. John Tanner, Anant Adke, David H .Lipin Tanner Research, Inc. 444 North AltadenaDrive Pasadena, CA 91107 integrated circuits. For one thing, it is very easy LO copy a design implemented. using off-the-shelf parts. As board densities go up, there is always a push towards reducing parts count. Putting the design into a single IC greatly reduces the parts count compared to a off-the-shelf implementation. Also, it is seldom possible to find an offthe-shelf part that exactly implements the required function. There are other advantages also. lower parts and inventory costs, lower manufacturing costs, lower power consumption and increased reliability being some of them. The downside of going to ASICs is that the design turnaround time increases significantly. The NRE costs associated with the design increase significantly (00. ASICs become cost-effective at volume production of at least 10,OOO. For full-custom designs, the volumes have to be as high as 100,000 units. There are several reasons for the high NRE costs. The tools required to support ASIC design are the first major cost item. Although workslation prices continue to drop, the software and hardware investment can easily run up LO hundreds of thousands of dollars. A significant effort has LO be expended to ensure design integrity prior to production, since recycling costs can kill a project. This requires a lot of simulation expenses. The other major cost of ASIC production is the mask charges. With todays complicated processes, it is common to have ten to twelve mask steps. With the per mask costs being $5000 and up, the mask charges alone can add up to tens of thousands of dollars. Does all this mean that ASIC design is restricted to big companies which can afford an investment of millions of dollars? Fortunately, it is not so. With the emergence of powerful new software running on inexpensive yet powerful personal computers, ASlC designers can implement their innovative designs inexpensively. The fabrication costs are reduced too, thanks to the many new technologies that allow quick and inexpensive prototyping and volume production.
ble D&rn

Abstract
To be competitive,companies must desi@ more application specific integrated circuits (ASICs) into their products. The number of ASICs designed increases each year, while the number of parts for each design decreases. The only way this trend can continue is if the cost of design hardware, software, and prototypes drops. This tutorial addresses recent advances in each of these three areas that allow affordable ASIC design for the first time. Commercial CAD tools are now available that support hands-on electronic design on inexpensive FCs as well as more expensive Macintoshes and Unix workstations. Designers can create vendor independent logic diagrams, simulate them, and implement them via automatic translation to a variety of technologies including field programmable gate arrays (FPGAs),commercial gate arrays and standard cells, and custom masks suitable for inexpensive MOSIS prototypes. Mask preparation tools include completely automatic mask generation for logic design, as well as fully customized design for VLSI applications. New cross-section viewing facilities aid in the understanding of IC fabrication processes and in the design of special structures. FPGAs and MOSIS prototypes are inexpensive and bring the fun back into designing with new IC technology. T h i s tutorial will discuss the following topics: Economics of ASIC use and fabrication Affordable design platforms Affordable design tools Traditional gate array and standard cell technologies Field programmable gate arrays (Actel. Xilinx) Affordable prototypes through multi-project wafers Affordable volume production

PI .&form.A

With the drop in price of personal computers and workstations and the emergence of new powerful yet lowcost CAD software, it is now possible LO provide hands-on design capability at lower costs than ever befoxe. Affordable low-volume prototyping of FPGAs and MOSIS custom chips allows designers to carry their designs through implementation and testing before volume production.

. .

There are many reasons for =design using off-the-shelf TTL parts to aplflication specific

The major capital costs associated with undertaking ASIC design in house are the costs of new computers and CAD software. Although Unix workstations have recently dropped in price dramatically, acquiring all the pieces necessary to implement ASIC design representsa significant investment t o the tune of hundreds of thousands of dollars. It is also m e that with the introduction of more powerful 32-bit microprocessors. the ubiquitous personal computers are approaching the native power of workstations. It has beem widely reported that more engineering groups have bought design tools that run on IBM PC compatible computers than tools based on any other platform. On the software side, the introduction of powerful new tools that

Table 1 Costsper CAE seat.

software
Many clone companies 386 computer, 20 MHZ 1 h4Byte RAM 2 floppy disks 60 MByte hard disk VGA graphics card and monitor

$2200

Mouse DOS software

OrcAD SchematicEditor TannerResearch Logic Simulation Actel Mapping library MOSIS Mapping library Layout Editor MOSIS Layout Library intusoft IS-SPICE

495 1295 249 249 995 295

295
$6.073

Total allow designers to implement low cost ASICs has completed the full spectrum of ASIC design. Indeed, personal computers provide the real bargains, not only in lowest purchase price but with low hardware and software maintenance costs and widest availability of affordable commercialsoftware. An ASIC designer can be outfitted with d IBM compatible 386-based PC for less than $4400 p a seat. Table 1 idenlifes the software and hardware r e q d for typical ASlC design . Software costs will vary with the emphasis of the

course.
System support costs of Pcs are minimal. Unlike Unix workstations that require a major time commitment from a Unix expert, DOS machines are simple enough that they can be run with almost no software maintenance support. Hardware maintenance of PC-class machines is also generally low. When the rare hardware failure does occur, it is easy for a novice to open the machines and swap cards and components with similar working machines to isolate problems. Budgets should include 10%to 15% of purchase costs per year to cover hardware maintenance and repair. After the first year budgets may allow for system enhancements such as RAM upgrades, local area networks, modems, and data backup systems.
Took The major integrated circuit design tasks are schematic capture, gate-level simulation. fault grading, cell mask layout, analog simulation, design rule checking, and chip layout. We will show that each of these steps can be implemented on a personal computer with affordable yet powerful software. Figure 1 is a block diagram of the tools and thek interrelationships.
n a d netlist generatio n Schematic w A typical design begins with the creation of a schematic using elements from a vendor independent logic library. Library elements range from low level gates, flip-flops, latches, and multiplexers up to multiple-bit counters and adders. The schematic editor creates a netlist that specifies

the library elements used in a design and their interconnection. The netlist translator, in conjunction with a vendor mapping library, substitutes a vendor-specific implementation for each generic element in the netlist and produces a new netlist in a particular vendors netlist format. o change technologies This capability allows the designer t by simply rerunning the netlist translator using a different mapping library. No changes to the schematic are necessary. The netlist wanslator allows for unit delay or full timing simulations. Before choosing an implementation technology, a designer may simulate with a constant delay for each logic element in order to debug the basic logic functionality. After choosing a vendor technology, the netlist translator is executed again. The translator accesses timing information in the selected vendor mapping library. Each of the vendors cells has been precharacterized for timing delays in the form of a constant plus a capacitiveload dependent term. The capacitances of each cells inputs are also contained in the mapping libraries. The netlist translator analyzes the circuit, adds up the iohl capacitance for each node, substitutes the appropriate capacitances into each delay formula, computes L h e delays, and passes them to the simulator. Wiring capacitances can be included in the calculation, either as a fanout dependent empirical prelayout estimate, or from a capacitance back annotation file provided from the place-and-routesoftware. Gate-level simulation The majority of the design time is spent iterating between the simulation and the schematic. Fortunately, the gatelevel simulator has beem heavily optimized for speed. The gate-level simulator allows for binary signals 0 and 1, unknown X, and high-impedance Zsignals and produces text output or waveforms. It includes a static timing analysis command that allows the designer to determine maximum or minimum delays between nodes. The simulator also includes a powerful fault simulator. Fault testing on the production line culls out chips that have fabrication defects and marks them for discard. This testing is very different from the functional testing that a designer must do to verify that his design is correct.

One of: Actel xilinx Vendor Harris Mapping National Library NcR OKI TI SCMOS CMOS3
L

SchemLibTM Vendor Independent Library

Schematic Capture

GateSimTM Gate-level

Intwace
Mask Level

Standard C e l p Place and Route

Lay0u Library

One of: SCMOSLibTM CMOS3LibTM AnaCMOSLibm other libraries

\

L-EditTM

Layout Editor
with DRC

e
FMask ormat

ES2 HP MCE MOSIS

Orbit
VLSI

us2

UTMC

Extractor 1

IS-Spice

or PSPICE Analog Simulation

Figure 1 : Block diagram of PC-based ASIC design CAD tools.

Functional testing may involve large numbers of test patterns to exercise the chips in many Vferent situations that the chip is expected to deal with. q h e goal of fault testing is to minimize the number of tedpattems and thus minimize the time each chip spends on an expensive tester yet still catch all fabrication faults by propagating their effects to the outputs. The fault simulator takes in a netlist and a production test pattern and returns the percentage of possible fabrication defects (modeled as stuck-at faults) that the test pattern would uncover. In today's climate of quality competition, test coverage of 98% or more is considered highly desirable. When the designer is satisfied with the simulated behavior of the circuit, the netlist is forwarded for implementation. In the case of FPGAs, the netlist is processed by the vendor's software to internally configure a specific FPGA part. For a volume production part, the netlist is passed to the semiconductor vendor where their place-and-route software will create the production mask data for the gate array or standard cell chip. For MOSIS prototypes. the netlist is passed to the layout software on the designer's own machine to create the MOSIS-compatible standard cell layout. In each of these cases, the timing information corresponding to the detailed placement and routing can be passed back to the designer for post-layout simulation. Before committing to final implementation costs, the designer can verify that the post-layout timing is within specifications.

provides a very affordable implementation of Spice. PSpice is another very popular commercial analog simulator. Several other commercial versions of Spice are available. The extractor can also produce a switch-level netlist file in NTK format. NTK files can be simulated at the switch-level using programs such as COSMOS from CMU. The NTK files can also be used for a layout vs. schematic (LVS) comparison to insure that the mask implements the designem intent as defined by the schematic. -tion Views

Standard cell designs only scratch the surface of the design possibilities available with silicon. High-performance digital designs can benefit from custom RAM, ROM, PLA, and ALU blocks. Analog design almost always requires hand crafted structures. Traditional analog circuits include amplifiers, comparators, analog-to-digital conveners. digitalto-analog converters. and switched capacitor filters. Possible novel structures include imagers (both MOS and CCD), combination bipolar-MOS transistors, Hall-effect sensors, temperature sensors, neural networks, and floating gate structures. An integrated circuit is inherently a three-dimensional device. Experienced designers can quickly mentally translate the flat screen representation into its corresponding three dimensional structure. In discussions between engineers, hand drawn cross section views are often used to . . communicate the relevant content of a design that may not ut 1 .ibranes be readily apparent from the usual flat top view. MOSIS-compatible layout libraries are available for digital Quick access to cross section views provides an effective and analog standard cells. These libraries contain fixed way of aiding understanding of integrated structures. We height cells suitable for automatic composition by the placehave implemented an automatic cross section view generator and-route software. The libraries also contain sets of pads within L-Edit, the Tanner Tools layout editor. L-Edit for the MOSIS technologies ranging from 3pm to 1 . 2 ~ . allows the designer to interactively create and edit geometric The analog library contains cells described in Analog VLSI mask data on a computer screen by using a mouse. With and Neural Systems by Carver Mead. Large scale analog the new cross section feature. the designer draws a sectioning circuits are generally not suitable for automatic layout line on the layout with a mouse. L-Edit immediately opens creation, so the analog library also contains several large a new window adjacent to the layout and constructs in the full-custom analog circuits that can serve as examples and window a cross section view corresponding to the sectioning can be scavenged for useful cell layouts. line in the layout area. This viewing facility allows the designer to check his layout against his mental model of it. Cross section views of integrated circuits aid novice and lavout. verification. and analQe simulation

T-15.4

implant, and CCD implant. Clever engineers can create multi-gate uansistors, JETS. isolated bipolar transistors, CCD transfer srructures. and a variety of floating gate structures. Cross section views are important even to the veteran chip designer when creating and communicating these more complex structures. Cross section views are often useful for understanding the reasons for geometrical design rules. For example, most CMOS processes have a minimum distance between via and the edge of polysilicon. Vias may be entirely surrounded by poly or completely away from poly, but may not be near an edge. Although this rule may Seem arbitrary to first-time designers, a cross section view shows clearly the uneven metal terrain over poly edges. It becomes easy to visualize the fabrication problem that would arise from trying to place a via over the uneven metal. Advanced designers benefit from understanding the motivation for d a g n rules by being able t o selectively violate design rules ufi8er conditions that wont cause fabrication problems. Our implementation of cross section views is intended to aid the circuit designer in conceptually Understanding t h e ! . vertical structure of integrated circuits. For this purpose, the renderings do not have to be a completely accurate representation of the physical structure of integrated circuits. Actual chips have a variety of properties, such as smooth height transitions. that are not modeled here. The simple cross section feature described is nor intended to be accurate enough to aid the process engineer but simply to show clearly the vertical relationship of the various fabrication layers as a function of the masks specified in the layout. The cross section views are built up from the layout by simulating a set of fabrication steps and building the diagram from the substrate up, one layer at a time. Our simplified process steps amount to the recipe used to create the integrated circuit view and correspond only roughly to the process steps used by the fabricator to create the chip. The process specification is maintained on-line within LEdit and may be edited interactively by the user. Figure 2 shows a screen captured from the PC version of the layout editor. In operation, the designer interactively draws and edits the mask geometry using a mouse. In this case, the upper half of the screen displays a finished inverter circuit. The designer then invokes the cross section command by pulling down the special menu. Next the designer chooses the cross section to be displayed by drawing a sectioning line across the layout. This line can be seen below with arrowheads at each end pointing toward the cross section view. L-Edit then opens a special cross section window and constructs the corresponding side view of the integrated circuit. L-Edit cross section views can also be constructed one step at a time, under control of the user. For illustrating the fabrication steps, the display can be temporarily halted after each step in the process specification table. This single-step display mode is useful for learning the steps involved in fabrication. It is also possible to use a much more detailed process specification table. Single stepping through a fabrication cross section that includes all the photoresist and other intermediate processing steps would better

communicate the full complexity of todays fabrication processes. For circuit designers who only want to view final cross sections, the simpler process specification is sufficient and easier to maintain.
D d P n Methodulogies

There are several technologies available to the ASIC designer to implement his designs.

s
Standard cells are a collection of fixed height cells which S I logic functions. implement commonly used SSI and M Designing with standard cells is very much like designing with off-the-shelf TTZ logic parts. The restriction of fixed pitch exists so that during the automatic placement and layout phase, all the cells can be abutted to each other. This reduces the complexity of the algorithms required for placement and muting. The cells themselves are hand-crafted by layout engineers. Note that during fabrication, the chip i s built from ground up, i.e.. all the mask steps have to be followed. This reduces the cost-effectiveness of standard cells. It is true that their space utilization and speed is higher than gate arrays. Gate arrays reduce the number of processing steps during fabrication. They consist of a prefabricated collection of uncommitted gates, which can be mask programmed using one or more levels of metallization. The gate array vendor is able to stock the gate arrays, and customize them for individual customers using a very few processing steps. as compared to the ten or twelve mask steps required to fabricate a chip ground up. This reduces the cost for the customer. It may not be possible to achieve as high speeds and space utilization as standard cells, though.

The two leading vendors of FPGAs today are Actel and Xilinx. Actel devices are configured by a special hardware device that permanently burns the connections internal to an Actel chip. Once burned, the Actel chip maintains its configuration and no longer requires any special support circuiuy. The configuration of Xilinx chips is stored in volatile flipflops within the chip. Each time a Xilinx chip is powered on, its configuration needs to be loaded into the device again. During prototyping, the configuration data can be downloaded from a PC. For stand alone operation, a Xilinx chip can load its configuration data on power up from a ROM. Xilinx prototypes have the advantage of being reusable but have a slight system complexity of allowing for power-up configuration. Prototyping with Actel parts requires access to a special burner box that costs $5,000 along with the specialized Actel software to operate it. Note that the Actel software requires atleast 80386-based machines. The investment in the Actel hardware and software can be avoided by using an Actel programming service such as the one provided by Tanner Research. The

T-15.5
~ _ _

Xilinx software and cable costs about $4OOO. Both Actel and Xilinx FPGAs employ programmable logic buildmg blocks and interconnect to implement a specific circuit. The vendor independent methodology shields the designer from these awkward and individual internal architectures and allows the designer to concentrate on the design problem using more familiar gates and flip-flops. The netlist translator in conjunction with the vendors

software maps each design onto the programmable structure inside the FPGAs. As the size of a design approaches the limits of the capacity of an FPGA, the vendors software may be unable to create a valid configuration. At this point, a designer may make his design smaller, select a larger FPGA .part, or attempt to perform hand optimization. Anecdotal evidence suggests that the Actel software can achieve much higher utilization of an array before giving up,

LEdit F i l e E d i t V i w Cell Arrange Setup Spmcial

P-

Figure 2: L-Edit screen display showing automatically generated cross section view.

Table 2: Comparison of Actel and Xilinx FPGAs and MOSIS prototypes.

Actel start-up Cost Cost per chip Implementation time Gate capacity Special structures
$5,000 $100 1 hour 2000

Actel using burning service

$0

Xilinx
$4000 $100 1 hour

MOSIS

so
$500 7 weeks 1000

$200 2 days
2000

No

No

2000 No

Yes

* Note that Xilinx has a wide variety of parts with different gale capacities and prices.

Their slated gate capacities arc theoretical Values that generally need to be divided by 2 or 3 to get actual gate capacities.

T-15.6

but Actel provides no access t o the internal elements of their FPGAs for hand optimization. The Xilinx software cannot achieve automatic and complete configuration for nearly as high a utilization as Actel's, but the Xilinx software comes with an editor for hand tweaking the design within the Xilinx architecture. In order to reduce start-up costs for using FFGAs. Tanner Research offers an Actel programming service. Customers can design and simulate their circuits on their own computer. When they are ready for an implementation. they transfer the netlist electronically to our computer, we program the part using our Actel software and hardware, and ship the resulting part overnight. The price for this service is $200 and $250 for the 1200 and 2000 gate part respectively, including the cost of the part and shipping costs.
Affordable Production

uses a novel technology wherein an E-beam is used to write all layers onto the wafer. They promise fully tested parts within four weeks.

Summarv
Affordable commercial CAD tools are now available for a range of electronic design classes. These tools support FPGA and MOSIS prototypes. In less than two years, the Tanner Research software has been adopted by more than 90 colleges and universities. The majority of these sites use PCs. A smaller number use Macintoshes. We expect the new Unix version of the tools to gain acceptance at schools that can afford these more expensive machines.

Contacts
Layout, Gate level Simulation, Libraries, Logic Mapping software (818) 795-1696 Tanner Research, Inc. Schematiccapture software (503) 690-988 1 MAD (619) 554-1000 Tango (Accel) (508) 480-088 1 Viewlogic Analog simulation software (213) 833-0710 intusoft (7 14) 770-3022 MicroSim FPGA hardware (408) 739-1010 Actel (408) 559-7778 Xilinx Custom IC prototypes (213) 822-1511 MOSIS Custom IC volume production (408) 744-1800 Orbit

ve P r o t o w

MOSIS is a prototyping service. It offers small quantities of full-custom and semi-custom chips for as little as $500
using industry standard volume production processes. Designs are combined on a single wafer run. Therefore, instead of paying for an entire wafer lot costing between $50.000 and $80,000, MOSIS users only pay for the percentage of silicon that they use, which can be as low as $500. For digital design, approximately lo00 gates will fit into a MOSIS TinyChip" using the Tanner Tools and libraries. The benefits gained by working with a volume production process may not be worth the additional cost and seven week fabrication delay for projects that are smctly digital and can fit into an FFGA. For analog designs o r special structures, access to a full-custom process is necessary. For prototype quantities MOSIS provides a tremendous cost advantage over a custom fabrication run purchased directly from a semiconductor vendor. Table 2 compares Actel and Xilinx FPGAs with MOSIS prototypes.

us2

(800) 969-7448

-V le
For production volumes, neither MOSIS gar& nor FPGAs provide cost effective solutions. As volfies increase, the piece price becomes more important jhan NRE costs. Engineers must be aware of ASIC prices in order to make an informed decision on the cost effectiveness of including an ASIC in a system design. Almost always, the price for volume purchase of ASICs is a negotiated settlement between the customer and the ASIC vendor. Orbit Semiconductor, Inc., working with Tanner Research, has provided budgetary ASIC costs for the purpose of engineering decisions prior to a negotiated semiconductor purchase. Orbit is a MOSIS vendor, so you have the option of obtaining inexpensive prototypes from their fabrication line. Another vendor who covers the full spectrum of prototypes, low volume Droduction run or hieh volumes is US2. US2