STATIC SYNCHRONOUS SERIES COMPENSATOR FOR LOW VOLTAGE RIDE THROUGH CAPABILITY OF WIND ENERGY SYSTEMS

Sijoy Raphael and A.M. Massoud sraphael@qu.edu.qa & ahmed.massoud@qu.edu.qa Dept. of Electrical Engineering, College of Engineering, Qatar University, Qatar
ABSTRACT Due to the large increase in number of installed high power renewable energy generating systems such as wind energy power plants, one of the important evolving requirement is riding through the fault at low or zero voltage. In this paper, static synchronous series compensator is employed in power systems with high penetration of renewable energy units to achieve low voltage ride through capability in abnormal operation in addition to power enhancement in normal operation. Matlab/Simulink simulation results are presented to validate the proposed concept of operation through two case studies. Index Terms SSSC, Renewable Energy, Wind Energy, and Ride Through Capability. power to control the transmission line voltage at a reference value (in condition that the rating of the shunt converter is not exceeded). The series converter operation modes as determined in the literature [1-25] are: voltage injection according to a predetermined reference value. phase shifter between the sending end and receiving end impedance proportional with the line current (avoiding negative impedances). power flow control (controlling active and reactive power) In this paper, and instead of using the unified power flow controller, static synchronous series compensator is employed in power systems with high penetration of renewable energy units to achieve low voltage ride through capability. Matlab/Simulink simulation results are presented to validate the proposed concept of operation. 2. APPLICATIONS OF SSSC 1. INTRODUCTION Due to the ongoing development of semiconductor devices, power electronics devices for power system applications has been increased. Unified power flow controller (UPFC) is one of the flexible AC transmission system (FACTS) devices [1-4]. Unified power flow controller (UPFC) controller is a back-to-back combination of a shunt converter (STATCOM) and a series converter (SSSC), which are coupled by a common DC-link, to allow bi-directional flow of active power between the series terminals and the shunt terminals of the converters, and are controlled to provide concurrent active and reactive series line compensation without an external electric energy source. The voltage rating of the series converter (SSSC) [3,4] is a fraction of the p.u. rated voltage reliant on the required injected series voltage. In normal operation [5-7], the series converter injects a voltage which has a two orthogonal components when transformed to synchronously rotating reference frame (the direct axis is aligned with phase a of the receiving end). The d-axis component contributes in magnitude variation and quadrature component which contributes in phase angle. The shunt converter functionality can be reactive source compensation (providing inductive or capacitive VAR) or voltage regulation providing reactive The SSSC is a solid state voltage source inverter (VSI) connected in series with a transmission line through a coupling transformer which can inject an almost sinusoidal voltage of variable magnitude which is almost in quadrature with the line current [8-12]. When the injected voltage is leading the line current, it emulates an inductive reactance in series with the line causing the power flow to decrease. On the other hand, when the injected voltage is lagging the line current, it emulates a capacitive reactance in series with the line causing the power flow to increase [5]. In contrast to a series capacitor, the SSSC can negotiate both active and reactive power by controlling the angular position of the injected voltage w.r.t line current, provided the SSSC is coupled with an energy source/sink. Because of this excellent ability SSSC can be used to keep the XL/R ratio of the transmission line high, by simultaneously compensating both the reactive and resistive components [6]. The SSSC is capable of effectively damping the power oscillation by concurrently injecting an alternating positive and negative real impedance in line with the machine swings [6].

Fig. 1. Control strategy of SSSC

3. CONTROL OF SSSC The proposed control of SSSC is as shown in Fig. 1. During normal operation, the SSSC would be in Power Flow Control mode [7] as shown in the figure. The reference real power is compared with the actual power transferred, and the error is passed through a PI controller. Since the SSSC controls only the active power, the reactive power reference is set to zero. The pahse locked loop (PLL) is derived from the phase currents and using the abc-dq transformation and vice versa, the VSI is controlled in the synchronous reference frame to achieve the set active power transfer. When a three phase to ground fault occurs in the parallel transmission line, the SSSC changes to Voltage Control mode [7] as shown in Fig.1. The control strategy changes from closed loop to open loop and the PLL is derived from the line voltages as the exponentially-decaying nature of the fault current affects the PLL based on the line currents. The reactive and real power injection at the PCC would make the voltage corrected to nominal value with appropriate change in power angle such that the real power transfer is maintained. If the injection of reactive power required to maintain the set active power transfer would make the voltage at PCC swells above the nominal, the reactive power would be controlled in such way to maintain the nominal voltage which could make the real power transfer to a lower value [7]. 4. LVRT USING SSSC In power systems terminology, the low voltage ride through (LVRT) can be described as the ability of an electric device to perform its intended operation during or immediately after a voltage dip, caused by a fault or a load change in the system. The voltage may be reduced in one, two or all the three phases of the power system. Depending on the application, the device:

disconnects temporarily from the grid, but reconnects and continues operation after the dip stays operational by not disconnecting from the grid The new regulations necessitate staying operational specially with the high penetration of renewable energy sources (which may affect power system stability). Even though LVRT is a commonly used acronym with wind turbines, the usage is not limited to this device only, but also applicable to any device which is operational in a power system. For generating units, the required LVRT behavior is defined in corresponding grid codes as shown in Fig. 2. The SSSC has excellent LVRT capability by means of the state-of-the-art design and construction, control systems, and energy storage facility by means of the DC capacitor. The sending end should be able to transfer the scheduled power to the receiving end through the transmission line, even when the voltage at PCC dips to low levels and there is an outage in other parallel lines. This is possible if the un-faulted line is connected through a SSSC. Two case studies are carried out to verify the LVRT performance of the SSSC. The ability of a SSSC to transfer the intended real power through the line, during a fault in the parallel line, is studied and presented in the following sections.

Fig. 2. A typical LVRT curve

The block diagram of the case study is given in Fig. 3. The generator and grid are represented behind respective Thevenin reactances. To match the realistic situations, the system is rated at 220 kV level. The sending and receiving ends are modeled as a three-phase ac sources. 5. LVRT CASE STUDY The system parameters for both the case studies are given in Table 1. 5.1 Case Study I Case study I investigates the LVRT capability of the SSSC when the receiving end voltage drops to almost 0.8 pu due to a fault in the parallel line, represented by the series connection of TL2 and TL3. Fig. 5 (a-d) shows the relevant figures for the system for a three phase to ground in parallel line which causes a a 0.2 pu drop in receiving end when SSSC is not in operation. Fig. 5.a represents sending end voltage waveform while Fig. 5.b represents the current through faulted transmission line. Fig. 5.c shows the current through unfaulted line while Fig. 5.d shows the active power transferred through unfaulted line. Fig. 6 (a-d) shows the relevant figures for the system for the same fault condition when SSSC is in operation. Fig. 6.a represents the voltage waveform measured after the SSSC while Fig. 6.b represents the voltage injected by the SSSC. Fig. 6.c shows the current through unfaulted line while Fig. 6.d shows the active power transferred through unfaulted line. The comparison of Fig. 5.c with Fig 6.c shows the increase in the current by the action of SSSC to transfer the scheduled power of 500 MW while the line was able to transfer only 350 MW without SSSC. The comparison

of Fig. 5.d with Fig 6.d shows that the scheduled power of 500 MW is almost maintained during normal operation and fault conditions when SSSC is installed. The SSSC was not able to keep the scheduled power transfer of 500 MW during fault conditions because the voltage would then go above the accepted limits. 5.2 Case Study II Case study II investigates the LVRT capability of the SSSC when the receiving end voltage drops to almost 0.5 pu due to a fault in the parallel line. Fig. 7 (a-d) shows the relevant figures for the system for a three phase to ground fault in parallel line which causes a a 0.5 pu drop in receiving end when SSSC is not in operation. Fig. 7.a represents sending end voltage waveform while Fig. 7.b represents the current through faulted transmission line. Fig. 7.c shows the current through unfaulted line while Fig. 7.d shows the active power transferred through unfaulted line. Fig. 8 (a-d) shows the relevant figures for the system for the same fault condition when SSSC is in operation. Fig. 8.a represents the voltage waveform measured after the SSSC while Fig. 8.b represents the voltage injected by the SSSC. Fig. 8.c shows the current through unfaulted line while Fig. 8.d shows the active power transferred through unfaulted line. The comparison of Fig. 7.c with Fig 8.c shows the increase in the current by the action of SSSC to transfer the scheduled power of 500 MW. The comparison of Fig. 7.d with Fig 8.d shows that the scheduled power of 500 MW is almost maintained during normal operation and fault conditions when SSSC is installed. The SSSC was not able to keep the scheduled power transfer of 500 MW during fault conditions because the voltage would then go above the accepted limits.

Fig. 3. Block diagram for case study

Table 1: System parameters for the case studies Sending and receiving ends: Rated voltage: 220 kV Reactance, Xth: 3.14 Transmission lines (100 km): Resistance: 1.2 /km Reactance, XL: 34.23 /km

Sending End Voltage (L-L)

300

Voltage after SSSC (L-L)

300

200

200

100

100

Voltage (kV)

Voltage (kV)

-100

-100

-200
Point of Fault Inception

-200
Point of Fault Inception

-300 0.4

0.5

0.6

0.7

0.8 Time (s)

0.9

1.1

1.2

-300 0.4

0.5

0.6

0.7

0.8 Time (s)

0.9

1.1

1.2

(a)
Current through Faulted Transmission Line
15

(a)
Voltage Injected by SSSC

100
10

50
Current (kA)
5

Voltage (kV)

-50
Point of Fault Inception

Point of Fault Inception

-5

-100

0.4

0.5

0.6

0.7

0.8 Time (s)

0.9

1.1

1.2

0.4

0.5

0.6

0.7

0.8 Time (s)

0.9

1.1

1.2

(b)
Current through Unfaulted Line
2
1

(b)
Current through Unfaulted Line

1.5 1

0.5

0.5

Current (kA)

Current (kA)

0 -0.5 -1 -1.5

-0.5

-1

Point of Fault Inception

-2 -2.5

Point of Fault Inception

0.4

0.5

0.6

0.7

0.8 Time (s)

0.9

1.1

1.2

0.4

0.5

0.6

0.7

0.8 Time (s)

0.9

1.1

1.2

(c)
Power Transferred through Unfaulted Line
500 450 400 350

(c)
Power Transferred through Unfaulted Line
1100 1000 900 800

Real Power (MW)

Real Power (MW)

300 250 200 150 100 50 0 0.4 0.5 0.6 0.7 0.8 Time (s) 0.9 1 1.1 1.2
Point of Fault Inception

700 600 500 400 300 200 Fault 100 0 0.4

Point of Inception

Reference

0.5

0.6

0.7

0.8 Time (s)

0.9

1.1

1.2

Fig. 5. (a) Sending end voltage waveform, (b) Current through faulted transmission line, (c) Current through unfaulted line without SSSC, and (d) Power transferred through unfaulted line without SSSC

Fig. 6. (a) Voltage waveform measured after SSSC, (b) Voltage injected by SSSC, (c) Current through unfaulted line with SSSC installed, and (d) Power transferred through unfaulted line with SSSC installed

Fig. 5. Figures for the system for a fault in parallel line which causes a a 0.2 pu drop in receiving end when SSSC is not in operation

Fig. 6. Figures for the system for a fault in parallel line which causes a a 0.2 pu drop in receiving end when SSSC is in operation

Sending End Voltage (L-L)

300 300

Voltage after SSSC (L-L)

200

200

100

100

Voltage (kV)

Voltage (kV)
Point of Fault Inception

-100

-100

-200

-200
Point of Fault Inception

-300 0.4

0.5

0.6

0.7

0.8 Time (s)

0.9

1.1

1.2

-300 0.4

0.5

0.6

0.7

0.8 Time (s)

0.9

1.1

1.2

(a)
Current through Faulted Transmission Line
50 40 30

(a)
Voltage Injected by SSSC
150

100

50
Current (kA)
20 10 0 -10

Voltage (kV)

-50 Point of
Fault Inception

-100
-20 -30 0.4
Point of Fault Inception

0.5

0.6

0.7

0.8 Time (s)

0.9

1.1

1.2

-150 0.4

0.5

0.6

0.7

0.8 Time (s)

0.9

1.1

1.2

(b)
Current through Unfaulted Line
2

(b)
Current through Unfaulted Line
3 2

1
Current (kA)
0

Current (kA)
Point of Inception

0 -1 -2

-1

-2 Fault

-3 -4
0.5 0.6 0.7 0.8 Time (s) 0.9 1 1.1 1.2

Point of Fault Inception

-3 0.4

0.4

0.5

0.6

0.7

0.8 Time (s)

0.9

1.1

1.2

(c)
Power Transferred through Unfaulted Line
500 450 400

(c)
Power Transferred through Unfaulted Line
1000 900 800

Real Power (MW)

Real Power (MW)

350 300 250 200 150 100 50 0 0.4 0.5 0.6 0.7 0.8 Time (s) 0.9 1 1.1 1.2
Point of Fault Inception

700 600 500 400 300 200 100 0 0.4 0.5 0.6 0.7
Point of Fault Inception

Reference

0.8 Time (s)

0.9

1.1

1.2

Fig. 7. (a) Sending end voltage waveform, (b) Current through faulted transmission line, (c) Current through unfaulted line without SSSC, and (d) Power transferred through unfaulted line without SSSC

Fig. 8. (a) Voltage waveform measured after SSSC, (b) Voltage injected by SSSC, (c) Current through unfaulted line with SSSC installed, and (d) Power transferred through unfaulted line with SSSC installed

Fig. 7. Figures for the system for a fault in parallel line which causes a a 0.5 pu drop in receiving end when SSSC is not in operation

Fig. 8. Figures for the system for a fault in parallel line which causes a a 0.5 pu drop in receiving end when SSSC is in operation

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