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DM7490A Decade and Binary Counter

August 1986 Revised September 1998

DM7490A Decade and Binary Counter


General Description
The DM7490A monolithic counter contains four masterslave flip-flops and additional gating to provide a divide-bytwo counter and a three-stage binary counter for which the count cycle length is divide-by-five. The counter has a gated zero reset and also has gated setto-nine inputs for use in BCD nines complement applications. To use the maximum count length (decade or four-bit binary), the B input is connected to the QA output. The input count pulses are applied to input A and the outputs are as described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the counters by connecting the QD output to the A input and applying the input count to the B input which gives a divide-by-ten square wave at output QA.

Features
s Typical power dissipation 90A 145 mW s Count frequency 42 MHz

Ordering Code:
Order Number DM7490AN Package Number N14A Package Description 14-Lead Plastic Dual-In-Line Package, JECEC MS-001, 0.300 Wide

Connection Diagram
Dual-In-Line Package

1998 Fairchild Semiconductor Corporation

DS006533.prf

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DM7490A

Function Tables
Count QD 0 1 2 3 4 5 6 7 8 9 L L L L L L L L H H

(Note 1)

BCD Count Sequence (Note 2) Outputs QC L L L L H H H H L L QB L L H H L L H H L L QA L H L H L H L H L H

Logic Diagram

BCD Bi-Quinary (5-2) (Note 3) Count QA 0 1 2 3 4 5 6 7 8 9 L L L L L H H H H H Outputs QD L L L L H L L L L H QC L L H H L L L H H L QB L H L H L L H L H L The J and K inputs shown without connection are for reference only and are functionally at a high level.

Reset/Count Function Table Reset Inputs R0(1) H H X X L L X R0(2) H H X L X X L R9(1) L X H X L X L R9(2) X L H L X L X QD L L H Outputs QC L L L QB L L L QA L L H

COUNT COUNT COUNT COUNT

Note 1: H = High Level, L = Low Level, X = Dont Care. Note 2: Output QA is connected to input B for BCD count. Note 3: Output QD is connected to input A for bi-quinary count.

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DM7490A

Absolute Maximum Ratings(Note 4)


Supply Voltage Input Voltage 7V 5.5V Operating Free Air Temperature Range Storage Temperature Range 0C to +70C -65C to +150C

Recommended Operating Conditions


Symbol VCC VIH VIL IOH IOL fCLK tW Supply Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current Low Level Output Current Clock Frequency (Note 5) Pulse Width (Note 5) tREL TA Reset Release Time (Note 5) Free Air Operating Temperature A B A B Reset 0 0 15 30 15 25 0 70 ns C ns Parameter Min 4.75 2 0.8 0.8 16 32 16 Nom 5 Max 5.25 Units V V V mA mA MHz

Note 4: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The Recommended Operating Conditions table will define the conditions for actual device operation. Note 5: TA = 25C and VCC = 5V.

DC Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol Conditions Parameter VI VOH VOL II IIH Input Clamp Voltage High Level Output Voltage Low Level Output Voltage Input Current @ Max Input Voltage High Level Input Current IIL Low Level Input Current IOS ICC Short Circuit Output Current Supply Current
Note 6: All typicals are at VCC = 5V, TA = 25C. Note 7: QA outputs are tested at IOL = Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability. Note 8: Not more than one output should be shorted at a time. Note 9: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V, and all other inputs grounded.

Min

Typ (Note 6)

Max 1.5

Units V V

VCC = Min, II = 12 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIH = Min, VIL = Max (Note 7) VCC = Max, VI = 5.5V VCC = Max VI = 2.7V VCC = Max VI = 0.4V VCC = Max (Note 8) VCC = Max (Note 9) A Reset B A Reset B DM54 DM74 -20 18 29 0.2 2.4 3.4

0.4 1 80 40 120 3.2 1.6 4.8 -57 57 42

V mA

mA mA mA

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DM7490A

AC Switching Characteristics at VCC = 5V and TA = 25C


From (Input) Symbol Parameter To (Output) Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Maximum Clock Frequency Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time Low to High Level Output Propagation Delay Time High to Low Level Output Propagation Delay Time High to Low Level Output SET-9 to Q A , QD SET-9 to Q B , QC SET-0 Any Q 40 ns 40 ns 30 ns B to QD 35 ns B to QD 32 ns B to QC 35 ns B to QC 32 ns B to QB 21 ns B to QB 16 ns A to QD 50 ns A to QD 48 ns A to QA 18 ns A to QA B to QB A to QA 32 16 16 ns RL = 400 CL = 15 pF Max MHz Units

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DM7490A Decade and Binary Counter

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Plastic Dual-In-Line Package, JEDEC MS-001, 0.300 Wide Package Number N14A

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Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.