ECE 260A VLSI Digital Circuits & Systems Fall 2002 Lecture 04: CMOS Inverter (static view)

Paul M. Chau ( chau@ece.ucsd.edu )

[Adapted from Rabaeys Digital Integrated Circuits, 2002, J. Rabaey et al.; MJIrwin PSU 2002]
VLSI Design: L4 Static CMOS Inverter.1 Chau/Cichy UCSD ECE

Review: Design Abstraction Levels

SYSTEM

MODULE + GATE CIRCUIT

Vin Vout

DEVICE
G S n+ D n+

VLSI Design: L4 Static CMOS Inverter.2

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Review: The MOS Transistor

Gate oxide Polysilicon W Gate Source n+

L

Drain n+

Field-Oxide (SiO2)

p substrate p+ stopper Bulk (Body)

VLSI Design: L4 Static CMOS Inverter.3

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CMOS Inverter:
A First Look

VDD

Vin CL

Vout

VLSI Design: L4 Static CMOS Inverter.4

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CMOS Inverter:
Steady State Response
VDD VDD

VOL = 0 VOH = VDD VM = f(Rn, Rp)

Rp Vout = 1 Rn Vout = 0

Vin = 0
VLSI Design: L4 Static CMOS Inverter.5

Vin = V DD
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CMOS Properties
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Full rail-to-rail swing high noise margins

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Logic levels not dependent upon the relative device sizes transistors can be minimum size ratioless

Always a path to Vdd or GND in steady state low output impedance (output resistance in k range) large fan-out (albeit with degraded performance) Extremely high input resistance (gate of MOS transistor is near perfect insulator) nearly zero steady-state input current No direct path steady-state between power and ground no static power dissipation Propagation delay function of load capacitance and resistance of transistors
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VLSI Design: L4 Static CMOS Inverter.6

Review: Short Channel I-V Plot (NMOS)

2.5 2
X 10-4

VGS = 2.5V VGS = 2.0V VGS = 1.5V VGS = 1.0V

Linear dependence
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ID (A)

1.5 1 0.5 0 0 0.5 1 1.5

2.5

VDS (V) NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V
VLSI Design: L4 Static CMOS Inverter.7

Review: Short Channel I-V Plot (PMOS)

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All polarities of all voltages and currents are reversed

-2

VDS (V)

-1

0 0

VGS = -1.0V VGS = -1.5V VGS = -2.0V

-0.2 -0.4 -0.6 -0.8

VGS = -2.5V

-1 X 10-4

PMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = -0.4V

VLSI Design: L4 Static CMOS Inverter.8 Chau/Cichy UCSD ECE

ID (A)

Transforming PMOS I-V Lines

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Want common coordinate set Vin, Vout, and IDn

IDn

IDSp = -IDSn VGSn = Vin ; VGSp = Vin - VDD VDSn = Vout ; VDSp = Vout - VDD
Vout

Vin = 0 Vin = 1.5

Vin = 0 Vin = 1.5

VGSp = -1 VGSp = -2.5

Mirror around x-axis Vin = VDD + VGSp IDn = -IDp

Horiz. shift over VDD Vout = VDD + VDSp

VLSI Design: L4 Static CMOS Inverter.9

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CMOS Inverter Load Lines

PMOS

2.5
Vin = 0V

X 10-4

NMOS Vin = 2.5V

2
Vin = 0.5V 1.5 Vin = 2.0V

IDn (A)

Vin = 1.0V 1

Vin = 2V 0.5
Vin = 1.5V Vin = 2.0V

Vin = 1.5V

Vin = 1V

Vin = 1.5V

Vin = 0.5V
Vin = 1.0V Vin = 0.5V

0 0.5 1 1.5 Vout (V) 2 2.5 Vin = 0V

Vin = 2.5V 0

0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V
VLSI Design: L4 Static CMOS Inverter.10 Chau/Cichy UCSD ECE

CMOS Inverter VTC

2.5 2

Vout (V)

1.5 1 0.5 0 0 0.5 1 1.5 2 2.5

Vin (V)
VLSI Design: L4 Static CMOS Inverter.11 Chau/Cichy UCSD ECE

CMOS Inverter VTC

NMOS off PMOS res NMOS sat PMOS res

2.5 2

Vout (V)

1.5 1 0.5 0 0 0.5 1

NMOS sat PMOS sat

NMOS res PMOS sat

NMOS res PMOS off

1.5

2.5

Vin (V)
VLSI Design: L4 Static CMOS Inverter.12 Chau/Cichy UCSD ECE

CMOS Inverter:
Switch Model of Dynamic Behavior
VDD VDD

Rp Vout CL CL Rn Vout

Vin = 0

Vin = V DD

VLSI Design: L4 Static CMOS Inverter.13

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CMOS Inverter:
Switch Model of Dynamic Behavior
VDD VDD

Rp Vout CL CL Rn Vout

Vin = 0 through Rp (discharge CL through Rn)

VLSI Design: L4 Static CMOS Inverter.14

Vin = V DD

l Gate response time is determined by the time to charge C L

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Relative Transistor Sizing

When designing static CMOS circuits, balance the driving strengths of the transistors by making the PMOS section wider than the NMOS section to
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maximize the noise margins and obtain symmetrical characteristics

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Switching Threshold
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VM where Vin = Vout (both PMOS and NMOS in saturation since VDS = V GS) VM rVDD/(1 + r) where r = kpVDSATp/knVDSATn

Switching threshold set by the ratio r, which compares the relative driving strengths of the PMOS and NMOS transistors

Want VM = VDD/2 (to have comparable high and low noise margins), so want r 1 (W/L)p
=

knVDSATn(VM-VTn-VDSATn/2)

(W/L)n kpVDSATp(VDD-VM+VTp+VDSATp/2)
VLSI Design: L4 Static CMOS Inverter.16 Chau/Cichy UCSD ECE

Switch Threshold Example

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In our generic 0.25 micron CMOS process, using the process parameters from slide L03.25, a VDD = 2.5V, and a minimum size NMOS device ((W/L)n of 1.5) NMOS PMOS VT0(V) 0.43 -0.4 (V0.5) 0.4 -0.4 VDSAT(V ) 0.63 -1 k(A/V2) 115 x 10-6 -30 x 10-6 (V-1) 0.06 -0.1

(W/L)p (W/L)n

VLSI Design: L4 Static CMOS Inverter.17

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Switch Threshold Example

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In our generic 0.25 micron CMOS process, using the process parameters from slide L03.25, a VDD = 2.5V, and a minimum size NMOS device ((W/L)n of 1.5) NMOS PMOS VT0(V) 0.43 -0.4 (V0.5) 0.4 -0.4 VDSAT(V ) 0.63 -1 k(A/V2) 115 x 10-6 -30 x 10-6 (V-1) 0.06 -0.1

(W/L)p 115 x 10-6 0.63 (1.25 0.43 0.63/2)

= x x

(W/L)n

-30 x

10-6

-1.0

(1.25 0.4 1.0/2)

= 3.5

(W/L)p = 3.5 x 1.5 = 5.25 for a VM of 1.25V

VLSI Design: L4 Static CMOS Inverter.18 Chau/Cichy UCSD ECE

Simulated Inverter VM
1.5 1.4 1.3 1.2

VM is relatively insensitive to variations in device ratio

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VM (V)

1.1 1 0.9 0.8 0.1 1

~3.4

setting the ratio to 3, 2.5 and 2 gives VMs of 1.22V, 1.18V, and 1.13V
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Increasing the width of the PMOS moves VM towards VDD

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10

(W/L)p/(W/L)n
Note: x-axis is semilog
VLSI Design: L4 Static CMOS Inverter.19

Increasing the width of the NMOS moves VM toward GND

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Noise Margins Determining V IH and V IL

3
VOH = VDD

By definition, VIH and VIL are where dVout/dVin = -1 (= gain) NMH = VDD - VIH NML = VIL - GND
VM

Vout

Approximating: VIH = V M - VM /g VIL = VM + (VDD - VM )/g

VIL

VOL = GND0

Vin VIH A piece-wise linear approximation of VTC

VLSI Design: L4 Static CMOS Inverter.20

So high gain in the transition region is very desirable

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CMOS Inverter VTC from Simulation

0.25um, (W/L)p/(W/L)n = 3.4 (W/L)n = 1.5 (min size) VDD = 2.5V VM 1.25V, g = -27.5 VIL = 1.2V, VIH = 1.3V NML = NMH = 1.2 (actual values are VIL = 1.03V, VIH = 1.45V NML = 1.03V & NMH = 1.05V)
0 0.5 1 1.5 2 2.5

2.5 2

Vout (V)

1.5 1

0.5 0

Vin (V)

Output resistance low-output = 2.4k high-output = 3.3k

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VLSI Design: L4 Static CMOS Inverter.21

Gain Determinates
Vin

Gain is a strong function of the slopes of the currents in the saturation region, for Vin = VM
1.5 2

0 0 -2 -4 -6

0.5

gain

-8 -10 -12 -14 -16 -18

(1+r) g ---------------------------------(VM-VTn-VDSATn/2)(n - p ) Determined by technology parameters, especially channel length modulation (). Only designer influence through supply voltage and VM (transistor sizing).
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VLSI Design: L4 Static CMOS Inverter.22

Impact of Process Variation on VTC Curve

2.5 2
Good PMOS Bad NMOS

Vout (V)

1.5 1 0.5 0 0 0.5 1 1.5 2 2.5

Nominal Bad PMOS Good NMOS

Vin (V)
lProcess variations (mostly) cause a shift in the switching threshold
VLSI Design: L4 Static CMOS Inverter.23 Chau/Cichy UCSD ECE

Scaling the Supply Voltage

0.2

2.5 2

0.15

Vout (V)

1.5 1 0.5 0 0 0.5 1 1.5 2

Vout (V)

0.1

0.05
2.5

Gain=-1
0 0 0.05 0.1 0.15 0.2

Vin (V)
Device threshold voltages are kept (virtually) constant
VLSI Design: L4 Static CMOS Inverter.24

Vin (V)
Device threshold voltages are kept (virtually) constant
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Intro LAB: CMOS Inverter magic Layout

Out metal1 metal2 In metal1-poly via polysilicon VDD

pdiff PMOS (4/.24 = 16/1) NMOS (2/.24 = 8/1) metal1-diff via ndiff GND metal2-metal1 via

VLSI Design: L4 Static CMOS Inverter.25

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Next Lecture and Reminders

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Next lecture
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IC manufacturing
- Reading assignment Rabaey, et al, 2.1-2.3

Reminders
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HW1 due September 10th (next lecture!) Project Title due September 12th (one week) Evening midterm exam scheduled
- Wednesday, October 10th from 8:15 to 10:15pm in 260 Willard - Only one midterm conflict filed for so far

VLSI Design: L4 Static CMOS Inverter.26

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