Unit 11 Registers and Counters: Department of Communication Engineering, NCTU

Unit 11 Registers and Counters
Department of Communication Engineering, NCTU
11.1 Register and Register Transfers
Logic Design
Sau-Hsuan Wu
A 4-bit register is composed of 4 D-type FFs which share a common clock, clear (Clr) and chip enable (CE)
Logic Design
Sau-Hsuan Wu
The symbol notation for a 4-bit register
Logic Design
Sau-Hsuan Wu
Data are passed from one register to another. In this case, whether Ai or Bi is sent to Di depends on En
Logic Design
Sau-Hsuan Wu
A 8-bit register with tri-state output enable (En), and its corresponding symbol
Logic Design
Sau-Hsuan Wu
Registers use output enable (for releasing data) and chip enable (for accepting data) to transfer data on a bus
Logic Design
Sau-Hsuan Wu
Accumulator : the output of adder is fed back as one of a addend
11.2 Shift Registers
Logic Design
Sau-Hsuan Wu
A shift register is a register whose data can be shifted right or left A 4-bit right-shift register
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Logic Design
Sau-Hsuan Wu
The timing diagram of a 4-bit right shift register
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Logic Design

Sau-Hsuan Wu
A right-shift register with inverted rotation feedback Two possible output patterns which depend on the initial state This is called Johnson counter
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11.3 Design of Binary Counters
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Logic Design
Sau-Hsuan Wu
A synchronous counter is a counter whose FFs are all driven by a clock. While for a asynchronous counter, the output of FF serves as a driving clock of the next FF A 3-bit synchronous counter implemented with T-FFs
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Logic Design
Sau-Hsuan Wu
Design the functions of TC , TB , and TA with a state table and a truth table First, draw a stable which lists the present state and the next state, then draw the truth table of the functions
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Logic Design
Sau-Hsuan Wu
Logic minimizations with the Karnaugh map
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Logic Design
Sau-Hsuan Wu
For D-FFs, DA is equal to the next state of FF A. So we only need a state table for counters designed with D-FFs
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Logic Design
Sau-Hsuan Wu
An alternative design with D-FFs
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Logic Design

Sau-Hsuan Wu
Design of up-down counter The state table and the state graph of a up-down counter
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Logic Design
Sau-Hsuan Wu
The logic functions of inputs
One can verify the function by setting U=0 and D=1, or vice versus. For example, U=0 and D=1
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Logic Design
Sau-Hsuan Wu
A up-down counter synthesized with D-FFs
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Logic Design
Sau-Hsuan Wu
Design of loadable counter with count enable
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Logic Design
Sau-Hsuan Wu
The next-state equations
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Logic Design

Sau-Hsuan Wu
Design of loadable up-dn counter with count enable? Realize this counter with GAL 22V10 Due on the next meet
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11.4 Counter of Other Sequences
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Logic Design

Sau-Hsuan Wu
A five state counter Define the next states of three unused states 001101110 as unspecified The counter can be realized with T-FFs
T =present state next state List the truth table for the next states of TA , TB , TC Use the Karnaugh map
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Logic Design

Sau-Hsuan Wu
Notice that T = Q+ Q So, first design Q+ = f (A,B,C) Use Karnaugh map for Q=0 and Q=1, respectively

For Q=0, have T = Q+ For Q=1, have T = (Q+ )
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Logic Design
Sau-Hsuan Wu
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Logic Design
Sau-Hsuan Wu
After simplification
TA C B TB C A CB TC C B CB
Notice that even if the next state of 001101 and 110 are not specified at the beginning, they are assigned certain values implicitly while being used as the don t care conditions for circuit simplifications
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Logic Design
Sau-Hsuan Wu
Circuit realization
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Logic Design
Sau-Hsuan Wu
The effects of don t care conditions

When CBA=001, TC TB TA = 110, then C+B+A+ =111 When CBA=101, TC TB TA = 011, then C+B+A+ =110 When CBA=110, TC TB TA = 101, then C+B+A+ =011
The final counter
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Logic Design

Sau-Hsuan Wu
An alternative design with D-FFs This is much easier since DC = C+, DB = B+ and DA = A+ So, the functions are
DC B DB C BA DA CA BA A (C B)
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11.5 Derivation of Flip-Flop Input Equations
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Logic Design
Sau-Hsuan Wu
In counter design, we mainly derive the input equations of FFs. This can be done either with the true table of the present states and the next states, or with the next-state map
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Logic Design
Sau-Hsuan Wu
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Logic Design
Sau-Hsuan Wu
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Unit 11 Registers and Counters: Department of Communication Engineering, NCTU

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Unit 11 Registers and Counters: Department of Communication Engineering, NCTU

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Unit 11 Registers and Counters

Department of Communication Engineering, NCTU

11.1 Register and Register Transfers

Department of Communication Engineering, NCTU