February 2013 (Spring drive) Bachelor of Computer Application (BCA) Semester 3 BC0046 Microprocessor

(Book ID: B0807)

4 Credits

(60 Marks)

Answer all questions.

[10 x 6 = 60]

1. Write an assembly language program to find the highest among two numbers.

2. Program 3. MVI D, 8BH 4. MVI C, 6FH 5. MOV A, C 6. ADD D 7. OUT PORT1 8. HLT
2. Draw and explain the internal architecture of 8085 briefly.

Figure 3.1 shows the internal architecture of the 8085. Except for the instruction register, which is actually a 6-byte queue, the control unit and working registers are divided into three groups according to their functions. There is a data group, which is essentially the set of arithmetic registers; the pointer group, which includes base and index registers, but also contains the program counter and stack pointer; and the segment group, which is a set of special purpose base registers. All of the registers are 16 bits wide. The data group consists of the AX, BX, CX and DX registers. These registers can be used to store both operands and results and each of them can be accessed as a whole, or the upper and lower bytes can be accessed separately. For example, either the 2 bytes in BX can be used together, or the upper byte BH or the lower byte BL can be used by itself by specifying BH or BL, respectively.

Fig 3.1: Internal Architecture of 8086

In addition to serving as arithmetic registers, the BX, CX and DX registers play special addressing, counting, and I/O roles: BX may be used as a base register in address calculations. CX is used as an implied counter by certain instructions. DX is used to hold the I/O address during certain I/O operations. The pointer and index group consists of the IP, SP, BP, SI, and DI registers. The instruction pointer IP and SP registers are essentially the program counter and stack pointer registers, but the complete instruction and stack addresses are formed by adding the contents of these registers to the contents of the code segment (CS) and stack segment (SS) registers. BP is a base register for accessing the stack and may be used with other registers and/or a displacement that is part of the instruction. The SI and DI registers are for indexing. Although they may be used by themselves, they are often used with the BX or BP registers and/or a displacement. Except for the IP, a pointer can be used to hold an operand, but must be accessed as a whole. To provide flexible base addressing and indexing, a data address may be formed by adding together a combination of the BX or BP register contents, SI or DI register contents, and a displacement. The result of such an address computation is called an effective address (EA) or offset. The word displacement is used to indicate a quantity that is added to the contents of a register(s) to form an EA. The final data address, however, is determined by the EA and the appropriate data segment (DS), extra segment (ES), or stack segment (SS) register. The segment group consists of the CS, SS, DS, and ES registers. As indicated above, the registers that can be used for addressing, the BX, IP, SP, BP, SI, and DI registers, are only 16 bits wide and, therefore, an effective address has only 16 bits. On the other hand, the address put on the address bus, called the physical address, must contain 20 bits. The extra 4 bits are obtained by adding the effective address to the contents of one of the segment registers as shown in Fig. 3.2. The addition is carried out by appending four 0 bits to the right of the number in the segment register before the addition is made; thus a 20-bit result is produced. As an example, if (CS) = 1234 and (IP) = 0002, then the next instruction will be fetched from 0002 Effective address + 12340 beginning segment address

12342 Physical address of instruction [It is standard notation for parentheses around an entity to mean "contents of," e.g., (IP) means the contents of IP. Also, all addresses are given in hexadecimal.]

Fig. 3.2 Generation of physical Address

The utilization of the segment registers essentially divide the memory space into overlapping segments, with each segment being 64K bytes long and beginning at a 16-byte, or paragraph, boundary, i.e., beginning at an address that is divisible by 16. We will hereafter refer to the contents of a segment register as the segment address, and the segment address multiplied by 16 as the beginning physical segment address, or simply, the beginning segment address. An illustration of the example above is given in Fig.3.3( a) and the overall segmentation of memory is shown in Fig. 3.3(b).
3. Explain the concept of Linking and Relocation.

Linking and Relocation In constructing a program some program modules may be put in the same source module and assembled together; others may be in different source modules and assembled separately. If they are assembled separately, then the main module, which has the first instruction to be executed, must be terminated by an END statement with the entry point specified, and each of the other modules must be terminated by an END statement with no operand. In any event, the resulting object modules, some of which may be grouped into libraries, must be linked together to form a load module before the program can be executed. In addition to outputting the load module, normally the linker prints a memory map that indicates where the linked object modules will be loaded into memory. After the load module has been created it is loaded into the memory of the computer by the loader and execution begins. Although the I/O can be performed by modules within the program, normally the I/O is done by I/O drivers that are part of the operating system. All that appears in the users program are references to the I/O drivers that cause the operating system to execute them. The general process for creating and executing a program is illustrated in Fig 5.1. The process for a particular system may not correspond exactly to the one diagrammed in the figure, but the general concepts are the same. The arrows indicate that corrections may be made after anyone of the major stages.

Fig. 5.1: Creation and Execution of a program

Segment Combination In addition to the linker commands, the ASM-86 assembler provides a means of regulating the way segments in different object modules are organized by the linker. Sometimes segments with the same name are concatenated and sometimes they are overlaid. Just how the segments with the same name are joined together is determined by modifiers attached to the SEGMENT directives. A SEGMENT directive may have the form Segment name SEGMENT Combine-type where the combine-type indicates how the segment is to be located within the load module. Segments that have different names cannot be combined and segments with the same name but no combine-type will cause a linker error. The possible combinetypes are: PUBLIC-If the segments in different object modules have the same name and the combine-type PUBLIC, then they are concatenated into a single segment in the load module. The ordering in the concatenation is specified by the linker command. COMMON-If the segments in different object modules have the same name and the combine-type is COMMON, then they are overlaid so that they have the same beginning address. The length of the common segment is that of the longest segment being overlaid. STACK-If segments in different object modules have the same name and the combine-type STACK, then they become one segment whose length is the sum of the lengths of the individually specified segments. In effect, they are combined to form one large stack. AT-The AT combine-type is followed by an expression that evaluates to a constant which is to be the segment address. It allows the user to specify the exact location of the segment in memory.. MEMORY-This combine-type causes the segment to be placed at the last of the load module. If more than one segment with the MEMORY combine type is being linked, only

the first one will be treated as having the MEMORY combine-type; the others will be overlaid as if they had COMMON combine types. Access to External Identifiers Clearly, object modules that are being linked together must be able to refer to each other. That is, there must be a way for a module to reference at least some of the variables and/or labels in the other modules. If an identifier is defined in an object module, then it is said to be a local (or internal) identifier relative to the module, and if it is not defined in the module but is defined in one of the other modules being linked, then It is referred to as an external (or global) identifier relative to the module. For single-object module programs all identifiers that are referenced must be locally defined or an assembler error will occur. For multiple-module programs, the assembler must be informed in advance of any externally defined identifiers that appear in a module so that it will not treat them as being undefined. Also, in order to permit other object modules to reference some of the identifiers in a given module, the given module must include a list of the identifiers to which it will allow access. Therefore, each module may contain two lists, one containing the external identifiers it references and one containing the locally defined identifiers that can be referred to by other modules. These two lists are implemented by the EXTRN and PUBLIC directives, which have the forms: EXTRN Identifier:Type, . . . , Identifier:Type and PUBLIC Identifier, . . ., Identifier where the identifiers are the variables and labels being declared as external or as being available to other modules. Because the assembler must know the type of all external identifiers before it can generate the proper machine code, a type specifier must be associated with each identifier in an EXTRN statement. For a variable the type may be BYTE, WORD, or DWORD and for a label it may be NEAR or FAR. In the statement INC VAR1 if VAR1 is external and is associated with a word, then the module containing the statement must also contain a directive such as EXTRN . . VAR1 :WORD.. . . and the module in which VARl is defined must contain a statement of the form PUBLIC .. ..VAR1. One of the primary tasks of the linker is to verify that every identifier appearing in an EXTRN statement is matched by one in a PUBLIC statement. If this is not the case, then there will be an undefined external reference and a linker error will occur. Fig. 5.2 shows three modules and how the matching is done by the linker while joining them together.

Fig. 5.2: Illustration of the matching verified by the linker

As we have seen, there are two parts to every address, an offset and a segment address. The offsets for the local identifiers can be and are inserted by the assembler, but the offsets for the external identifiers and all segment addresses must be inserted by the linking process. The offsets associated with all external references can be assigned once all of the object modules have been found and their external symbol tables have been examined. The assignment of the segment addresses is called relocation and is done after the king process has determined exactly where each segment is to be put in memory.

4. Define macros and procedures. In what way is Procedures better than macros.

A macro is a group of repetitive instructions in a program which are codified only once and can be used as many times as necessary. The main difference between a macro and a procedure is that in the macro the passage of parameters is possible and in the procedure it is not, this is only applicable for the MASM - there are other programming languages which do allow it. At the moment the macro is executed each parameter is substituted by the name or value specified at the time of the call. We can say then that a procedure is an extension of a determined program, while the macro is a module with specific functions which can be used by different programs. Another difference between a macro and a procedure is the way of calling each one, to call a procedure the use of a directive is required, on the other hand the call of macros is done as if it were an assembler instruction. Example of procedure: For example, if we want a routine which adds two bytes stored in AH and AL each one, and keep the addition in the BX register: Adding Proc Near ; Declaration of the procedure

Mov Bx, 0 ; Content of the procedure Mov B1, Ah Mov Ah, 00 Add Bx, Ax Ret ; Return directive Add Endp ; End of procedure declaration and an example of Macro: Position MACRO Row, Column PUSH AX PUSH BX PUSH DX MOV AH, 02H MOV DH, Row MOV DL, Column MOV BH, 0 INT 10H POP DX POP BX POP AX ENDM
5. Explain the function of any 3 flag of a 8086 flag register with examples.

8086 CPU has 8 general purpose registers, each register has its own name:
AX - the accumulator register (divided into AH / AL): 1. Generates shortest machine code 2. Arithmetic, logic and data transfer 3. One number must be in AL or AX 4. Multiplication & Division 5. Input & Output BX - the base address register (divided into BH / BL). CX - the count register (divided into CH / CL): 1. Iterative code segments using the LOOP instruction 2. Repetitive operations on strings with the REP command 3. Count (in CL) of bits to shift and rotate DX - the data register (divided into DH / DL): 1. DX:AX concatenated into 32-bit register for some MUL and DIV operations 2. Specifying ports in some IN and OUT operations SI - source index register:

1. Can be used for pointer addressing of data 2. Used as source in some string processing instructions 3. Offset address relative to DS DI - destination index register: 1. Can be used for pointer addressing of data 2. Used as destination in some string processing instructions 3. Offset address relative to ES BP - base pointer: 1. Primarily used to access parameters passed via the stack 2. Offset address relative to SS SP - stack pointer: 1. Always points to top item on the stack 2. Offset address relative to SS 3. Always points to word (byte at even address) 4. An empty stack will had SP = FFFEh

SEGMENT REGISTERS
CS - points at the segment containing the current program.

DS - generally points at segment where variables are defined. ES - extra segment register, it's up to a coder to define its usage. SS - points at the segment containing the stack. Although it is possible to store any data in the segment registers, this is never a good idea. The segment registers have a very special purpose - pointing at accessible blocks of memory. Segment registers work together with general purpose register to access any memory value. For example if we would like to access memory at the physical address 12345h (hexadecimal), we could set the DS = 1230h and SI = 0045h. This way we can access much more memory than with a single register, which is limited to 16 bit values. The CPU makes a calculation of the physical address by multiplying the segment register by 10h and adding the general purpose register to it (1230h * 10h + 45h = 12345h):

The address formed with 2 registers is called an effective address. By default BX, SI and DI registers work with DS segment register; BP and SP work with SS segment register.

Other general purpose registers cannot form an effective address. Also, although BX can form an effective address, BH and BL cannot.

SPECIAL PURPOSE REGISTERS

IP - the instruction pointer: 1. Always points to next instruction to be executed 2. Offset address relative to CS

IP register always works together with CS segment register and it points to currently executing instruction.

FLAGS REGISTER
Flags Register - determines the current state of the processor. They are modified automatically by CPU after mathematical operations, this allows to determine the type of the result, and to determine conditions to transfer control to other parts of the program. Generally you cannot access these registers directly.

1. Carry Flag (CF) - this flag is set to 1 when there is an unsigned overflow. For example when you add bytes 255 + 1 (result is not in range 0...255). When there is no overflow this flag is set to 0. 2. Parity Flag (PF) - this flag is set to 1 when there is even number of one bits in result, and to 0 when there is odd number of one bits. 3. Auxiliary Flag (AF) - set to 1 when there is an unsigned overflow for low nibble (4 bits). 4. Zero Flag (ZF) - set to 1 when result is zero. For non-zero result this flag is set to 0. 5. Sign Flag (SF) - set to 1 when result is negative. When result is positive it is set to 0. (This flag takes the value of the most significant bit.) 6. Trap Flag (TF) - Used for on-chip debugging. 7. Interrupt enable Flag (IF) - when this flag is set to 1 CPU reacts to interrupts from external devices. 8. Direction Flag (DF) - this flag is used by some instructions to process data chains, when this flag is set to 0 - the processing is done forward, when this flag is set to 1 the processing is done backward. 9. Overflow Flag (OF) - set to 1 when there is a signed overflow. For example, when you add bytes 100 + 50 (result is not in range -128...127).

6. What are the advantages of the MOVS and CMPS instructions over the MOV and CMP instructions? Explain.

When working with strings, the advantages of the MOVS and CMPS instructions over the MOV and CMP instructions are: 1. They are only 1 byte long. 2. Both operands are memory operands. 3. Their auto-indexing obviates the need for separate incrementing or decrementing instructions, thus decreasing overall processing time. As an example consider the problem of moving the contents of a block of memory to another area in memory. A solution that uses only the MOV instruction, which cannot perform a memory-to-memory transfer, is shown in Fig. 6.2(a).

Fig. 6.2: Program sequences for moving a block of data A solution that employs the MOVS instruction is given in Fig. 6.2(b). Note that the second program sequence may move either bytes or words, depending on the type of STRING1 and STRING2.

7. What is interrupt? How does the computer respond to interrupts? Explain.

In systems programming, an interrupt is a signal to the processor emitted by hardware or software indicating an event that needs immediate attention. An interrupt alerts the processor to a high-priority condition requiring the interruption of the current code the processor is executing, the current thread. The processor responds by suspending its current activities, saving its state, and executing a small program called an interrupt handler (or interrupt service routine, ISR) to deal with the event. This interruption is temporary, and after the interrupt handler finishes, the processor resumes execution of the previous thread. There are two types of interrupts: A hardware interrupt is an electronic alerting signal sent to the processor from an external device, either a part of the computer itself such as a disk controller or an external peripheral. For example, pressing a key on thekeyboard or moving the mouse triggers hardware interrupts that cause the processor to read the keystroke or mouse position. Unlike the software type (below), hardware interrupts are asynchronous and can occur in the middle of instruction execution, requiring additional care in programming. The act of initiating a hardware interrupt is referred to as an interrupt request (IRQ). A software interrupt is caused either by an exceptional condition in the processor itself, or a special instruction in the instruction set which causes an interrupt when it is executed. The former is often called a trap or exception and is used for errors or events occurring during program execution that are exceptional enough that they cannot be handled within the program itself. For example, if the processor's arithmetic logic unit is commanded to divide a number by zero, this impossible demand will cause a divide-by-zero exception, perhaps causing the computer to abandon the calculation or display an error message. Software interrupt instructions function similarly to subroutine calls and are used for a variety of purposes, such as to request services from low level system software such as device drivers. For example, computers often use software interrupt instructions to communicate with the disk controller to request data be read or written to the disk. Each interrupt has its own interrupt handler. The number of hardware interrupts is limited by the number of interrupt request (IRQ) lines to the processor, but there may be hundreds of different software interrupts.

9. Draw and explain Process states and state changes.

The following typical process states are possible on computer systems of all kinds. In most of these states, processes are "stored" on main memory.

Created [edit]
(Also called New) When a process is first created, it occupies the "created" or "new" state. In this state, the process awaits admission to the "ready" state. This admission will be approved or delayed by a longterm, or admission, scheduler. Typically in most desktop computersystems, this admission will be approved automatically, however for real-time operating systems this admission may be delayed. In a real time system, admitting too many processes to the "ready" state may lead to oversaturation and overcontention for the systems resources, leading to an inability to meet process deadlines.

Ready or waiting [edit]

A "ready" or "waiting" process has been loaded into main memory and is awaiting execution on a CPU (to be context switched onto the CPU by the dispatcher, or short-term scheduler). There may be many "ready" processes at any one point of the system's executionfor example, in a one-processor system,

only one process can be executing at any one time, and all other "concurrently executing" processes will be waiting for execution. A ready queue or run queue is used in computer scheduling. Modern computers are capable of running many different programs or processes at the same time. However, the CPU is only capable of handling one process at a time. Processes that are ready for the CPU are kept in a queue for "ready" processes. Other processes that are waiting for an event to occur, such as loading information from a hard drive or waiting on an internet connection, are not in the ready queue.

Running
A process moves into the running state when it is chosen for execution. The process's instructions are executed by one of the CPUs (or cores) of the system. There is at most one running process per CPU or core.

10. Explain the 8288 Bus controller.

For reasons of simplicity, flexibility, and low cost, most microcomputers, including those involving multiprocessor configurations, are built around a primary system bus which connects all of the major components in the system. In order to obtain a foundation while designing its products, a microcomputer manufacturer makes assumptions about the bus that is to be used to connect its devices together Frequently, these assumptions become formalized and constitute what is referred to as a bus standard The Intel MULTIBUS has gained wide industrial acceptance and several manufacturers offer MULTIBUS-compatible modules. This bus is designed to support both 8-bit and 16bit devices and can be used in multiprocessor systems in which several processors can be masters. At any point in time, only two devices may communicate with each other over the bus, one being the master and the other the slave. The master/slave relationship is dynamic with bus allocation being accomplished through the bus allocation (i.e., request/grant) control signals. The MULTIBUS has been physically implemented on an etched backplane board which is connected to each module using two edge connectors, denoted PI and P2, I shown in Fig. 9.13. The connector P1 consists of 86 pins which provide-the major bus signals, and P2 is an optional connector consisting of 60 auxiliary lines, primarily used for power failure detection and handling.

Fig. 9.13: Illustration of a module being plugged into MULTIBUS The P1 lines can be divided into the following groups according to their functions: 1. Address lines. 2. Data lines. 3. Command and handshaking lines. 4. Bus access control lines. 5. Utility lines. The MULTIBUS has 20 address lines, labeled through , where the numeric suffix represents the address bit in hexadecimal. The address lines are driven by the bus master to specify the memory location or I/O port being accessed.. The MULTIBUS standard calls for all single bytes to be communicated over only the lower 8 bits of the bus; therefore, any 16-bit interface must include a swap byte buffer so that only the lower data lines are used for all byte transfers. (It should be pointed out that because an 8086 expects a byte to be put on the high-order byte of the bus when is active, one may want to permit nonstandard MULTIBUS transfers between memory and an 8086.) The two inhibit signals are provided for overlaying RAM, ROM, and auxiliary ROM in a common address space. For example, a bootstrap loader may be stored in an auxiliary ROM and a monitor in a ROM. Because the loader is needed only after a reset, and

could both be activated while the loader is executing.Then, when the monitor is in control, could be raised while remains low. If control is passed to the user,

and could both be deactivated, thus allowing the RAM to fill the entire memory space during normal operation. There are 16 bidirectional data lines ( ), only eight of which are used in an 8-bit system. Data transfers on the MULTIBUS bus are accomplished by handshaking signals in a manner similar to that described in the preceding sections. The memory read ( ), memory write ( ), I/O read ( ), and I/O write ( ) lines are defined to be the same as they were in the discussion of the 8288 bus controller. There is an acknowledge ( ) signal which serves the same purpose as the READY signal in the discussion of the bus control logic, i.e., to verify the end of a transfer. In a general setting it may be received by bus master. Because a master must wait to be notified of the completion transfer, the duration of a bus cycle varies depending on the speed of the bus master and the slave. This asynchronous nature enables the system to handle slow devices without penalizing fast devices

10. Explain how 8086 and its coprocessor interacts when an instruction is executed by the coprocessor.

Figure 3.1 shows the internal architecture of the 8086. Except for the instruction register, which is actually a 6-byte queue, the control unit and working registers are divided into three groups according to their functions. There is a data group, which is essentially the set of arithmetic registers; the pointer group, which includes base and index registers, but also contains the program counter and stack pointer; and the segment group, which is a set of special purpose base registers. All of the registers are 16 bits wide. The data group consists of the AX, BX, CX and DX registers. These registers can be used to store both operands and results and each of them can be accessed as a whole, or the upper and lower bytes can be accessed separately. For example, either the 2 bytes in BX can be used together, or the upper byte BH or the lower byte BL can be used by itself by specifying BH or BL, respectively.

Fig 3.1: Internal Architecture of 8086

In addition to serving as arithmetic registers, the BX, CX and DX registers play special addressing, counting, and I/O roles: BX may be used as a base register in address calculations. CX is used as an implied counter by certain instructions. DX is used to hold the I/O address during certain I/O operations. The pointer and index group consists of the IP, SP, BP, SI, and DI registers. The instruction pointer IP and SP registers are essentially the program counter and stack pointer registers, but the complete instruction and stack addresses are formed by adding the contents of these registers to the contents of the code segment (CS) and stack segment (SS) registers. BP is a base register for accessing the stack and may be used with other registers and/or a displacement that is part of the instruction. The SI and DI registers are for indexing. Although they may be used by themselves, they are often used with the BX or BP registers and/or a displacement. Except for the IP, a pointer can be used to hold an operand, but must be accessed as a whole. To provide flexible base addressing and indexing, a data address may be formed by adding together a combination of the BX or BP register contents, SI or DI register contents, and a displacement. The result of such an address computation is called an effective address (EA) or offset. The word displacement is used to indicate a quantity that is added to the contents of a register(s) to form an EA. The final data address,

however, is determined by the EA and the appropriate data segment (DS), extra segment (ES), or stack segment (SS) register. The segment group consists of the CS, SS, DS, and ES registers. As indicated above, the registers that can be used for addressing, the BX, IP, SP, BP, SI, and DI registers, are only 16 bits wide and, therefore, an effective address has only 16 bits. On the other hand, the address put on the address bus, called the physical address, must contain 20 bits. The extra 4 bits are obtained by adding the effective address to the contents of one of the segment registers as shown in Fig. 3.2. The addition is carried out by appending four 0 bits to the right of the number in the segment register before the addition is made; thus a 20-bit result is produced. As an example, if (CS) = 1234 and (IP) = 0002, then the next instruction will be fetched from 0002 Effective address + 12340 beginning segment address 12342 Physical address of instruction [It is standard notation for parentheses around an entity to mean "contents of," e.g., (IP) means the contents of IP. Also, all addresses are given in hexadecimal.]

Fig. 3.2 Generation of physical Address

The utilization of the segment registers essentially divide the memory space into overlapping segments, with each segment being 64K bytes long and beginning at a 16byte, or paragraph, boundary, i.e., beginning at an address that is divisible by 16. We will hereafter refer to the contents of a segment register as the segment address , and the segment address multiplied by 16 as the beginning physical segment address , or simply, the beginning segment address. An illustration of the example above is given in Fig.3.3( a) and the overall segmentation of memory is shown in Fig. 3.3(b). The advantages of using segment registers are that they: 1. Allow the memory capacity to be 1 MB even though the addresses associated with the individual instructions are only 16 bits wide. 2. Allows the instruction, data, or stack portion of a program to be more than 64K bytes long by using more than one code, data, or stack segment. 3. Facilitate the use of separate memory areas for a program, its data, and the stack.Permit a program and/or its data to be put into different areas of memory each time the program is executed.

Fig 3.3 Memory segmentation The 8086s PSW contains 16 bits, but 7 of them are not used. Each bit in the PSW is called a flag. The 8086 flags are divided into the conditional flags, which reflect the result of the previous operation involving the ALU, and the control flags, which control the execution of special functions. The flags are summarized in Fig. 3.4. The condition flags are: SF (Sign FIag)-Is equal to the MSB of the result. Since in 2s complement negative numbers have a 1 in the MSB and for nonnegative numbers this bit is 0, this flag indicates whether the previous result was negative or nonnegative. ZF (Zero Flag)-Is set to 1 if the result is zero and 0 if the result is nonzero. PF (Parity Flag)-Is set to 1 if the low-order 8 bits of the result contains an even number of 1s; otherwise it is cleared. CF (Carry Flag)-An addition causes this flag to be set if there is a carry out of the MSB, and a subtraction causes it to be set if a borrow is needed. Other instructions also affect this flag and its value will be discussed when these instructions are defined. AF (Auxiliary Carry Flag)-Is set if there is a carry out of bit 3 during an addition or a borrow by bit 3 during a subtraction. This flag is used exclusively for BCD arithmetic. OF (Overflow Flag)-Is set if an overflow occurs, i.e., a result is out of range. More specifically, for addition this flag is set when there is a carry into the MSB and no carry out of the MSB or vice versa. For subtraction, it is set when the MSB needs a borrow and there is no borrow from the MSB or vice versa. As an example, if the previous instruction performed the addition 0010 0011 0100 1101 + 0011 0010 0001 0001 0101 0101 0101 1110 then following the instruction: SF=0 ZF=0 PF=0 CF=0 AF=0 OF=0

Fig 3.4: PSW register of 8086

If the previous instruction performed the addition 0101 0100 0011 1001 + 0100 0101 0110 1010 1001 1001 1010 0011 then the flags would be: SF = 1 ZF = 0 PF = 1 CF = 0 AF = 1 CF = 1 The control flags are: DF (Direction Flag)-Used by string manipulation instructions. If zero, the string is processed from its beginning with the first element having the lowest address. Otherwise, the string is processed from the high address towards the low address. IF (Interrupt Enable Flag)-If set, a certain type of interrupt (a maskable interrupt) can be recognized by the CPU; otherwise, these interrupts are ignored. TF (Trap Flag)-If set, a trap is executed after each instruction.