LT084

TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS
SLOS081E FEBRUARY 1977 REVISED FEBRUARY 1999
D D D D D
Low Power Consumption Wide Common-Mode and Differential Voltage Ranges Low Input Bias and Offset Currents Output Short-Circuit Protection Low Total Harmonic Distortion . . . 0.003% Typ
D D D D
High Input Impedance . . . JFET-Input Stage Latch-Up-Free Operation High Slew Rate . . . 13 V/s Typ Common-Mode Input Voltage Range Includes VCC+
description
The TL08x JFET-input operational amplifier family is designed to offer a wider selection than any previously developed operational amplifier family. Each of these JFET-input operational amplifiers incorporates well-matched, high-voltage JFET and bipolar transistors in a monolithic integrated circuit. The devices feature high slew rates, low input bias and offset currents, and low offset voltage temperature coefficient. Offset adjustment and external compensation options are available within the TL08x family. The C-suffix devices are characterized for operation from 0C to 70C. The I-suffix devices are characterized for operation from 40C to 85C. The Q-suffix devices are characterized for operation from 40C to 125C. The M-suffix devices are characterized for operation over the full military temperature range of 55C to 125C.
symbols
TL081 OFFSET N1 IN + IN OFFSET N2 + OUT IN + IN + OUT TL082 (EACH AMPLIFIER) TL084 (EACH AMPLIFIER)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TL081M U PACKAGE (TOP VIEW)
TL082M U PACKAGE (TOP VIEW)
NC OFFSET N1 IN IN+ VCC
1 2 3 4 5
10 9 8 7 6
NC NC VCC+ OUT OFFSET N2
NC 1OUT 1IN 1IN+ VCC
1 2 3 4 5
10 9 8 7 6
NC VCC+ 2OUT 2IN 2IN+
TL081, TL081A, TL081B D, JG, P, OR PW PACKAGE (TOP VIEW)
TL082, TL082A, TL082B D, JG, P, OR PW PACKAGE (TOP VIEW)
OFFSET N1 IN IN + VCC
1 2 3 4
8 7 6 5
NC VCC + OUT OFFSET N2
1OUT 1IN 1IN + VCC
1 2 3 4
8 7 6 5
VCC + 2OUT 2IN 2IN +
TL081M . . . FK PACKAGE (TOP VIEW)
NC OFFSET N1 NC NC NC
NC IN NC IN + NC
3 2 1 20 19 18 4 5 6 7 8 17 16 15 14 9 10 11 12 13
NC VCC + NC OUT NC
NC 1IN NC 1IN + NC
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
NC 1OUT NC VCC+ NC NC 2OUT NC 2IN NC

TL084, TL084A, TL084B D, J, N, PW, OR W PACKAGE (TOP VIEW)
NC VCC NC OFFSET N2 NC
NC No internal connection
DALLAS, TEXAS 75265
2IN 2OUT NC 3OUT 3IN
1OUT 1IN 1IN + VCC + 2IN + 2IN 2OUT
1 2 3 4 5 6
14 13 12 11 10 9
4OUT 4IN 4IN + VCC 3IN + 3IN 3OUT
1IN + NC VCC + NC 2IN +
4 5 6 7 8
3 2 1 20 19 18 17 16 15 14 9 10 11 12 13
1IN 1OUT NC 4OUT 4IN 4IN + NC VCC NC 3IN +
NC VCC NC 2IN + NC
AVAILABLE OPTIONS PACKAGED DEVICES TA VIOmax AT 25C 15 mV 6 mV 3 mV 0C to 70C 15 mV 6 mV 3 mV 15 mV 6 mV 3 mV 40C to 85C 40C to 125C 55C to 125C 6 mV 6 mV 6 mV
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SMALL OUTLINE (D008) TL081CD TL081ACD TL081BCD TL082CD TL082ACD TL082BCD TL081ID TL082ID TL084ID
SMALL OUTLINE (D014)
CHIP CARRIER (FK)
CERAMIC DIP (J)
CERAMIC DIP (JG)
PLASTIC DIP (N)
PLASTIC DIP (P) TL081CP TL081ACP TL081BCP TL082CP TL082ACP TL082BCP TL081IP TL082IP
TSSOP (PW) TL081CPW
FLAT PACK (U)
FLAT PACK (W)
CHIP FORM (Y)
TL082Y
TL082CPW TL084CPW
TL084CD TL084ACD TL084BCD
TL084CN TL084ACN TL084BCN
TL084Y
TL084ID TL084QD TL081MFK TL082MFK TL084MFK
TL084IN
TL081MJG TL082MJG
TL081MU TL082MU
9 mV 6 mV 6 mV 9 mV
TL084MW
TL084MJ
The D package is available taped and reeled. Add R suffix to the device type (e.g., TL081CDR).
schematic (each amplifier)

VCC +
IN + 64 OUT 128 64 C1
IN
1080 VCC OFFSET N1
1080
OFFSET N2
TL081 Only Component values shown are nominal.
DALLAS, TEXAS 75265
TL082Y chip information

These chips, when properly assembled, display characteristics similar to the TL082. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(7)
(6)
(5) 1IN + 1IN 2OUT (7) (3) (2) +
VCC+ (8) (1) 1OUT + (5) (6) 2IN + 2IN
61
(8)
(4)
(4) VCC CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 4 MINIMUM TJmax = 150C TOLERANCES ARE 10%. ALL DIMENSIONS ARE IN MILS.
(1) 61
(2)
(3)
PIN (4) IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP.
DALLAS, TEXAS 75265
TL084Y chip information

These chips, when properly assembled, display characteristics similar to the TL084. Thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS VCC+ (4) + + + + (11) VCC
(2) (3) (4) (6)
1IN + 1IN 2OUT 3IN +

(14) (8) (7)
(3) (2)
(1) 1OUT (5) (6) (8) 3OUT (12) (13) 4IN + 4IN 2IN + 2IN
(13)
(12)
(11)
(10)
(9)
(7) (10) (9)
62
3IN 4OUT (14)
(1)
105
CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 4 MINIMUM TJmax = 150C TOLERANCES ARE 10%. ALL DIMENSIONS ARE IN MILS. PIN (11) IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP.
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
TL08_C TL08_AC TL08_BC Supply voltage, VCC + (see Note 1) Supply voltage VCC (see Note 1) Differential input voltage, VID (see Note 2) Input voltage, VI (see Notes 1 and 3) Duration of output short circuit (see Note 4) Continuous total power dissipation Operating free-air temperature range, TA Storage temperature range, Tstg Case temperature for 60 seconds, TC Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds FK package J or JG package D, N, P, or PW package 260 260 260 0 to 70 65 to 150 18 18 30 15 unlimited TL08_I 18 18 30 15 unlimited 40 to 85 65 to 150 TL084Q 18 18 30 15 unlimited 40 to 125 65 to 150 TL08_M 18 18 30 15 unlimited 55 to 125 65 to 150 260 300 C C C C C UNIT V V V V
See Dissipation Rating Table
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between VCC + and VCC . 2. Differential voltages are at IN+ with respect to IN . 3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less. 4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the dissipation rating is not exceeded. DISSIPATION RATING TABLE PACKAGE D (8 pin) D (14 pin) FK J JG N P PW (8 pin) PW (14 pin) U W TA 25C POWER RATING 680 mW 680 mW 680 mW 680 mW 680 mW 680 mW 680 mW 525 mW 700 mW 675 mW 680 mW DERATING FACTOR 5.8 mW/C 7.6 mW/C 11.0 mW/C 11.0 mW/ C 8.4 mW/C 9.2 mW/C 8.0 mW/C 4.2 mW/C 5.6 mW/C 5.4 mW/C 8.0 mW/C DERATE ABOVE TA 32C 60C 88C 88C 69C 76C 65C 25C 25C 25C 65C TA = 70C POWER RATING 460 mW 604 mW 680 mW 680 mW 672 mW 680 mW 640 mW 336 mW 448 mW 432 mW 640 mW TA = 85C POWER RATING 373 mW 490 mW 680 mW 680 mW 546 mW 597 mW 520 mW N/A N/A 351 mW 520 mW TA = 125C POWER RATING N/A 186 mW 273 mW 273 mW 210 mW N/A N/A N/A N/A 135 mW 200 mW
DALLAS, TEXAS 75265
electrical characteristics, VCC = 15 V (unless otherwise noted)

PARAMETER TEST CONDITIONS TA MIN VIO VIO Input offset voltage Temperature coefficient of input offset voltage Input offset current Input bias current Common-mode input voltage range RL = 10 k RL 10 k RL 2 k VO = 10 V, VO = 10 V, RL 2 k RL 2 k VO = 0 RS = 50 RS = 50 25C Full range Full range 25C Full range 25C Full range 25C 25C Full range 25C Full range 25C 25C VIC = VICRmin, VO = 0, RS = 50 VCC = 15 V to 9 V, VO = 0, RS = 50 VO = 0, No load 25C 70 11 12 12 10 25 15 3 1012 86 75 12 200 12 to 15 13.5 30 18 5 200 2 400 10 11 12 12 10 50 25 3 1012 86 75 12 200 12 to 15 13.5 30 TL081C TL082C TL084C TYP 3 MAX 15 20 18 5 100 2 200 7 11 12 12 10 50 25 3 1012 86 75 12 200 12 to 15 13.5 30 MIN TL081AC TL082AC TL084AC TYP 3 MAX 6 7.5 18 5 100 2 200 7 11 12 12 10 50 25 3 1012 86 MHz dB 12 200 V/mV 12 to 15 13.5 V 30 MIN TLO81BC TL082BC TL084BC TYP 2 MAX 3 5 18 5 100 10 200 20 MIN TL081I TL082I TL084I TYP 3 MAX 6 9 mV UNIT
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Template Release Date: 71194
VO = 0
V/C pA nA pA nA V
IIO IIB
VO = 0 VO = 0
VICR
VOM
Maximum M i peak k out ut voltage swing output Large-signal differential voltage amplification Unity-gain bandwidth Input resistance Common-mode rejection ratio Supply voltage rejection ratio ( VCC / VIO) Supply current (per amplifier)
AVD B1 ri CMRR
kSVR
25C 25C
70
86
80
86
80
86
80
86
dB
ICC
1.4
2.8
1.4
2.8
1.4
2.8
1.4
2.8
mA
VO1/ VO2 Crosstalk attenuation AVD = 100 25C 120 120 120 120 dB All characteristics are measured under open-loop conditions with zero common-mode voltage unless otherwise specified. Full range for TA is 0C to 70C for TL08_C, TL08_AC, TL08_BC and 40C to 85C for TL08_I. Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive as shown in Figure 17. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
electrical characteristics, VCC = 15 V (unless otherwise noted)

PARAMETER VIO VIO Input offset voltage Temperature coefficient of input offset voltage Input offset current Input bias current Common-mode input voltage range RL = 10 k RL 10 k RL 2 k VO = 10 V, VO = 10 V, RL 2 k RL 2 k TEST CONDITIONS VO = 0 0, RS = 50 RS = 50 TL081M, TL082M TA 25C Full range Full range 25C 125C 25C 125C 25C 25C Full range 25C Full range 25C 25C VIC = VICRmin, VO = 0, RS = 50 VCC = 15 V to 9 V, VO = 0, RS = 50 VO = 0, No load 25C 25C 25C 80 11 12 12 10 25 15 3 1012 86 80 12 200 12 to 15 13.5 30 18 5 100 20 200 50 11 12 12 10 25 15 3 1012 86 MHz dB 12 200 V/mV 12 to 15 13.5 V 30 MIN TYP 3 MAX 6 9 18 5 100 20 200 50 TL084Q, TL084M MIN TYP 3 MAX 9 15 UNIT mV
VO = 0
V/C pA nA pA nA V
IIO IIB
VO = 0 VO = 0
VICR
VOM
Maximum M i peak k out ut voltage swing output Large-signal differential voltage amplification Unity-gain bandwidth Input resistance Common-mode rejection ratio Supply voltage rejection ratio (VCC /VIO) Supply current (per amplifier)
AVD B1 ri CMRR
kSVR ICC
80
86
80
86
dB
1.4
2.8
1.4
2.8
mA
VO1/ VO2 Crosstalk attenuation AVD = 100 25C 120 120 dB All characteristics are measured under open-loop conditions with zero common-mode input voltage unless otherwise specified. Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive as shown in Figure 17. Pulse techniques must be used that maintain the junction temperatures as close to the ambient temperature as is possible.
operating characteristics, VCC = 15 V, TA = 25C (unless otherwise noted)

PARAMETER VI = 10 V, SR tr Slew rate at unity gain Rise time Overshoot factor Vn In THD Equivalent input in ut noise voltage Equivalent input noise current Total harmonic distortion VI = 10 V, TA = 55C to 125C, mV VI = 20 mV, RS = 20 RS = 20 , VIrms = 6 V, f = 1 kHz TEST CONDITIONS RL = 2 k, RL = 2 k, See Figure 1 RL = 2 k, f = 1 kHz f = 10 Hz to 10 kHz f = 1 kHz AVD = 1, RS 1 k, RL 2 k, CL = 100 pF, CL = 100 pF, See Figure 1 MIN 8 5 See Figure 1 0.05 20% 18 4 0.01 0.003% nV/Hz V pA/Hz TYP 13 V/s s MAX UNIT
pF CL = 100 pF,
On products compliant to MIL-PRF-38535, this parameter is not production tested.
DALLAS, TEXAS 75265
electrical characteristics, VCC = 15 V, TA = 25C (unless otherwise noted)

PARAMETER VIO VIO IIO IIB VICR VOM AVD B1 ri CMRR kSVR Input offset voltage Temperature coefficient of input offset voltage Input offset current Input bias current Common-mode input voltage range Maximum peak output voltage swing Large-signal differential voltage amplification Unity-gain bandwidth Input resistance Common mode rejection ratio Common-mode Supply voltage rejection ratio (VCC /VIO) VIC = VICRmin, , RS = 50 VO = 0, , 70 70 70 70 RL = 10 k, VO = 10 V, RL 2 k TEST CONDITIONS VO = 0, VO = 0, VO = 0, VO = 0, 11 12 25 RS = 50 RS = 50 TL082Y, TL084Y MIN TYP 3 18 5 30 12 to 15 13.5 200 3 1012 86 86 86 86 200 400 MAX 15 UNIT mV V/C pA pA V V V/mV MHz dB dB
VCC = 15 V to 9 V, , VO = 0, RS = 50
ICC Supply current (per amplifier) VO = 0, No load 1.4 2.8 mA VO1/ VO2 Crosstalk attenuation AVD = 100 120 dB All characteristics are measured under open-loop conditions with zero common-mode voltage unless otherwise specified. Input bias currents of a FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive as shown in Figure 17. Pulse techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
operating characteristics, VCC = 15 V, TA = 25C

PARAMETER SR tr Slew rate at unity gain Rise time Overshoot factor Vn In THD Equivalent input noise voltage Equivalent input noise current Total harmonic distortion VI = 10 V, VI = 20 mV, mV RS = 20 RS = 20 , VIrms = 6 V, f = 1 kHz TEST CONDITIONS RL = 2 k, RL = 2 k, f = 1 kHz f = 10 Hz to 10 kHz f = 1 kHz AVD = 1, RS 1 k, RL 2 k, CL = 100 pF, CL = 100 pF, pF See Figure 1 See Figure 1 MIN 8 TYP 13 0.05 20% 18 4 0.01 0.003% nV/Hz V pA/Hz MAX UNIT V/ s s
10
DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
10 k 1 k VI CL = 100 pF RL = 2 k OUT + RL CL = 100 pF
OUT + VI
Figure 1
100 k
Figure 2
TL081 OUT
C2 C1 500 pF
IN
IN +
IN
N1 OUT
Figure 3
Figure 4
DALLAS, TEXAS 75265
+ N1 100 k VCC
N2
1.5 k
11
TYPICAL CHARACTERISTICS Table of Graphs

FIGURE vs Frequency vs Free-air temperature vs Load resistance vs Supply voltage vs Free-air temperature vs Frequency vs Frequency with feed-forward compensation vs Free-air temperature vs Free-air temperature vs Supply voltage vs Free-air temperature vs Time vs Elapsed time vs Free-air temperature vs Frequency vs Frequency 5, 6, 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
VOM
Maximum peak output voltage
AVD PD ICC IIB VO CMRR Vn THD
Large signal differential voltage amplification Large-signal Differential voltage amplification Total power dissipation Supply current Input bias current Large-signal pulse response Output voltage Common-mode rejection ratio Equivalent input noise voltage Total harmonic distortion
MAXIMUM PEAK OUTPUT VOLTAGE vs FREQUENCY

15 VOM Maximum Peak Output Voltage V VCC = 15 V 12.5 VOM Maximum Peak Output Voltage V RL = 10 k TA = 25C See Figure 2 15

RL = 2 k TA = 25C See Figure 2
12.5 10
VCC = 15 V
10
VCC = 10 V
VCC = 10 V 7.5 5 VCC = 5 V 2.5
7.5
VCC = 5 V
2.5
0 100 1k 10 k 100 k 1M 10 M f Frequency Hz
0 100 1k 10 k 100 k 1M f Frequency Hz
10 M
Figure 5
Figure 6
12
DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
15 VOM Maximum Peak Output Voltage V TA = 25C VOM Maximum Peak Output Voltage V VCC = 15 V RL = 2 k See Figure 2 15
MAXIMUM PEAK OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE
12.5
12.5
10 TA = 55C 7.5 TA = 125C
10

RL = 10 k RL = 2 k
7.5
2.5
2.5
VCC = 15 V See Figure 2 25 0 25 50 75 100 125
0 10 k
40 k 100 k
400 k
1M
4M
10 M
0 75 50
f Frequency Hz
TA Free-Air Temperature C
Figure 7
MAXIMUM PEAK OUTPUT VOLTAGE vs LOAD RESISTANCE
15 VOM Maximum Peak Output Voltage V VOM Maximum Peak Output Voltage V VCC = 15 V TA = 25C See Figure 2 15 RL = 10 k TA = 25C
Figure 8
MAXIMUM PEAK OUTPUT VOLTAGE vs SUPPLY VOLTAGE
12.5
12.5
10
10
7.5
7.5
2.5
2.5
0 0.1
0 0.2 0.4 0.7 1 2 4 7 10 0 2 4 6 8 10 12 14 16 RL Load Resistance k | VCC | Supply Voltage V
Figure 9
Figure 10
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
DALLAS, TEXAS 75265
13
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREE-AIR TEMPERATURE
1000 700 400 AVD Large-Signal Differential Voltage Amplification V/mV 200 100 70 40 20 10 7 4 2 1 75 VCC = 15 V VO = 10 V RL = 2 k 50 25 0 25 50 75 100 125
Figure 11
LARGE-SIGNAL DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREQUENCY
106 VCC = 5 V to 15 V RL = 10 k TA = 25C
105 AVD Large-Signal Differential Voltage Amplification V/mV
104
103
45
102 Phase Shift (right scale)
90
101
135 180 10 M
1 1 10 100 1k 10 k 100 k 1M f Frequency Hz
Figure 12
14
DALLAS, TEXAS 75265
Phase Shift
Differential Voltage Amplification (left scale)
DIFFERENTIAL VOLTAGE AMPLIFICATION vs FREQUENCY WITH FEED-FORWARD COMPENSATION
106 AVD Differential Voltage Amplification V/mV VCC = 15 V C2 = 3 pF TA = 25C See Figure 3 250 225 PD Total Power Dissipation mW 200 175 150 125 100 75 50 25 0 75 50 25 0 25 50 75 100 125 TL081 TL082, TL083 TL084, TL085 VCC = 15 V No Signal No Load
TOTAL POWER DISSIPATION vs FREE-AIR TEMPERATURE
105
104
103
102
10
1 100
1k
10 k
100 k
1M
10 M
f Frequency With Feed-Forward Compensation Hz
Figure 13
SUPPLY CURRENT PER AMPLIFIER vs FREE-AIR TEMPERATURE
2.0 1.8 I CC Supply Current mA 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 75 VCC = 15 V No Signal No Load I CC Supply Current mA 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 50 25 0 25 50 75 100 125 0 0 2 4 TA = 25C No Signal No Load
Figure 14
SUPPLY CURRENT vs SUPPLY VOLTAGE
10
12
14
16
| VCC | Supply Voltage V
Figure 15
Figure 16
DALLAS, TEXAS 75265
15
INPUT BIAS CURRENT vs FREE-AIR TEMPERATURE
100 V CC = 15 V Input and Output Voltages V 4 Output 2 6
VOLTAGE-FOLLOWER LARGE-SIGNAL PULSE RESPONSE

VCC = 15 V RL = 2 k CL = 100 pF TA = 25C
I IB Input Bias Current nA
10
2 Input 4
0.1
0.01 50
6 25 0 25 50 75 100 125 0 0.5 1 1.5 2 2.5 3 3.5 TA Free-Air Temperature C t Time s
Figure 17
OUTPUT VOLTAGE vs ELAPSED TIME
28 24 VO Output Voltage mV 20 16 12 8 4 0 4 0 0.2 0.4 0.6 0.8 1.0 1.2 t Elapsed Time s VCC = 15 V RL = 2 k CL = 100 pF TA = 25C See Figure 1 CMRR Common-Mode Rejection Ratio dB 89
Figure 18
COMMON-MODE REJECTION RATIO vs FREE-AIR TEMPERATURE
VCC = 15 V RL = 10 k
88
87
86
85
84
83 75
50
25
25
50
75
100
125
Figure 19
Figure 20
16
DALLAS, TEXAS 75265
EQUIVALENT INPUT NOISE VOLTAGE vs FREQUENCY
50 Vn Equilvalent Input Noise Voltage nV/ Hz VCC = 15 V AVD = 10 RS = 20 TA = 25C 1 0.4 THD Total Harmonic Distortion % VCC = 15 V AVD = 1 VI(RMS) = 6 V TA = 25C
TOTAL HARMONIC DISTORTION vs FREQUENCY
40
0.1 0.04
30
20
0.01 0.004
10
0 10 40 100 400 1 k 4 k 10 k 40 k 100 k f Frequency Hz
0.001
10
400
1k
4k
10 k
40 k
100 k
f Frequency Hz
Figure 21
Figure 22
APPLICATION INFORMATION
RF = 100 k VCC + 15 V TL081 + CF = 3.3 F 1 k 15 V 3.3 k f= 1 2 RF CF 9.1 k R3 C1 C2 3.3 k Output Input R1 C3 R2 TL081 + VCC R1 = R2 = 2(R3) = 1.5 M C1 = C2 = C3 = 110 pF 2 1 = 1 kHz fo = 2 R1 C1 Output
Figure 23
Figure 24
DALLAS, TEXAS 75265
17
1 M VCC + 1 F Input 100 k + VCC + TL084 + VCC + TL084 VCC + VCC + TL084 + Output C + Output B 1N4148 18 k (see Note A) 15 V 18 pF VCC + 1/2 TL082 88.4 k 18 pF + VCC 88.4 k VCC+ 1/2 TL082 + VCC 1 k 15 V 88.4 k 1N4148 18 k (see Note A) 6 cos t 1 k Output A
TL084 100 k 100 k
100 F
100 k
Figure 25. Audio-Distribution Amplifier

6 sin t 18 pF
NOTE A: These resistor values may be adjusted for a symmetrical output.
Figure 26. 100-KHz Quadrature Oscillator
18
DALLAS, TEXAS 75265
16 k 220 pF 43 k 43 k Input VCC +
1/4 TL084
16 k 220 pF 30 k 43 k VCC + VCC +

1/4 TL084
30 k
220 pF
VCC + 43 k 43 k
1/4 TL084
220 pF
1.5 k
VCC
1.5 k VCC
VCC
Output A Output A Output B
2 kHz/div Second-Order Bandpass Filter fo = 100 kHz, Q = 30, GAIN = 4
2 kHz/div Cascaded Bandpass Filter fo = 100 kHz, Q = 69, GAIN = 16
Figure 27. Positive-Feedback Bandpass Filter
DALLAS, TEXAS 75265
43 k
1/4 TL084
Output B
VCC
19
MECHANICAL DATA
D (R-PDSO-G**)
14 PIN SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) 0.010 (0,25) M
Gage Plane
0.010 (0,25) 1 A 7 0 8 0.044 (1,12) 0.016 (0,40)
Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.004 (0,10)
PINS ** DIM A MAX
8 0.197 (5,00) 0.189 (4,80)
14 0.344 (8,75) 0.337 (8,55)
16 0.394 (10,00) 0.386 (9,80) 4040047 / D 10/96
A MIN
NOTES: A. B. C. D.
All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012
20
DALLAS, TEXAS 75265
MECHANICAL DATA
FK (S-CQCC-N**)
28 TERMINAL SHOWN
LEADLESS CERAMIC CHIP CARRIER
18
17
16
15
14
13
12
NO. OF TERMINALS ** 11 10 28 9 8 7 6 68 5 84 44 52 20
A MIN 0.342 (8,69) 0.442 (11,23) 0.640 (16,26) 0.739 (18,78) 0.938 (23,83) 1.141 (28,99) MAX 0.358 (9,09) 0.458 (11,63) 0.660 (16,76) 0.761 (19,32) 0.962 (24,43) 1.165 (29,59) MIN 0.307 (7,80) 0.406 (10,31) 0.495 (12,58) 0.495 (12,58) 0.850 (21,6) 1.047 (26,6)
B MAX 0.358 (9,09) 0.458 (11,63) 0.560 (14,22) 0.560 (14,22) 0.858 (21,8) 1.063 (27,0)
19 20 21 B SQ 22 A SQ 23 24 25
26
27
28
4 0.080 (2,03) 0.064 (1,63) 0.020 (0,51) 0.010 (0,25)
0.020 (0,51) 0.010 (0,25)
0.055 (1,40) 0.045 (1,14)
0.045 (1,14) 0.035 (0,89)
0.028 (0,71) 0.022 (0,54) 0.050 (1,27)
0.045 (1,14) 0.035 (0,89)
4040140 / D 10/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a metal lid. The terminals are gold plated. Falls within JEDEC MS-004
DALLAS, TEXAS 75265
21
MECHANICAL DATA
J (R-GDIP-T**)
14 PIN SHOWN
CERAMIC DUAL-IN-LINE PACKAGE
PINS ** DIM A MAX B 14 8 A MIN
14 0.310 (7,87) 0.290 (7,37) 0.785 (19,94) 0.755 (19,18) 0.300 (7,62) 0.245 (6,22)
16 0.310 (7,87) 0.290 (7,37) 0.785 (19,94) 0.755 (19,18) 0.300 (7,62) 0.245 (6,22)
18 0.310 (7,87) 0.290 (7,37) 0.910 (23,10)
20 0.310 (7,87) 0.290 (7,37) 0.975 (24,77) 0.930 (23,62)
B MAX C B MIN
1 0.065 (1,65) 0.045 (1,14)
C MAX
0.300 (7,62) 0.245 (6,22)
0.300 (7,62) 0.245 (6,22)
C MIN
0.100 (2,54) 0.070 (1,78)
0.020 (0,51) MIN
0.200 (5,08) MAX Seating Plane 0.130 (3,30) MIN
0.100 (2,54) 0.023 (0,58) 0.015 (0,38) 0.014 (0,36) 0.008 (0,20)
015
4040083/D 08/98 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. Falls within MIL STD 1835 GDIP1-T14, GDIP1-T16, GDIP1-T18, GDIP1-T20, and GDIP1-T22.
22
DALLAS, TEXAS 75265
MECHANICAL DATA
JG (R-GDIP-T8)
0.400 (10,20) 0.355 (9,00) 8 5
CERAMIC DUAL-IN-LINE PACKAGE
0.280 (7,11) 0.245 (6,22)
4 0.065 (1,65) 0.045 (1,14)
0.020 (0,51) MIN
0.310 (7,87) 0.290 (7,37)
0.063 (1,60) 0.015 (0,38) 0.100 (2,54)
0.023 (0,58) 0.015 (0,38) 0.014 (0,36) 0.008 (0,20)
015
4040107/C 08/96 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only. Falls within MIL-STD-1835 GDIP1-T8
DALLAS, TEXAS 75265
23
MECHANICAL DATA
N (R-PDIP-T**)
16 PIN SHOWN PINS ** DIM A 16 9 A MAX
PLASTIC DUAL-IN-LINE PACKAGE
14 0.775 (19,69) 0.745 (18,92)
16 0.775 (19,69) 0.745 (18,92)
18 0.920 (23.37) 0.850 (21.59)
20 0.975 (24,77) 0.940 (23,88)
A MIN
0.260 (6,60) 0.240 (6,10)
8 0.070 (1,78) MAX
0.035 (0,89) MAX
0.020 (0,51) MIN
0.310 (7,87) 0.290 (7,37)
0.100 (2,54) 0.021 (0,53) 0.015 (0,38)
0 15 0.010 (0,25) NOM
0.010 (0,25) M
14/18 PIN ONLY 4040049/C 08/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001 (20 pin package is shorter then MS-001.)
24
DALLAS, TEXAS 75265
MECHANICAL DATA
P (R-PDIP-T8)
0.400 (10,60) 0.355 (9,02) 8 5
PLASTIC DUAL-IN-LINE PACKAGE
0.260 (6,60) 0.240 (6,10)
4 0.070 (1,78) MAX 0.020 (0,51) MIN 0.310 (7,87) 0.290 (7,37)
0.100 (2,54) 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) M 0.010 (0,25) NOM
0 15
4040082 / B 03/95 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
DALLAS, TEXAS 75265
25
MECHANICAL DATA
PW (R-PDSO-G**)
14 PIN SHOWN 0,30 0,19 14 8
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,10 M
0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 A 7 0 8 0,75 0,50
Seating Plane 1,20 MAX 0,15 0,05 0,10
PINS ** DIM A MAX 8 14 16 20 24 28
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60 4040064 / E 08/96
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-153
26
DALLAS, TEXAS 75265
MECHANICAL DATA
U (S-GDFP-F10) CERAMIC DUAL FLATPACK
0.250 (6,35) 0.246 (6,10)
0.006 (0,15) 0.004 (0,10) 0.080 (2,03) 0.050 (1,27) 0.045 (1,14) 0.026 (0,66)
0.350 (8,89) 0.250 (6,35) 1
0.300 (7,62)
0.350 (8,89) 0.250 (6,35) 10 0.019 (0,48) 0.015 (0,38)
0.050 (1,27) 0.250 (6,35)
0.025 (0,64) 0.005 (0,13)
1.000 (25,40) 0.750 (19,05) 4040179 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP1-F10 and JEDEC MO-092AA
DALLAS, TEXAS 75265
27
MECHANICAL DATA
W (R-GDFP-F14) CERAMIC DUAL FLATPACK
0.260 (6,60) 0.235 (5,97)
Base and Seating Plane
0.007 (0,18) 0.004 (0,10) 0.080 (2,03) 0.045 (1,14) 0.280 (7,11) 0.255 (6,48) 1 14 0.045 (1,14) 0.026 (0,66) 0.360 (9,14) 0.240 (6,10) 0.360 (9,14) 0.240 (6,10)
0.019 (0,48) 0.015 (0,38)
0.050 (1,27)
0.390 (9,91) 0.335 (8,51)
0.025 (0,64) 0.015 (0,38)
7 1.000 (25,40) 0.735 (18,67)
4040180-2 / B 03/95 NOTES: A. B. C. D. E. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. This package can be hermetically sealed with a ceramic lid using glass frit. Index point is provided on cap for terminal identification only. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB
28
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL APPLICATIONS). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMERS RISK. In order to minimize risks associated with the customers applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TIs publication of information regarding any third partys products or services does not constitute TIs approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated

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TL081, TL081A, TL081B, TL082, TL082A, TL082B TL082Y, TL084, TL084A, TL084B, TL084Y JFET-INPUT OPERATIONAL AMPLIFIERS

SLOS081E FEBRUARY 1977 REVISED FEBRUARY 1999

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TL081M U PACKAGE (TOP VIEW)

TL082M U PACKAGE (TOP VIEW)

NC OFFSET N1 IN IN+ VCC

NC NC VCC+ OUT OFFSET N2

NC 1OUT 1IN 1IN+ VCC

NC VCC+ 2OUT 2IN 2IN+

TL081, TL081A, TL081B D, JG, P, OR PW PACKAGE (TOP VIEW)

TL082, TL082A, TL082B D, JG, P, OR PW PACKAGE (TOP VIEW)

NC VCC + OUT OFFSET N2

1OUT 1IN 1IN + VCC

VCC + 2OUT 2IN 2IN +

TL081M . . . FK PACKAGE (TOP VIEW)

TL082M . . . FK PACKAGE (TOP VIEW)

NC 1OUT NC VCC+ NC NC 2OUT NC 2IN NC

TL084, TL084A, TL084B D, J, N, PW, OR W PACKAGE (TOP VIEW)

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

2IN 2OUT NC 3OUT 3IN

1OUT 1IN 1IN + VCC + 2IN + 2IN 2OUT

4OUT 4IN 4IN + VCC 3IN + 3IN 3OUT

1IN + NC VCC + NC 2IN +

1IN 1OUT NC 4OUT 4IN 4IN + NC VCC NC 3IN +

SMALL OUTLINE (D014)

CHIP CARRIER (FK)

CERAMIC DIP (J)

CERAMIC DIP (JG)

PLASTIC DIP (N)

TSSOP (PW) TL081CPW

FLAT PACK (U)

FLAT PACK (W)

CHIP FORM (Y)

TL084CD TL084ACD TL084BCD

TL084CN TL084ACN TL084BCN

TL084ID TL084QD TL081MFK TL082MFK TL084MFK

SLOS081E FEBRUARY 1977 REVISED FEBRUARY 1999

schematic (each amplifier)

1080 VCC OFFSET N1

TL081 Only Component values shown are nominal.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TL082Y chip information

(5) 1IN + 1IN 2OUT (7) (3) (2) +

VCC+ (8) (1) 1OUT + (5) (6) 2IN + 2IN

PIN (4) IS INTERNALLY CONNECTED TO BACKSIDE OF CHIP.

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

TL084Y chip information

1IN + 1IN 2OUT 3IN +

(7) (10) (9)

3IN 4OUT (14)

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

See Dissipation Rating Table

POST OFFICE BOX 655303

DALLAS, TEXAS 75265

electrical characteristics, VCC = 15 V (unless otherwise noted)

SLOS081E FEBRUARY 1977 REVISED FEBRUARY 1999

Template Release Date: 71194

electrical characteristics, VCC = 15 V (unless otherwise noted)

operating characteristics, VCC = 15 V, TA = 25C (unless otherwise noted)