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DTU Informatics Institute of Informatics and Mathematical Modeling Technical University of Denmark
Richard Petersens Plads Bygning 322
June 27. - 2009 1.Edition This report is written as documentation of a B.Eng. project made at Informatics and Mathematical Modeling at the Technical University of Denmark.
Abstract
Multiplication operations are frequently required in digital signal processing. To increase the speed with which these are done, parallel multipliers can be used. These however require a large area on the chip and consume much power. An important goal would therefore be to reduce the area requirements. The purpose of this project is to analyze several methods of performing truncated multiplication and to determine which method would be most efficient for unsigned numbers of 8, 16 or 32 bits.
Truncated multiplication is a technique where only the most significant columns of the multiplication matrix are used and therefore area requirements can be reduced by up to 46.08 % for 32 bit inputs. This however leads to a rounding error and a reduction error which needs to be corrected by introducing a correction constant, and the goal of this project is to determine the point of balance for error vs. hardware savings. The scope of this project is to evaluate different well-known area reduction methods along with minimizing the error.
The multiplier is implemented using VHDL (VHSIC Hardware Description Language, where VHSIC stands for Very High Speed Integrated Circuit) and simulated with ModelSim/Xilinx ISE in order to observe the hardware area reduction. It is also implemented and simulated using Matlabs Simulink tool in order to evaluate the error.
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Resum
Ved digital signal behandling stilles der ofte krav om multiplikation. For at ge hastigheden af denne proces kan parallelle multiplikatorer finde anvendelse, men dette optager stor plads p chipen og krver desuden en betydelig effekt. Det er derfor af vigtighed at reducere kravet til plads (og dermed effekt) gennem brug af forskellige metoder til udfrelse af trunkeret multiplikation og til at bestemme hvilken metode, der er den mest effektive for ikke-fortegnsbestemte tal p 8, 16 eller 32 bits.
Trunkeret multiplikation er en teknik, der kun bruger de mest betydningsfulde sjler i multipliktionsmatricen for bl.a. at spare plads. Teknikken frer imidlertid til afrundingsfejl og reduktionsfejl, som der derfor m korrigeres for gennem inddragelse af en korrektionskonstant.
Formlet med dette projekt er at bestemme balancepunktet mellem prcisionsfejl og plads p hardwaren. Projektets ml er at evaluere forskellige allerede kendte metoder, der sigter mod pladsbesparelse samtidig med en minimering af fejlforgelsen.
Multiplikatoren implementeres gennem brug af VHDL (Very High Speed Integrated Circuit Hardware Description Language), og simuleres med modelSim/Xilinx ISE med det forml at konstatere pladsbesparelsen i hardwaren. Ved at bruge Matlabs redskab Simulink implementeres og simuleres den endvidere med det forml at observere fejlforgelsen.
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Preface
This report is written as documentation of a B.Eng. project made at the Informatics and Mathematical Modeling department of the Technical University of Denmark.
The team consisted of Andreas Thor Winther. The project supervisor at DTU was Associate Professor Alberto Nannarelli. Amanuensis Edward Alexandru Todirica helped with the technical part of the VHDL implementation.
The project was about reducing area consumption on conventional parallel multipliers using truncation. The report consists of an analysis of the problem, a description of a possible solution, and a presentation of how it might be designed and implemented.
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Acknowledgements
The project was proposed by Associate Professor Alberto Nannarelli of IMM1 who also made sure I got a desk, along with the needed hardware and software, to carry out the task. I would like to thank Alberto for giving me the opportunity to work on this project and for being available during the project period.
I would also like to thank Amanuensis Edward Alexandru Todirica for helping me with various problems concerning both VHDL problems and the writing of the report.
Furtermore I would like to thank Emil N. Jakobsen, Markku Eerola, Bjarne Petersen and Troels Winther for reading through the report and for coming with constructive criticism.
Andreas T. Winther June 2009 Testing and analyzing of several methods for truncated multiplication in binary
Table of Contents
i ii iii iv 1 Abstract ........................................................................................................................ Resum......................................................................................................................... Preface.......................................................................................................................... Acknowledgements...................................................................................................... Introduction................................................................................................................. 1 1.1 The problem ........................................................................................................ 1 Problem description .................................................................................... 1 Motivation................................................................................................... 2
The project .......................................................................................................... 2 Structure of the report ................................................................................. 2 List of terminologies ................................................................................... 3 Tools used ................................................................................................... 5 Matlab r2008b Simulink ...................................................................... 5 ModelSim 6.3a........................................................................................ 5 Xilinx ISE 9.2i ........................................................................................ 5 Hardware used ............................................................................................ 6 Method ........................................................................................................ 6
Theoretical background .............................................................................................. 8 2.1 Binary multiplication .......................................................................................... 8 Rounding..................................................................................................... 9 Truncation ................................................................................................. 10
Conventional multipliers................................................................................... 11 Binary addition.................................................................................................. 11 Carry-save adder (CSA) multiplier................................................................... 15 Multiplier trees.......................................................................................... 16
2.4.1 3
4.2 5
Implementation ......................................................................................................... 23 5.1 5.2 Matlab Simulink............................................................................................. 24 VHDL ............................................................................................................... 26 Components.vhd ....................................................................................... 27 Fadd 1-bit Full adder.......................................................................... 27 CLA_g n-bit Carry look-ahead adder ................................................ 28 CSA_g Carry-save adder ................................................................... 29 Nxn_mult.vhd ........................................................................................... 30 Testbench.vhd ........................................................................................... 30
Testing............................................................................................................... 31 Matlab Simulink test .............................................................................. 31 Modelsim Xilinx ISE simulation ........................................................... 31 Testing on an FPGA.................................................................................. 32
Discussion ................................................................................................................. 37 7.1 Results evaluation ............................................................................................. 37 Precision Error .......................................................................................... 37 Hardware savings...................................................................................... 39
10 Appendix A Matlab Simulink Design.................................................................... 46 10.1 10.2 The inside of the Simulink sub-systems ........................................................... 46 Matlab embedded function full source code..................................................... 47
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11.2 11.3
12 Appendix C Test results......................................................................................... 59 12.1 12.2 Simulink test bench........................................................................................... 59 Simulation diagrams from modelSim ............................................................... 61
13 Appendix D Synthesis reports ............................................................................... 67 13.1 13.2 13.3 13.4 13.5 CLA_g (Carry Look-ahead) VS add_g (Ripple-carry) ..................................... 67 32-bit input (left = 31)....................................................................................... 67 16-bit input (left = 15)....................................................................................... 70 8-bit input (left = 7)........................................................................................... 73 Example of a full syntesis report ...................................................................... 75
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Table 1: Precision error for various truncated multipliers ................................................ 35 Table 2: Hardware savings for various truncated multipliers ........................................... 36
Andreas T. Winther June 2009 Testing and analyzing of several methods for truncated multiplication in binary
Table 3: Maximum precision error for various multipliers .............................................. 38 Table 4: Hardware savings compared with [17] ............................................................... 39
Andreas T. Winther June 2009 Testing and analyzing of several methods for truncated multiplication in binary
1 Introduction
This chapter gives an introduction to the problem, the tools used, the methods, and the structure of the report and the chapter consists of 2 sub-chapters:
2. The project Tools and hardware, methods and the structure of the report.
1. To determine the error for several methods and degrees of truncation for 8, 16 and 32 bits. This is done in chapter 6
2. To design and implement the parallel multiplier in order to observe the reduction in area and to confirm if the method works. This is done in chapter 5 and 6
3. To compare the results and determine which area/error balance would be most efficient for 8, 16 and 32 bits.
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1.1.2 Motivation
Truncation is a method used to reduce hardware requirements of multipliers, while remaining very simple in terms of implementation and options to correct for potential adverse effects. This implies that the results of the project could potentially lead to major improvements in the design and manufacture of multiplier circuitry. It has been possible to simulate the effects of truncation, given a wide variety of conditions, without imposing demands that are impossible to meet using readily available technology. The balance of challenge and tractability of the stated problem has been a determining factor in the decision to undertake the project, along with a sense of personal interest and enthusiasm. Examples of use: [1], [2], [3], [4] , [5].
Chapter 1 is an introduction to the problem at hand and the tools and methods used. Chapter 2 gives the theoretical background. Chapter 3 provides a closer analysis of the problem Chapter 4 gives a top-view design of the two model implementations Chapter 5 explains in closer detail the implementation of the two models. Chapter 6 provides the results of the work. Chapter 7 discusses the work Chapter 8 concludes the report Chapter 9 has a list of used references. Appendix A unrolls the Simulink model including the full Matlab function source code.
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Appendix B gives the full source code for the VHDL implementation. Appendix C provides test results. Appendix D holds the various synthesis reports used in this report.
ASIC:
(Application-Specific Integrated Circuit), is a chip designed for a particular application and is pre-programmed
FPGA:
(Field Programmable Gate Array) can be reprogrammed and therefore makes it an excellent choice when testing models
HDL:
(Hardware Description Language) General term for a language used to describe hardware.
LED:
(Light-Emitting Diode): a semiconductor that gives out light when an electric current is applied to it.
LUT:
(Look-Up Table): A data structure, usually an array or associative array, often used to replace a runtime computation with a simpler array indexing operation.
MSB:
10011000.
RTL: (Register Transfer Level) A way of describing the operation of a synchronous digital circuit. In RTL design, a circuit's behavior is defined in terms of the flow of signals (or transfer of data) between hardware registers, and the logical operations performed on those signals.
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Synthesize:
See XST.
SystemC:
Verilog:
VHDL:
(Very High Speed Integrated Circuit Hardware Description Language) is the VHSIC Hardware Description Language. VHSIC is an abbreviation for Very High Speed Integrated Circuit.
XST:
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2 3
See more about Matlab and Simulink at: http://www.mathworks.com/products/ (14-06/2009) See more about ModelSim at: http://www.model.com/ (14-06/2009) 4 See more about Xilinx at: http://www.xilinx.com/tools/designtools.htm (14-06/2009)
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1.2.5 Method
Following is a short explanation of how the before mentioned tools were used in this project.
Matlab was used to simulate the error using Simulink. Two uniformly random numbers were generated. These numbers were then multiplied using both the built-in (no truncation, no error) multiplier block and a custom-made Embedded Matlab Function block with implemented truncation. The truncated product was rounded down to match the input size of the multiplier and the multiplicand and a correction constant was added to reduce the error. Lastly the truncated product was subtracted from the real product to see the deviation (the error resulting from the truncation). Finally the average deviation from a 1,000,000 samples were calculated and noted.
ModelSim was used to compile the VHDL code and to simulate it. 3 VHDL files were written: nxn_mult.vhd The main file with the code needed for the multiplier. components.vhd Some components needed (full adder, n-bit adder etc). testbench.vhd Testbench used to stimulate inputs to the multiplier To see in more detail how the multiplier was implemented, see chapter 0
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Xilinx ISE was used to synthesize the VHDL code implemented in ModelSim and a synthesis report which provides detailed information about the model was generated.
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2 Theoretical background
If the multiplier bit is 0, the partial product is also 0 If the multiplier bit is 1, the partial product is equal to the multiplicand Repeat for every multiplier bit
Notice that this gives a number of partial products equal to the width of the multiplier. To obtain the final product the elements in the columns (from right to left) are added using binary logic7. Any carries are carried on to the next column. The result of this operation is stored in one bit of the product and the operation is repeated for each remaining column.
5 6
Equivalent to multiplying by hand. By ANDing, means sending the two bits through a 2-bit and gate. 7 For more information about binary adding, see [8].
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Figure 1: 4x4 bit Binary Multiplication. Notice: A nxn-bit multiplier renders a 2n-bit product. Source: http://edu.cs.tut.fi/PD2009/figs/EPs_arith/multiply.jpg -11/06/09
2.1.1 Rounding
Conventionally an n-bit multiplicand and an n-bit multiplier would render a 2n-bit product. Sometimes an n-bit output is desired to reduce the number of stored bits. This is done in two steps. When rounding to n-bits a 1 is added to the n-1th bit and a potential carry is propagated to the nth-bit and so on. The unwanted bits (the n-1th least significant bits) are discarded.
In Figure 1 rounding down to 4 bits corresponds to adding a 1 to p3 and then discarding the 4 least significant bits. Rounding in decimal numbers is done in a similar way, that is if you add a 5 instead of a 1 to the n-1th bit.
This will not work if the product corresponds to a number unless the bits discarded are fractional bits. To give an example in decimal numbers:
213,456 rounded to 3 decimals would be 213 which is correct, while 213456 rounded to 213 would result in a very different number.
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2.1.2 Truncation
Truncation is a method where the least significant columns in the partial product matrix are not formed. The amount of columns not formed in this way, T, defines the degree of truncation and the T least significant bits of the product always result in 0. The algorithm behind truncated multiplication is the same as when dealing with nontruncated multiplication regardless of the truncation degree. The effect is illustrated in Figure 2, where a truncation degree of T = 3, is applied. Notice that the columns to the right of the maroon vertical line are missing.
A loss of precision follows as a result of truncation since the least significant bits of the resulting product are always 0. Notices that the truncated product is always equal to or lower than the real product since 1s are converted to 0s and never the other way around. This error, however, can be compensated for by introducing a correction constant and thus leading to a truncation error that is acceptable in most cases when dealing with digital signal processing. In this report the correction constant is found by simulating the multiplier (without correction) and the average precision error over 1,000,000 million samples is then used in a second simulation run as the correction constant. A more detailed introduction to this will be given in the design chapter.
Figure 3: Left: A sequential multiplier, right: A parallel multiplier Sources: http://www.cise.ufl.edu/~mssz/CompOrg/Figure3.16-ALUmult2ckt.gif (21/06-2009) http://www.cs.umbc.edu/~squire/download/pmul4.jpg (21/06-2009)
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A full adder is one of the simplest components used to perform binary addition as it deals with only 1-bit signals. It takes two inputs A, B and a carry in, Cin which results in a sum, S and a carry out, Cout. The carry in is only used when a third input comes from somewhere, for example from another full adder.
Adding n-bit numbers together can be done in various ways [9]. The simplest n-bit adder is called a Ripple-carry adder and a 4-bit example is shown in Figure 5. It is simply an array of full-adders where the carry-out from the right-most adder, C1 propagates into the carry-in of the second adder and so on. This is called a ripple-carry adder because the carry ripples from full adder to full adder as shown in the diagram.
Figure 5: 4-bit Ripple-Carry Adder The carry ripples from right to left. [10]
This adder is quite slow as every full adder has to wait for the carry-out of the previous adder and only one adder is in use at any given time. To reduce delay various techniques
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have been used and in this project two are especially prominent, the Carry-save adder and the Carry look-ahead adder.
A Carry look-ahead adder calculates the sum without regard for potential carries from previous adders. The Carry Look-ahead block shown on the diagram calculates all the carries in the system. In the end the sums and the carries are added and the final sum is given including the last carry from the most significant bit. The advantage of this is that the delay time is radically decreased, as the full adders dont have to wait for a ripple-carry from a previous state. The catch is of course that more components are needed to implement the Carry look-ahead block and thus takes up more area on the chip. Since this project is about reducing hardware needed this adder might not seem as a logical choice. However, as will be mentioned later (and in Appendix D Synthesis reports) the area used is actually the same as for a ripple-carry adder after the area optimization algorithm is performed by Xilinx ISE. More about the Carry look-ahead adder can be found in Appendix B.6 in [8] and [11].
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Lastly, the Carry-save adder (CSA) is shown in Figure 7. Looking at the 1-bit case it can be seen that the CSA block is basically a full adder and has the same number of inputs and outputs (IO), they are just renamed. Here x and y are used instead of a and b to avoid confusion.
Figure 7: the Full adder and the CSA has same IO. [8]
When implementing multipliers it is needed to add three n-bit numbers and this requires one CSA block for every bit as shown in Figure 8.
Figure 8: CSA array For every bit one CSA block is needed. This circuit adds three n = 8 bit numbers. [8].
The important thing to notice here is the fact that the CSA blocks all operate simultaneously and they dont wait for a carry from a previous state. The three input n-bit numbers are compressed into two n-bit numbers, a sum and a carry.
Finally the sum and carry are added, typically using a fast adder like the before mentioned Carry look-ahead adder.
For more information about Carry-save addition, see [8]. [8], [10]
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Figure 9: Schematic of the CSA. a, sumin, cin, sumout, cout are all n-bit wide, while b(i) is only one bit wide.
Every CSA-array has three input numbers as illustrated in Figure 9. The outputs of the first CSA are used as inputs in the second CSA along with a and so on. Since the first CSA array has no previous CSA-arrays it has two 0s and of course a as input. This
8
If b(i) is 0 the signal a is gated and treated as zero in the box, otherwise a is passed through unaltered.
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means that the first CSA-array can actually be replaced by very simple logic but more about that in 4.2.
As shown in Figure 10 it is possible to combine the CSA-array with a Carry lookahead adder. Each CSA-array outputs one bit giving the least significant half of the final product, while the final Carry look-ahead adder outputs the most significant half of the final product.
Figure 11: Example of a carry-save adder Wallace tree multiplier. This type of multiplier will not be used as it is efficient for reducing delay (speed) and that is not within the scope of this project. Source: http://net.pku.edu.cn/~course/cs101/resource/Intro2Algorithm/book6/676_a.gif -11/06/09
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3 Analysis
In this chapter a closer analysis of the problem is done. As mentioned earlier the main problem in this project is to reduce area used on the FPGA. This chapter will consist of two sub-chapters:
Identification of the priorities of the report. A possible solution to the problem. Which choices have to be made and why?
3.1 Priorities
Many things can be optimized by using different methods aiming at solving different problems. However, the primary purpose of this project is to reduce the area used on the FPGA. Speed is also a concern but only a secondary priority as described in 3.2.
A Carry look-ahead adder was used as the final adder instead of a Ripple-carry adder as it was faster without compromising area requirements.
Carry-save adders were used to represent the partial product matrix as they are fast and area efficient when adding m different n-bit numbers.
In Chapter 2 a multiplier consisting of several Carry-save adders and a final Carry lookahead adder was introduced. A third adder, the Ripple-carry adder, was introduced but also rejected shortly after as it was too slow. The problem to be addressed now is if there
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are other adders than the three above mentioned and the answer is yes. There are an almost endless amount of different adders invented, some of which are quite obscure (a few examples: [9]). They all have their perks and drawbacks but we will not go more into details about adders. The Carry look-ahead adder and the Carry-save adder were chosen as they are both very readily implemented, while still providing superior performance. These adders are also very commonly used in parallel multipliers and are as such obvious choices.
As stated in 2.1.2 a precision error occurs when truncation is applied and this error can be averted by introducing some sort of correction. Here one type of correction, correction using a constant, was introduced. There are however several ways of applying correction some of which are quite intricate (as with adders) [12], [13], [14], [15]. The method of constant correction was chosen as it is an easily implemented correction and compared to this, the error precision achieved is quite noteworthy
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4 Design
In this chapter both the Simulink model and the ModelSim VHDL model will be presented at a high-level to give a general idea of how to apply the solution presented in the analysis chapter (chapter 3.2).
The Multiplier with Truncation block is a Matlab Embedded Function and the block is implemented using the Matlab Programming language. More details about this implementation are given in chapter 5.1.
The rounding is implemented in two steps. First a 1 is added to the appropriate bit (see 2.1.1). Second, shifting is applied n times as shown in Figure 12. In this way the truncated bits arent removed but simply changed to zero. If the bits were completely removed then conversion to base 10 (decimal) would be incorrect.
Figure 12: Bit shifting When shifting right twice then left twice the 2 least significant bits become 0
The simulation is run twice with each set-up. First, the simulation is run without any correction applied and the average difference is noted. Second, the average difference from first run is used as correction and the simulation is run again.
Finally the average difference, both with and without applied correction, is noted in a table. See chapter 6.1.1 for the table.
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Figure 13: The designed Simulink model. The inside of the boxes can be seen in Appendix A Matlab Simulink Design.
Figure 14: High-level design of the nxn bit parallel CSA multiplier implemented. Everything right of the blue line is truncated (not formed).
In Figure 14 is used the same CSA multiplier as introduced in chapter 2.4 except for two modifications.
Recollect that the first CSA-array can be replaced by very simple logic. This logic is implemented in the process trunc.
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Truncation is applied. Remember that CSA-arrays are simply arrays of CSAblocks (or full adders) and depending on the degree of truncation a number of the least significant adders are discarded. In Figure 14 this corresponds to discarding everything right of the blue line.
The level of truncation and the width of the multiplicand is given by two parameters, T and left respectively. The implementation of the multiplier will be explained in more detail in chapter 0.
The sum output after each stage is left shifted once before put into the next stage and the least significant bit of the sum (before left shifting) is used as product bit. The signal sum_1 coming from CSA_1 would give the product bit p(1) and so on. Quick example, T = 4: The 3 rightmost adders are not formed in CSA_1 (the first CSA-array). The 2 rightmost adders are not formed in CSA_2. The rightmost adder is not formed in CSA_3. The product bits p(3)-p(0) are set to 0. All other components operate as normal.
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5 Implementation
In this chapter an in-depth explanation of how the two models (Simulink and vhdl) is made. Since the Matlab Simulink model was made mostly using pre-made blocks, the only interesting part left is the embedded Matlab function and as such 5.1 will mostly be about this. The top view design has already been given in the design chapter (4.1).
The VHDL implementation, however, is much more interesting to have a closer look at. A top view design has been given in the design chapter (4.2) but in this chapter we will go into details as to how exactly the different components were implemented. This is what 0 is all about.
Finally it is explained how the above mentioned models have been tested to confirm that they are in fact correct and/or reliable.
The parameter used to define the level of truncation is different in the Simulink model and the VHDL implementation. Simulink uses the parameter k where n + k is the number of columns used from the partial product matrix while truncating. Contrarily, the VHDL implementation uses the parameter T which is defined as
Figure 15: The 2n-bit product. Two n-bit inputs render a 2n-bit final product. The T bits are truncated while the n+k bits are kept.
the number of columns not used from the partial product matrix.
In the beginning of the project k was used but this was a poor choice and instead T was used when the VHDL model was implemented as it seemed more logical.
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Now for the embedded Matlab function: It is implemented by using the Matlab Programming language and the full source code can be found in Appendix A Matlab Simulink Design as well. It has four inputs: a, b, n and k. The parameters n and k have to be set manually using the Matlab console. The correction constant C is not used in this function but is also set manually using the Matlab console.
a and b are the inputs the multiplicand and the multiplier respectively. n defines the width of a and b. k defines the degree of truncation used.
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Figure 16: Flow diagram of the Embedded Matlab function, multiplier with truncation.
It has two inputs and 1 output, all 32-bit integers. It is followed by 5 steps:
1. The 32-bit integer inputs are converted into binary vectors or arrays with n giving the width of those arrays.
2. The partial product matrix is formed as explained in 2.1. As an example a = 2710 = 110112 and b = 2610 = 110102 would render the matrix in Figure 16
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It is important to note that the algorithms and the methods used here wont be efficient at all on a real chip but they do give us the correct result. Since this is the only thing we are interested in at this point it is not a problem.
5.2 VHDL
This is a description of the VHDL code used to implement the n-bit multiplier introduced in 4.2. It uses Carry-save adders to represent the partial product matrix and it uses a Carry look-ahead adder as the final adder.
The VHDL code is in principal quite simple with only a few components; there are, however, some parts that might need a closer look. The full source code can be found in Appendix B - VHDL code.
The entire model consists of 3 vhdl files including a test bench. They are all made from scratch and their use will now be clarified.
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Figure 17: Top-View of the VHDL implementation The testbench stimulates inputs (a and b) to the multiplier and receives the resulting product (y). Inside the multiplier is one Carry look-ahead adder and n CSA-arrays, each with n full adders (CSAblocks) inside.
5.2.1 Components.vhd
This file contains all the components needed to implement the multiplier and as such does nothing by itself. It was made to keep nxn_mult.vhd simpler.
This is a common full adder as described in 2.3. It takes a, b and cin (carry in) and gives s (sum) and cout (carry out) as outputs.
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In this component left is a generic. This means that you have to specify a value for left, when this component is instantiated. Left specifies the position of the MSB (most significant bit) of a,b and sum. With left being 31; a,b and sum would be 32 bits wide.
This is a carry look-ahead adder like the one introduced in 2.3. It is used as the final adder in the multiplier since it is faster than a ripple-carry adder and uses the same area when optimized properly9.
In this case cin is 0 and cout is connected to a signal with no connection (nc1). The signals sum_n and carry_n, coming from the final CSA-array in the multiplier, are connected to a and b respectively.
The output of the adder, sum becomes the left+1 most significant bits in the final product.
Figure 18: 2n bit final product of the multiplier The light green square represents the left+1 most significant bits.
Xilinx ISE 9.2i is used to synthesize the code and the code is optimized automatically while doing so.
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The signal b is not a part of a conventional carry-save adder and is only used in one line: aa <= a when b = '1' else zero;
As mentioned earlier b is a gating parameter. If b is 0 the signal a is gated and the internal signal aa is zero, otherwise a is passed through to aa. It is aa which is used inside the component.
Concurrent statement: So called because conceptually they can be activated and perform their actions together, that is, concurrently.
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10
5.2.2 Nxn_mult.vhd
Generics: {left, T} Inputs: {a, b} Outputs: {y} a and b are left bits wide. y is 2* left+1 bits wide.
This is the main multiplier component itself. The inputs a and b are the multiplicand and the multiplier respectively and y is the product. Like in the previous components left and T are generics and here they set the width of the multiplicand and the degree of truncation respectively.
Basically, the full role of this component is declaration and instantiation of the above mentioned components. It generates the wires needed to connect the components correctly using the before mentioned generate statements. One additional thing worth mentioning is the process trunc.
As mentioned earlier the first CSA-array is replaced purely with combinatorial logic. This combinatorial logic is what trunc describes. The signal carry_0 is always zero (untouched in this process) and sum_0 <= a if b(0)= 1, else sum_0 <= zero.
5.2.3 Testbench.vhd
The test bench creates one or more instances of the multiplier. Several different architectures are used depending on specific needs. One architecture creates a multiplier with left = 31, another with left = 15 and a third creates multiple multipliers with the same left but different levels of T.
Shared by all architectures is that they stimulate these multipliers with a and b as inputs and receives the product (y). The test bench is simulated using ModelSim and the simulation results are discussed next and shown in Appendix C Test results.
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5.3 Testing
Testing is a vital part of any work. Below is explained how the testing was carried out in this project.
After designing the model and testing it, it was synthesized using Xilinx ISE. As mentioned in 3.2 I ended up using a Carry look-ahead adder instead of a ripple carry adder since the area it takes is the same. This was verified by synthesizing both a normal generic ripple carry adder and a generic carry look-ahead adder. See Appendix D Synthesis reports for further details.
11
Simulink uses seeds to generate random numbers. This means that if the seeds arent changed it will still be the same X random numbers thus making them not so random. The seeds are therefore changed everytime the correction constant was applied.
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6 Results
In this chapter the results from the two models will be presented.
As explained in the implementation chapter 5 the Simulink model and the VHDL model use two different parameters of defining the level of truncation (k and T respectively), hence both parameters are shown in both tables.
Simulink does not support integers of more than 32 bits, which could have otherwise solved the problem. Notice that a 64 bit signed integer is potentially 9,223,372,036,854,775,807, which is quite a high number.
N = 15 (two 15-bit inputs) which gives the highest possible correct result, is included in Table 1.
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E is the uncorrected error. This calculation is performed to avoid using the truncated bits (2n (n + k)) as they are always 0.
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Table 1: Precision error for various truncated multipliers Each row represents a multiplier defined by the parameters n, k and T.
n 8 8 8 8 8 8 15 15 15 15 15 15 15 15 16 16 16 16 16 16 16 32 32 32 32 32 32 32 32 32
k 1 2 3 4 5 8 1 2 3 4 5 6 7 15 1 2 3 4 5 6 16 1 2 3 4 5 6 7 8 32
T 7 6 5 4 3 0 14 13 12 11 10 9 8 0 15 14 13 12 11 10 0 31 30 29 28 27 26 25 24 0
E[not corrected] -130.253771 -49.368171 -16.653515 -4.2326551 -0.053813 1.599285 -45064.90 -20507.77 -9216.607 -4114.335 -1807.960 -795.4281 -343.2297 58.83136 -59592.17 -45049.86 -37639.47 -286374.2 -25537.30 -31825.38 -30026.22 OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW
C 130.2539 49.36816 16.65332 4.232666 0.053833 -1.599289 45064.90 20507.77 9216.607 4144.335 1807.960 795.4281 343.2297 -58.83136 59592.17 45049.86 37639.48 286374.2 25537.30 31825.38 30026.22 OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW
E[corrected] -5.965983 -6.347613 -4.954989 -0.30413 0.391538 -0.69136 -9.476291 17.29518 5.324396 43.53750 -4.668613 8.099846 43.11340 -59.64291 OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW OVERFLOW
Inputs 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 1,000,000 -
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Table 2: Hardware savings for various truncated multipliers Each row represents a multiplier defined by the parameters n, k and T.
n k 8 1 8 2 8 3 8 4 8 5 8 8 16 1 16 2 16 3 16 4 16 5 16 6 16 16 32 1 32 2 32 3 32 4 32 5 32 6 32 7 32 8 32 32
T Look Up Tables (LUTs) Slices used Hardware savings 7 77 44 34.75 % 6 88 51 25.42% 5 99 57 16.10 % 4 106 61 10.17 % 3 111 64 5.932 % 0 118 68 0.000 % 15 286 164 42.11 % 14 313 180 36.64 % 13 339 195 31.38 % 12 363 209 26.52 % 11 384 221 22.27 % 10 404 232 18.22 % 0 494 284 0.000 % 31 1086 624 46.08 % 30 1145 658 43.15 % 29 1203 692 40.27 % 28 1259 724 27.49 % 27 1312 754 24.86 % 26 1364 784 32.27 % 25 1414 813 29.79 % 24 1461 840 27.46 % 0 2014 1158 0.000 %
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7 Discussion
In this chapter, the results presented in this report are discussed and compared with similar previously published results. It will also be discussed whether the tools, methods and components used were correct. Finally the perspectives of the work and what future work could be done are discussed.
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Table 3: Maximum precision error for various multipliers For more information as to how these numbers are calculated, see [17]
n 8 8 8 8 8 8
k 1 2 3 4 5 8
T 7 6 5 4 3 0
16 1 16 2 16 3 16 4 16 5 16 6
16 16 0 24 1 24 2 24 3 24 4 24 5 24 6 24 7
24 24 0
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n 8 8 8 8 8 8 16 16 16 16 16 16
k 1 2 3 4 5 8 1 2 3 4 5 6
T 7 6 5 4 3 0 15 14 13 12 11 10 0 31 30 29 28 27 26 25 24 0
Hardware savings Hardware savings ([17]) 34.75 % 25.42% 16.10 % 10.17 % 5.932 % 0.000 % 42.11 % 36.64 % 31.38 % 26.52 % 22.27 % 18.22 % 0.000 % 46.08 % 43.15 % 40.27 % 27.49 % 24.86 % 32.27 % 29.79 % 27.46 % 0.000 % 35.4 % 23.9 % 15.2 % 9.28 % 4.36 % 0,00 % 42.6 % 40.0 % 34.2 % 29.3 % 24.2 % 19.9 % 0.00 % -
16 16 32 32 32 32 32 32 32 32 1 2 3 4 5 6 7 8
32 32
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In [17] the results are based on theoretical calculations and in this project they are based on experimental results. It can be seen that the experimental results from this project are in agreement with [17]. In [17] it is stated about the values in Table 4:
the values given correspond to the hardware savings of truncated multipliers compared with conventional multipliers which implement round to nearest by adding a one to column n-1. For this table, the relative sizes of the AND gates, half adders and full adders are 1, 4 and 9, respectively. The relative size of each full adder in the CLA is 9 and a 4-bit CLA logic block has a relative size of 20. [17]
The same model is implemented in this project as in [17] except for three things:
n half adders are used in [17] instead of full adders, where n is the size of the inputs. Since half adders and full adders have the same relative size in [17] this does not affect the results.
A simpler full-array multiplier is used in [17] compared to the CSAs used in this project. The area used, however, is equivalent as it is only a matter of how the carries are passed on.
These differences are judged as minor differences, which can explain the deviations in Table 4. They do not affect the overall conclusion.
7.2 Simulink
As mentioned previously overflow occurs when using Simulink to simulate the multiplier for inputs of more than 15 bits and this immediately raises the question if Simulink is even the right tool. It is an easy readily understood tool with a user-friendly interface but it is not as powerful as other tools (E.g. Matlab). The multiplier itself was implemented using an Embedded Matlab Function but these inherit the restrictions enforced on
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Simulink and are as such not as useful as pure Matlab functions. It is therefore suggested to implement the model using only the Matlab programming language.
7.3 Perspectives
Truncation is a method widely used. There are great possibilities in using truncation as it has always been a concern problem to reduce area-on-chip along with power dissipation and complexity of the components. Some of the many examples of use can be found in [1], [2], [4], [5], [18].
Specific for this project, correcting the Simulink model or rewriting it completely using the Matlab programming language is a pending problem. Also, simulating the maximum error would be helpful as such a table is very helpful when deciding the degree of truncation to use.
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8 Conclusion
In this project n-1 Carry-save adders and one Carry look-ahead adder were used to implement a parallel multiplier with truncation, where n is the width of the inputs.
To get the precision error a Simulink model was designed and implemented. Using inputs of more than 15-bits caused overflow. This made simulations unreliable and raised the question whether Simulink was the right tool. Using standard Matlab programming was suggested. The results though clearly demonstrated how truncation introduced large errors but also how those errors could be reduced to an acceptable level by introducing a simple correction constant. In [17] the maximum precision error of a single sample on a similar multiplier was predicted using theoretical calculations. These revealed that the maximum error increased as the degree of the truncation increased. Lastly, more complex correction methods could be used to reduce the precision error even further but this was not within the scope of this project [12], [13], [14], [15].
The Multiplier was also implemented and simulated in ModelSim using the hardware description language VHDL. Furthermore the VHDL model was synthesized using Xilinx ISE to evaluate hardware savings. This showed that hardware savings of up to 46.08 % for 32-bit inputs could be achieved. The hardware savings from this project were also compared with [17]. It was found that the theoretical predictions made in [17] and the results presented in this project were in agreement.
To conclude the project it can be said that even high levels of truncation lead to a relatively small precision error. This means that truncated multipliers offer significant hardware savings for applications, which do not require exact multiplication. Given specific hardware and precision constraints, the right number of columns to truncate for 8, 16 and 32 bits can easily be determined. Future work could be to extend to multiple multipliers and/or multipliers that form the partial product matrix through other
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techniques (e.g. modified booth encoding [1], [18]). Some examples of use can be found in [1], [2], [4], [5], [18].
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9 References
[1] Tso-Bin Juang, Shen-Fu-Hsiao, Low-Error Carry-Free Fixed-Width Multipliers With Low-Cost Composation Circuits, IEEE Transactions on circuits and systems-II: Express briefs, Vol. 52, No. 6, June 2005, (.PDF file). [2] E. George Walters III, Mark G. Arnold, Michael J. Schulte, Using Truncated Multipliers in DCT and IDCT hardware accelerators, (.PDF file). [3] Sunder S. Kidambi, Fayez El-Guibaly, Andreas Antoniou, Area-Efficient Multipliers for Digital Signal Processing Applications, IEEE Transactions on Circuits and SystemsII: Analog and Digital Signal Processing, Vol. 43, No. 2, February 1996, (.PDF file). [4] Florean Curticapean, Jarkko Niitylahti, A Hardware Efficient Direct Digital Frequency Synthesizer, Tampere (.PDF file). [5] E. George Walters III, Michael J. Schulte, Design Tradeoffs Using Truncated Multipliers In FIR Filter implementations, Lehigh University, (.PDF file) [6] [7] [8] http://www.systemc.org/home (last visited 24/6-2009). http://www.systemverilog.org/ (last visited 24/6-2009) Prof. Loh - Carry-Save Addition, CS3220 Processor Design February 2, 2005, (.PDF file). [9] http://www.aoki.ecei.tohoku.ac.jp/arith/mg/algorithm.html (last visited 24/62009) [10] http://www.statemaster.com/encyclopedia/Adder-(electronics), homepage, last visited 21/7-2009. [11] David A. Patterson, John L. Hennesey, Computer Organization And Design The Hardware/Software Interface, 3rd edition, revised printing, Morgan Kaufmann publishers, 2007, ISBN: 978-0-12-370606-5. [12] Lan-Da Van, Chih-Chyau Yang, Generalized Low-Error Area-Efficient FixedWidth Multipliers, (.PDF file). [13] Eric J. King, Earl E. Swartzlander, Jr. Data-Dependent Truncation Scheme for Parallel Multipliers, Texas, (.PDF file).
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[14] E. George Walters III, Michael J. Schulte, Efficient Function Approximation Using Truncated Multipliers and Squarers, USA, (.PDF file). [15] James E. Stine, Oliver M. Duverne, Variations on Truncated Multiplication, Illinois, (.PDF file) [16] Peter J. Ashenden, The Designers Guide To VHDL, 2nd Edition, 1996, ISBN: 1-55860-674-2. [17] Michael J. Schulte, Earl E. Swartzlander, Jr., Truncated Multiplication with Correction Constant, (.PDF file). [18] Alok A. Katkar, james E. Stine, Modified Booth Truncated Multipliers, Illinois (.PDF file)
Pictures and homepages of tools used are referenced to directly in the report.
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Figure 19: The rounding sub-system The input is converted to a 32bit integer, a constant is added and the integer is first right shifted, then lefting shifted (here 8 bits each way). This is done to simulate the rounding error.
Figure 20: The Random Number Generator sub-system Two random numbers are generated and converted to 32-bit integers.
Figure 21: The Average Calc sub-system The first part of the subsystem takes the sum of all samples and the second part divides with the number of samples performed at any given time. The block Counter functions as a +1 counter.
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sumbin(j) = sumbin(j) - carry * 2; %% setting final partiel product produkt end %%% Here the binary sum vector is converted to back to an integer for j = 0:n*2-1 sum = sum + sumbin(2*n-j)*pow2(j); end int32(sum); end
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entity Mult is generic ( left : natural := 7; -- position of MSB T : integer := 7 -- truncation of 0 means no truncation ); port ( a : in std_logic_vector(left downto 0); b : in std_logic_vector(left downto 0); -y_round: out std_logic_vector(left downto 0); --only used for rounding y : out std_logic_vector(2*left+1 downto 0) ); end Mult; architecture circuits of Mult is constant zero : std_logic_vector(left downto 0) := (others => '0'); signal nc1 : std_logic; type arr is array(0 to left) of std_logic_vector(left downto 0); signal c : arr := (others => (others => '0')); -- carries equals amount of adders signal s : arr := (others => (others => '0')); -- partial sums signal ss : arr := (others => (others => '0')); -- shifted sums
component CSA_g -- duplicates entity port generic ( left : integer; T : integer ); port ( b : in std_logic; -- a multiplier bit a : in std_logic_vector(left downto 0); -- multiplicand sum_in : in std_logic_vector(left downto 0); -- sums from previous stage cin : in std_logic_vector(left downto 0); -- carrys from previous stage sum_out : out std_logic_vector(left downto 0); -- sums to next stage cout : out std_logic_vector(left downto 0) -- carrys to next stage ); end component CSA_g;
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component CLA_g -- duplicates entity port generic(left: integer); port (a : in std_logic_vector (left downto 0); b : in std_logic_vector (left downto 0); cin : in std_logic; sum : out std_logic_vector (left downto 0); cout : out std_logic ); end component CLA_g;
begin -- circuits of Mult --for truncation. Only affects p(0) trunc: process(a,b,s) is begin if (T > 0 and b(0) = '1' ) then s(0) <= a(left downto 1)&'0'; elsif (T = 0 and b(0) = '1') then s(0) <= a; else -- if b(0) = '0' it doesnt matter what T is s(0) <= zero; end if; end process trunc; ss(0) <= '0'&s(0)(left downto 1); y(0) <= s(0)(0);
-- VHDL 'generate' to have less statements stage: for I in 1 to left generate st: CSA_g generic map(left,T-I) --position of MSB and level of truncation port map(b(I), a, ss(I-1), c(I-1), s(I), c(I)); ss(I) <= '0'&s(I)(left downto 1); y(I) <= s(I)(0); end generate stage;
add: CLA_g generic map(left) port map(ss(left), c(left), '0', y(left*2+1 downto left+1), nc1); -- Use this adder instead for rounding to left+1 bits
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-- add_round: CLA_g -generic map(left) -- port map(ss(left), c(left), y(left), y_round(left downto 0), nc1);
11.2 Components.vhd
library IEEE; use IEEE.std_logic_1164.all; entity fadd is -- a, b and the carry-in ci are inputs of the adder. -- s is the sum output, co is the carry-out. port ( a, b : in std_logic; cin : in std_logic; s : out std_logic; cout : out std_logic ); end fadd; architecture circuits of fadd is begin -- This full-adder architecture contains two concurrent assignment. -- Compute the sum. s <= a xor b xor cin; -- Compute the carry. cout <= (a and b) or (a and cin) or (b and cin); end circuits;
--Carry-look ahead adder n-bit adder used as the final adder LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; entity CLA_g IS generic(left : natural := 31 -- top bit ); port (a : in std_logic_vector (left downto 0); b : in std_logic_vector (left downto 0); cin : in std_logic; sum : out std_logic_vector (left downto 0); cout : out std_logic );
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end CLA_g; architecture circuits OF CLA_g IS signal signal signal signal h_sum : carry_generate carry_propagate carry_in_internal std_logic_vector(left downto 0); : std_logic_vector(left downto 0); : std_logic_vector(left downto 0); : std_logic_vector(left downto 1);
begin h_sum <= a xor b; carry_generate <= a and b; carry_propagate <= a or b; process (carry_generate,carry_propagate,carry_in_internal,cin) begin carry_in_internal(1) <= carry_generate(0) or (carry_propagate(0) and cin); inst: for i in 1 to left-1 loop carry_in_internal(i+1) <= carry_generate(i) or (carry_propagate(i) and carry_in_internal(i)); end loop; cout <= carry_generate(left) or (carry_propagate(left) and carry_in_internal(left)); end process; sum(0) <= h_sum(0) xor cin; sum(left downto 1) <= h_sum(left downto 1) xor carry_in_internal(left downto 1); end circuits; library IEEE; use IEEE.std_logic_1164.all;
entity CSA_g is generic( left : integer := 7; T : integer := 0 --0 means no truncation ); port( b : in std_logic; -- a multiplier bit a : in std_logic_vector(left downto 0); -- multiplicand sum_in : in std_logic_vector(left downto 0); -- sums from previous stage cin : in std_logic_vector(left downto 0); -- carrys from previous stage sum_out : out std_logic_vector(left downto 0) := (others => '0'); -- sums to next stage cout : out std_logic_vector(left downto 0) := (others => '0') -- carrys to next stage );
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end CSA_g; architecture circuits of CSA_g is signal zero : std_logic_vector(left downto 0) := (others => '0'); signal aa : std_logic_vector(left downto 0) := (others => '0'); component fadd -- duplicates entity port port(a : in std_logic; b : in std_logic; cin : in std_logic; s : out std_logic; cout : out std_logic); end component fadd; begin -- circuits of CSA_g -- If T is negative just use 0 as T aa <= a when b = '1' else zero; s1: IF T < 0 generate st1: for I in 0 to left generate sta: fadd port map(aa(I), sum_in(I), cin(I) , sum_out(I), cout(I)); end generate st1; end generate s1; s2: IF T >= 0 generate st2: for I in T to left generate sta: fadd port map(aa(I), sum_in(I), cin(I) , sum_out(I), cout(I)); end generate st2; end generate s2; end architecture circuits; -- of CSA_g
-- This is the generic n-bit adder and the CLA_g was used to compare hardware savings. -- It was found that the area used was the same for the two. library IEEE; use IEEE.std_logic_1164.all; entity add_g is --generic n-bit adder generic(left : natural := 31 -- top bit ); port (a : in std_logic_vector (left downto 0); b : in std_logic_vector (left downto 0); cin : in std_logic; sum : out std_logic_vector (left downto 0); cout : out std_logic); end add_g;
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architecture circuits of add_g is signal isum : std_logic_vector(left downto 0); -- internal signal carry : std_logic_vector(left+1 downto 0); -- internal begin -- circuits carry(0) <= cin; adder: for i in 0 to left generate isum(i) <= a(i) xor b(i) xor carry(i); carry(i+1) <= (a(i) and b(i)) or (a(i) and carry(i)) or (b(i) and carry(i)); end generate adder; sum <= isum; cout <= carry(left+1); end architecture circuits; -- of add_g
11.3 Testbench.vhd
library IEEE; use IEEE.std_logic_1164.all; entity testbench is end testbench;
architecture arch32 of testbench is signal a_i,b_i:std_logic_vector(31 downto 0); --signal y_i_round: std_logic_vector(31 downto 0); type arr is array(0 to 31) of std_logic_vector(63 downto 0); signal y : arr; -- All the 32-bit products of the testbench begin --this generate loop generates 31 multipliers with the same inputs but --31 different levels of truncation (T=0 => T=31) stage: for I in 0 to 31 generate mult: entity work.Mult(circuits) -- K = N-T generic map(left => 31,T => I) --position of MSB and level of truncation port map(a_i,b_i,y(I)); -- add y_i_round if rounding is needed end generate stage;
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stimulus: process begin a_i<=X"11111111";b_i<=X"11111111"; wait for 10 ns; if now=10 ns then wait; end if; end process stimulus; end arch32;
architecture arch16 of testbench is signal a_i,b_i:std_logic_vector(15 downto 0); -- signal y_i_round: std_logic_vector(15 downto 0); signal y_i: std_logic_vector(31 downto 0); begin mult: entity work.Mult(circuits) -- K = N-T generic map(left => 15,T => 4) --position of MSB and level of truncation port map(a_i,b_i,y_i); -- add y_i_round if rounding is needed stimulus: process begin a_i<="1011101110111011";b_i<="1100110011001100"; wait for 10 ns; a_i<="0111011101110111";b_i<="1011101110111011"; wait for 10 ns; a_i<="1101110111011101";b_i<="0111011101110111"; wait for 10 ns; a_i<="1111111111111111";b_i<="0010001000100010"; wait for 10 ns; a_i<="1101110111011101";b_i<="1000100010001000"; wait for 10 ns; a_i<="1111111111111111";b_i<="1111111111111111"; wait for 10 ns; a_i<="1111111111111111";b_i<="0010001000100010"; wait for 10 ns; a_i<="1011101110111011";b_i<="1011101110111011"; wait for 10 ns;
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a_i<="0110011001100110";b_i<="1010101010101010"; wait for 10 ns; a_i<="1101110111011101";b_i<="1010101010101010"; wait for 10 ns; if now=100 ns then wait; end if; end process stimulus; end arch16;
architecture arch8 of testbench is signal a_i,b_i:std_logic_vector(7 downto 0); -- signal y_i_round: std_logic_vector(7 downto 0); signal y_i: std_logic_vector(15 downto 0); begin mult: entity work.Mult(circuits) -- K = N-T generic map(left => 7,T => 0) --position of MSB and level of truncation port map(a_i,b_i,y_i); -- add y_i_round if rounding is needed stimulus: process begin a_i<="10111010";b_i<="11011100"; wait for 10 ns; a_i<="01111010";b_i<="10101111"; wait for 10 ns; a_i<="11001011";b_i<="01110101"; wait for 10 ns; a_i<="11111111";b_i<="00010010"; wait for 10 ns; a_i<="11000001";b_i<="10001000"; wait for 10 ns; a_i<="11111111";b_i<="11111111"; wait for 10 ns; a_i<="11110101";b_i<="00001011"; wait for 10 ns; a_i<="11011011";b_i<="10101101"; wait for 10 ns; a_i<="00110110";b_i<="10000110"; wait for 10 ns;
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a_i<="11010110";b_i<="10100110"; wait for 10 ns; if now=100 ns then wait; end if; end process stimulus; end arch8;
--arch4 with only 4 bits inputs is used for testing since --it is easy to follow using the "pen and paper" method architecture arch4 of testbench is signal a_i,b_i:std_logic_vector(3 downto 0); --signal y_i_round: std_logic_vector(3 downto 0); signal y_i_3: std_logic_vector(7 downto 0); signal y_i_2: std_logic_vector(7 downto 0); signal y_i_1: std_logic_vector(7 downto 0); signal y_i_0: std_logic_vector(7 downto 0); begin mult_3: entity work.Mult(circuits) -- K = N-T generic map(left => 3,T => 3) --position of MSB and level of truncation port map(a_i,b_i,y_i_3); -- add y_i_round if rounding is needed mult_2: entity work.Mult(circuits) -- K = N-T generic map(left => 3,T => 2) --position of MSB and level of truncation port map(a_i,b_i,y_i_2); -- add y_i_round if rounding is needed mult_1: entity work.Mult(circuits) -- K = N-T generic map(left => 3,T => 1) --position of MSB and level of truncation port map(a_i,b_i,y_i_1); -- add y_i_round if rounding is needed mult_0: entity work.Mult(circuits) -- K = N-T generic map(left => 3,T => 0) --position of MSB and level of truncation port map(a_i,b_i,y_i_0); -- add y_i_round if rounding is needed stimulus: process begin
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a_i<="0000";b_i<="0000"; wait for 10 ns; a_i<="1111";b_i<="1111"; wait for 10 ns; a_i<="0000";b_i<="1111"; wait for 10 ns; a_i<="1111";b_i<="0000"; wait for 10 ns; a_i<="1100";b_i<="1100"; wait for 10 ns; a_i<="0011";b_i<="0011"; wait for 10 ns; a_i<="1010";b_i<="0101"; wait for 10 ns; if now=70 ns then wait; end if; end process stimulus; end arch4;
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Figure 23: left = 3, T = 3. Binary representation It is seen that since T = 3, the four last product bits are always 0 due to truncation. Going through these results using the pen-and-paper method shows that the results are correct.
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Figure 24: left = 3, T = 3. Unsigned representation. Like in picture Figure 23 but with unsigned representation. Notice how the products are a bit too small compared to the real product. This is expected as some 1s are lost due to truncation.
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Figure 25: Left = 31, T = 0 - 28. Binary representation 29 multipliers are shown above with degree of truncation T = 0 31. Notice how the T least significant bits (everything right of the red line) of the products are all 0.
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Figure 26: Left = 31, T = 0 - 28. Unsigned representation 29 multipliers are shown above with degree of truncation T = 0 31. The products become smaller as the degree of truncation increases. This is expected as some 1s are lost due to truncation.
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Figure 27: left = 3, T = 0 - 3. Binary representation 4 multipliers are shown all with the same inputs (a and b). Mult_0 has no truncation, Mult_1 has truncation degree T = 1 and so on. Notice how the least significant bits become 0 when truncation increases. The bottom of this diagram unrolls the signals of Mult_3.
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Figure 28: left = 3, T = 0 - 3. Unsigned representation Same as with figure 26 but in unsigned representation. Notice how the products become smaller when truncation is applied.
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Add_G: Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: CLA_g: Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs:
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k = 8 => T = 24
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 840 out of 2352 35% 1461 out of 4704 31% 128 128 out of 140 91%
k = 7 => T = 25
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 813 out of 2352 34% 1414 out of 4704 30% 128 128 out of 140 91%
k = 6 => T = 26
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 784 out of 2352 33% 1364 out of 4704 28% 128 128 out of 140 91%
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k = 5 => T = 27
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 754 out of 2352 32% 1312 out of 4704 27% 128 128 out of 140 91%
k = 4 => T = 28
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 724 out of 2352 30% 1259 out of 4704 26% 128 128 out of 140 91%
k = 3 => T = 29
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 692 out of 2352 29% 1203 out of 4704 25% 128 128 out of 140 91%
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k = 2 => T = 30
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 658 out of 2352 27% 1145 out of 4704 24% 128 128 out of 140 91%
k = 1 => T = 31
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 624 out of 2352 26% 1086 out of 4704 23% 128 128 out of 140 91%
k = 16 => T = 0 Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 284 out of 2352 12% 494 out of 4704 10% 64 64 out of 140 45%
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k = 6 => T = 10 Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 232 out of 2352 9% 404 out of 4704 8% 64 64 out of 140 45%
k = 5 => T = 11 Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 221 out of 2352 9% 384 out of 4704 8% 64 64 out of 140 45%
k = 4=> T = 12 Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 209 out of 2352 8% 363 out of 4704 7% 64 64 out of 140 45%
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k = 3 => T = 13 Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 195 out of 2352 8% 339 out of 4704 7% 64 64 out of 140 45%
k = 2 => T = 14
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 180 out of 2352 7% 313 out of 4704 6% 64 64 out of 140 45%
k = 1 => T = 15
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 164 out of 2352 6% 286 out of 4704 6% 64 64 out of 140 45%
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k = 8 => T = 0
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 68 out of 2352 2% 118 out of 4704 2% 32 32 out of 140 22%
k = 5 => T = 3 Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 64 out of 2352 2% 111 out of 4704 2% 32 32 out of 140 22%
k = 4 => T = 4
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 61 out of 2352 2% 106 out of 4704 2% 32 32 out of 140 22%
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k = 3 => T = 5
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 57 out of 2352 2% 99 out of 4704 2% 32 32 out of 140 22%
k = 1 => T = 7
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 44 out of 2352 1% 77 out of 4704 1% 32 32 out of 140 22%
k = 2 => T = 6
Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: 51 out of 2352 2% 88 out of 4704 1% 32 32 out of 140 22%
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========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "Mult.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name Output Format Target Device
---- Source Options Top Module Name : Mult Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes
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Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Asynchronous To Synchronous : NO Multiplier Style : lut Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 100 Add Generic Clock Buffer(BUFG) : 4 Register Duplication : YES Slice Packing : YES Optimize Instantiated Primitives : NO Convert Tristates To Logic : Yes Use Clock Enable : Yes Use Synchronous Set : Yes Use Synchronous Reset : Yes Pack IO Registers into IOBs : auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort :1 Library Search Order : Mult.lso Keep Hierarchy : NO RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator :/ Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 =========================================================================
========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "//adserv1.imm.dtu.dk/users/s053010/Bachelor/VHDL_project/4x4/components.vhd" in Library work. Architecture circuits of Entity fadd is up to date. Architecture circuits of Entity cla_g is up to date.
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Architecture circuits of Entity csa_g is up to date. Compiling vhdl file "//adserv1.imm.dtu.dk/users/s053010/Bachelor/VHDL_project/4x4/nxn_mult.vhd" in Library work. Entity <mult> compiled. Entity <mult> (Architecture <circuits>) compiled. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity <Mult> in library <work> (architecture <circuits>) with generics. T=7 left = 7 Analyzing hierarchy for entity <CSA_g> in library <work> (architecture <circuits>) with generics. T=6 left = 7 Analyzing hierarchy for entity <CSA_g> in library <work> (architecture <circuits>) with generics. T=5 left = 7 Analyzing hierarchy for entity <CSA_g> in library <work> (architecture <circuits>) with generics. T=4 left = 7 Analyzing hierarchy for entity <CSA_g> in library <work> (architecture <circuits>) with generics. T=3 left = 7 Analyzing hierarchy for entity <CSA_g> in library <work> (architecture <circuits>) with generics. T=2 left = 7 Analyzing hierarchy for entity <CSA_g> in library <work> (architecture <circuits>) with generics. T=1 left = 7 Analyzing hierarchy for entity <CSA_g> in library <work> (architecture <circuits>) with generics. T=0 left = 7 Analyzing hierarchy for entity <CLA_g> in library <work> (architecture <circuits>) with generics. left = 7 Analyzing hierarchy for entity <fadd> in library <work> (architecture <circuits>).
========================================================================= * HDL Analysis * ========================================================================= Analyzing generic Entity <Mult> in library <work> (Architecture <circuits>). T=7 left = 7 Entity <Mult> analyzed. Unit <Mult> generated. Analyzing generic Entity <CSA_g.1> in library <work> (Architecture <circuits>).
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T=6 left = 7 Entity <CSA_g.1> analyzed. Unit <CSA_g.1> generated. Analyzing Entity <fadd> in library <work> (Architecture <circuits>). Entity <fadd> analyzed. Unit <fadd> generated. Analyzing generic Entity <CSA_g.2> in library <work> (Architecture <circuits>). T=5 left = 7 Entity <CSA_g.2> analyzed. Unit <CSA_g.2> generated. Analyzing generic Entity <CSA_g.3> in library <work> (Architecture <circuits>). T=4 left = 7 Entity <CSA_g.3> analyzed. Unit <CSA_g.3> generated. Analyzing generic Entity <CSA_g.4> in library <work> (Architecture <circuits>). T=3 left = 7 Entity <CSA_g.4> analyzed. Unit <CSA_g.4> generated. Analyzing generic Entity <CSA_g.5> in library <work> (Architecture <circuits>). T=2 left = 7 Entity <CSA_g.5> analyzed. Unit <CSA_g.5> generated. Analyzing generic Entity <CSA_g.6> in library <work> (Architecture <circuits>). T=1 left = 7 Entity <CSA_g.6> analyzed. Unit <CSA_g.6> generated. Analyzing generic Entity <CSA_g.7> in library <work> (Architecture <circuits>). T=0 left = 7 Entity <CSA_g.7> analyzed. Unit <CSA_g.7> generated. Analyzing generic Entity <CLA_g> in library <work> (Architecture <circuits>). left = 7 Entity <CLA_g> analyzed. Unit <CLA_g> generated.
========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit <CLA_g>. Related source file is "//adserv1.imm.dtu.dk/users/s053010/Bachelor/VHDL_project/4x4/components.vhd". Found 7-bit xor2 for signal <sum<7:1>>. Found 8-bit xor2 for signal <h_sum>. Unit <CLA_g> synthesized.
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Synthesizing Unit <fadd>. Related source file is "//adserv1.imm.dtu.dk/users/s053010/Bachelor/VHDL_project/4x4/components.vhd". Found 1-bit xor3 for signal <s>. Summary: inferred 1 Xor(s). Unit <fadd> synthesized.
Synthesizing Unit <CSA_g_1>. Related source file is "//adserv1.imm.dtu.dk/users/s053010/Bachelor/VHDL_project/4x4/components.vhd". WARNING:Xst:1305 - Output <cout<5:0>> is never assigned. Tied to value 000000. WARNING:Xst:1305 - Output <sum_out<5:0>> is never assigned. Tied to value 000000. WARNING:Xst:647 - Input <sum_in<5:0>> is never used. WARNING:Xst:647 - Input <cin<5:0>> is never used. WARNING:Xst:646 - Signal <aa<5:0>> is assigned but never used. WARNING:Xst:653 - Signal <zero> is used but never assigned. Tied to value 00000000. Unit <CSA_g_1> synthesized.
Synthesizing Unit <CSA_g_2>. Related source file is "//adserv1.imm.dtu.dk/users/s053010/Bachelor/VHDL_project/4x4/components.vhd". WARNING:Xst:1305 - Output <cout<4:0>> is never assigned. Tied to value 00000. WARNING:Xst:1305 - Output <sum_out<4:0>> is never assigned. Tied to value 00000. WARNING:Xst:647 - Input <sum_in<4:0>> is never used. WARNING:Xst:647 - Input <cin<4:0>> is never used. WARNING:Xst:646 - Signal <aa<4:0>> is assigned but never used. WARNING:Xst:653 - Signal <zero> is used but never assigned. Tied to value 00000000. Unit <CSA_g_2> synthesized.
Synthesizing Unit <CSA_g_3>. Related source file is "//adserv1.imm.dtu.dk/users/s053010/Bachelor/VHDL_project/4x4/components.vhd". WARNING:Xst:1305 - Output <cout<3:0>> is never assigned. Tied to value 0000. WARNING:Xst:1305 - Output <sum_out<3:0>> is never assigned. Tied to value 0000. WARNING:Xst:647 - Input <sum_in<3:0>> is never used. WARNING:Xst:647 - Input <cin<3:0>> is never used. WARNING:Xst:646 - Signal <aa<3:0>> is assigned but never used. WARNING:Xst:653 - Signal <zero> is used but never assigned. Tied to value 00000000. Unit <CSA_g_3> synthesized.
Synthesizing Unit <CSA_g_4>. Related source file is "//adserv1.imm.dtu.dk/users/s053010/Bachelor/VHDL_project/4x4/components.vhd". WARNING:Xst:1305 - Output <cout<2:0>> is never assigned. Tied to value 000. WARNING:Xst:1305 - Output <sum_out<2:0>> is never assigned. Tied to value 000. WARNING:Xst:647 - Input <sum_in<2:0>> is never used. WARNING:Xst:647 - Input <cin<2:0>> is never used. WARNING:Xst:646 - Signal <aa<2:0>> is assigned but never used. WARNING:Xst:653 - Signal <zero> is used but never assigned. Tied to value 00000000. Unit <CSA_g_4> synthesized.
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Synthesizing Unit <CSA_g_5>. Related source file is "//adserv1.imm.dtu.dk/users/s053010/Bachelor/VHDL_project/4x4/components.vhd". WARNING:Xst:1305 - Output <cout<1:0>> is never assigned. Tied to value 00. WARNING:Xst:1305 - Output <sum_out<1:0>> is never assigned. Tied to value 00. WARNING:Xst:647 - Input <sum_in<1:0>> is never used. WARNING:Xst:647 - Input <cin<1:0>> is never used. WARNING:Xst:646 - Signal <aa<1:0>> is assigned but never used. WARNING:Xst:653 - Signal <zero> is used but never assigned. Tied to value 00000000. Unit <CSA_g_5> synthesized.
Synthesizing Unit <CSA_g_6>. Related source file is "//adserv1.imm.dtu.dk/users/s053010/Bachelor/VHDL_project/4x4/components.vhd". WARNING:Xst:1305 - Output <cout<0>> is never assigned. Tied to value 0. WARNING:Xst:1305 - Output <sum_out<0>> is never assigned. Tied to value 0. WARNING:Xst:647 - Input <sum_in<0>> is never used. WARNING:Xst:647 - Input <cin<0>> is never used. WARNING:Xst:646 - Signal <aa<0>> is assigned but never used. WARNING:Xst:653 - Signal <zero> is used but never assigned. Tied to value 00000000. Unit <CSA_g_6> synthesized.
Synthesizing Unit <CSA_g_7>. Related source file is "//adserv1.imm.dtu.dk/users/s053010/Bachelor/VHDL_project/4x4/components.vhd". WARNING:Xst:653 - Signal <zero> is used but never assigned. Tied to value 00000000. Unit <CSA_g_7> synthesized.
Synthesizing Unit <Mult>. Related source file is "//adserv1.imm.dtu.dk/users/s053010/Bachelor/VHDL_project/4x4/nxn_mult.vhd". WARNING:Xst:646 - Signal <nc1> is assigned but never used. WARNING:Xst:653 - Signal <c<0>> is used but never assigned. Tied to value 00000000. WARNING:Xst:653 - Signal <zero> is used but never assigned. Tied to value 00000000. Unit <Mult> synthesized.
========================================================================= HDL Synthesis Report Macro Statistics # Xors 1-bit xor2 1-bit xor3 8-bit xor2
: 43 :7 : 35 :1
========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= Loading device for application Rf_Device from file 'v200.nph' in environment C:\Xilinx92i.
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========================================================================= Advanced HDL Synthesis Report Macro Statistics # Xors 1-bit xor2 1-bit xor3 8-bit xor2
: 43 :7 : 35 :1
========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit <Mult> ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block Mult, actual ratio is 1. Final Macro Processing ... ========================================================================= Final Register Report Found no macro ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------No Partitions were found in this design. ------------------------------========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : Mult.ngr Top Level Output File Name : Mult Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs Cell Usage : # BELS
: 32
: 78
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# GND :1 # LUT2 : 15 # LUT3 :8 # LUT4 : 54 # IO Buffers : 32 # IBUF : 16 # OBUF : 16 ========================================================================= Device utilization summary: --------------------------Selected Device : 2s200pq208-5 Number of Slices: Number of 4 input LUTs: Number of IOs: Number of bonded IOBs: --------------------------Partition Resource Summary: --------------------------No Partitions were found in this design. --------------------------44 out of 2352 1% 77 out of 4704 1% 32 32 out of 140 22%
========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: -----------------No clock signals found in this design Asynchronous Control Signals Information: ---------------------------------------No asynchronous control signals found in this design Timing Summary: --------------Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 35.140ns Timing Detail: -------------All values displayed in nanoseconds (ns)
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========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 7864 / 9 ------------------------------------------------------------------------Delay: 35.140ns (Levels of Logic = 15) Source: a<7> (PAD) Destination: y<15> (PAD) Data Path: a<7> to y<15> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- -----------IBUF:I->O 16 0.924 2.800 a_7_IBUF (a_7_IBUF) LUT4:I0->O 2 0.653 1.340 stage[1].st/s2.st2[6].sta/cout1 (c<1><6>) LUT4:I2->O 2 0.653 1.340 stage[2].st/s2.st2[6].sta/Mxor_s_xo<1>1 (s<2><6>) LUT4:I3->O 2 0.653 1.340 stage[3].st/s2.st2[5].sta/Mxor_s_xo<1>1 (s<3><5>) LUT4:I3->O 2 0.653 1.340 stage[4].st/s2.st2[4].sta/Mxor_s_xo<1>1 (s<4><4>) LUT4:I3->O 2 0.653 1.340 stage[5].st/s2.st2[3].sta/Mxor_s_xo<1>1 (s<5><3>) LUT4:I3->O 2 0.653 1.340 stage[6].st/s2.st2[2].sta/Mxor_s_xo<1>1 (s<6><2>) LUT4:I3->O 3 0.653 1.480 stage[7].st/s2.st2[1].sta/Mxor_s_xo<1>1 (s<7><1>) LUT4:I2->O 2 0.653 1.340 add/carry_in_internal_2_or00001 (add/carry_in_internal<2>) LUT3:I2->O 2 0.653 1.340 add/carry_in_internal_3_or00001 (add/carry_in_internal<3>) LUT3:I2->O 2 0.653 1.340 add/carry_in_internal_4_or00001 (add/carry_in_internal<4>) LUT3:I2->O 2 0.653 1.340 add/carry_in_internal_5_or00001 (add/carry_in_internal<5>) LUT3:I2->O 2 0.653 1.340 add/carry_in_internal_6_or00001 (add/carry_in_internal<6>) LUT4:I0->O 1 0.653 1.150 add/carry_in_internal_7_or00001 (add/carry_in_internal<7>) OBUF:I->O 5.557 y_15_OBUF (y<15>) ---------------------------------------Total 35.140ns (14.970ns logic, 20.170ns route) (42.6% logic, 57.4% route) ========================================================================= CPU : 16.33 / 16.73 s | Elapsed : 16.00 / 16.00 s --> Total memory usage is 134544 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 40 ( 0 filtered) Number of infos : 0 ( 0 filtered)
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