18 views

Uploaded by Truong Nguyen

- The Study of PWM Methods in Permanent Magnet Brushless DC Motor Speed Control System
- PE Lesson Plan
- 1
- Springer (IJ 6)
- IETE Journal of Research
- IRJET-Design and Implementation of an Efficient Soft Switching Inverter Fed Ac Drive
- 76292560 Electric Machines and Drives 259
- SVPWM Thesis Prepared by Deekshit
- Bd 35310316
- Drives Montado Sempai Nel
- EE1351-QB
- 6. three phase inverter-1.docx
- 17 Chapter 7
- e2173c7e45f85c960cb4bd78acec2d1c.pdf
- Mini Project Report 2.pdf
- untitled
- 2010_IEEE_ECE
- IRJET-Hybrid Reference Frame Control of AC-DC Converter
- WEG Vfds vs Soft Starters White Paper Vfdsvssoftstarters Technical Article English
- Basic Drive Training

You are on page 1of 54

Topologies

Single-phase inverters Three-phase inverters

Gating patterns

Square wave operation Pulse width modulation (PWM) Selected harmonic elimination (SHE) Delta modulation

1

4.1 Introduction

Inverters:

Input: dc voltage, fixed magnitude Output: ac voltage, adjustable frequency and adjustable magnitude

Main feature:

dc-to-ac conversion Solid state device, no rotating machines.

4.1 Introduction

Types

Voltage source inverter (VSI): voltage source dc power supply. Output voltage is defined, based on the gating pattern. Output current is dependent on the load

Widely used in industry

Current source inverter (CSI): current source dc power supply. Output current is defined, based on the gating pattern. Output voltage is dependent on the load

Single-phase inverter

Circuit diagram

T1~T4 IGBTs, switching devices D1~D4 Freewheeling diodes C dc filter capacitor (VSI) Vd dc link voltage

P

+

T1

g1

C

D1

T3

D3 B D2

g3

Vd

N

A T4

io +

D4

L

vo R

g4

g2

T2

vg1, vg2

vg3, vg4 vAN

waveforms

T

t t Vd t Vd Vd t t t

Period I II III IV T1, T2 on T3, T4 on D3, D4 on D1, D2 on

vBN

vAB

io

Vd

Period I: vg1=vg2>0 T1, T2 on, current path: Vd+T1LoadT2Vdvo=Vd Period II: vg3=vg4>0 But io>0 D3, D4 on, energy stored in L is releasing to Vd, current path: Vd-D4LoadD3Vd+ Period III: vg3=vg4>0 But io<0 T3, T4 on, current path: Vd+T3LoadT4VdPeriod IV: vg1=vg2>0 But io<0 D1, D2 on, energy stored in L is releasing to Vd, current path: Vd-D2LoadD2Vd+

rms value of output voltage 1 T 2 vo dt = Vd T 0 Fourier series output voltage Vo ,rms = vo (t ) = 4Vd 4V sin nt = d n =1, 3, 5... n

Analysis

I on ,rms

Von ,rms

nL

1 1 sin t + sin 3t + sin 5t + ... 3 5 rms value of fundamental component 2 4Vd f = 2 = Vo1,rms = 2 = 0.9Vd T Fourier series of output current io (t ) =

n =1, 3, 5...

n =1, 3, 5...

n R + (nL )

2

4Vd

sin (nt n )

2

and n = tan 1

nL R

6

4.2 Example

RLC load

P + g1 Vd

N

T1 C g4 A T4

D1

+

T3 g3 vo

L

D3 B D2

io C g2 T2

D4

Load

Example R = 10, L = 31.5mH, C = 112F, Vd = 220V, f o = 60Hz Find : a) Fourier series of io (up to 9th order harmonic) b) I o1,rms , c) THD, d) Pload , and e) I d

8

Three-phase inverter

Circuit diagram

T1~T6 IGBTs, switching devices D1~D6 Freewheeling diodes C dc filter capacitor Vd (VSI) Vd dc link voltage R three-phase resistive load

P + g1 C T1 A

D1

T3 g3

B

D3

T5

D5 iA iB iC D2 R n

g5

C

g4 T4

g6

D4

g2 T6 D6

T2

11

vg1

T

60 60 60

Note:

120 120

Vd

vg5 and vg2 are complimentary (2) VAN is controlled by vg1. They t have the same wave shape

t Vd t t t Vd t

VBN is controlled by vg3. They have the same wave shape VCN is controlled by vg5. They have the same wave shape

12

vAN vBN vCN

Vd

120

t Vd

120

Note: (1) VAN leads VBN 120 VBN leads VCN 120 VCN leads VAN 120

t Vd

vAB

vBC

VBC leads VCA 120 VCA leads VAB 120 (3) VAN lags VAB 30 VBN lags VBC 30 VCN lags VCA 30

Vd

60

Vd Vd Vd Vd

vCA

Vd

Vd

t

13

vg1 vg2 vg3 vg4 vg5 vg6

T6 on I II III IV V VI

Switching sequence

T1 on

T2 on T3 on T4 on T5 on T6 on I II III IV T1 on Note:

t Period I: T5, T6 and T1 on t Period II: T6, T1 and T2 on t Period III: T1, T2 and T3 on t Period IV: T2, T3 and T4 on t Period V: T3, T4 and T5 on t

Period VI: T4, T5 and T6 on

14

Waveforms, phase voltage on load

Period I: T5, T6 and T1 on Period III: T1, T2 and T3 on Period V: T3, T4 and T5 on

+ Vd

A R C R

+ Vd

A R B R

R R R R R

R R R

+ Vd

C R

A

+ Vd

A R C R

+ Vd

C R

A

+ Vd

15

Waveforms, phase voltage on load

vAn

2 3 d

1 3 d

Note:

vBn

t

vCn

t

I II III IV V VI I II III IV

16

rms value VLL,rms =

7 1 sin 7t + 6 7

+ ...

2=

Vd = 0.78Vd

triple - order harmonics 9 1 4Vd 3 1 4Vd = 0, VAB 9,rms = =0 sin sin 3 3 2 9 2 3 Other harmonics VAB 3,rms = VAB 5,rms = 1 4Vd 5 = 0.156Vd sin 5 3 2

17

Analysis, phase voltage

rms value V p ,rms 1 = T

2=

Vd = 0.45Vd

triple - order harmonics VAn 3,rms = 0, VAn 9,rms = 0 Other harmonics 1 2Vd VAn 5,rms = = 0.09Vd 2 5

18

Analysis, harmonic equivalent circuit

V An ,n , rms I An , rms n V Bn ,n , rms I Bn ,rms jn L jn L jn L R

R R

Fourier series of i A iA =

n =1, 3, 5, 7...

3n R 2 + (nL ) n L R

4Vd

sin

n n sin sin( nt n ) 2 3

where n = tan 1

19

Load neutral voltage

Note: In practical design, the neutral of capacitors is not grounded because of the grounded threephase power supply.

Vd 2 + Vd g4 C 2 T4

C T1 g1 A

D1

T3

g3

B

D3

T5

D5 iA iB iC D2 R n + vn

g5

C

Neutral point grounded three-phase inverter vn: voltage of load neutral respect to ground vA: voltage of node A respect to ground vB: voltage of node B respect to ground vC: voltage of node C respect to ground

20

Ground

g6

D4

g2 T6

D6

T2

Load neutral voltage

vg1 vg4 vA

Vd 2 Vd 2

t magnitude t t

2Vd 1 1 sin t + sin 3t + sin 5t 3 5 1 1 + sin 7t + sin 9t... 7 9

vAn vn

1 6 d

2 3 d

vA =

1 3 d

v An =

1 d 6V

2Vd 1 1 sin t + sin 5t + sin 7t + ... 5 7 2V 1 1 1 vn = d sin 3t + sin 9t + sin 15t + ... 3 9 15

21

Load neutral voltage

VAn ,rms I jn L An , rms VBn ,rms I Bn ,rms VCn ,rms I Cn ,rms

R

jn L R

jn L R

Harmonic Equivalent circuit Triple-order harmonic: voltages are in phase. But no current path between node n and ground. Then the voltage will be applied to the load neutral Other harmonics: voltages are not in phase (120 lagging or leading). The three harmonic voltages are three-phase balanced voltages, then load neutral voltage is zero.

22

Purpose of using PWM

To make inverter output voltage adjustable To make inverter output frequency adjustable To eliminate low order harmonics

Method

Change the pulse width according to the modulating waveform (sinusoidal, trapezoidal, et al) Carrier waveform: triangular wave

29

Principle

Half bridge inverter

T1, T2 IGBTs, switching devices D1, D2 Freewheeling diodes C dc filter capacitors (VSI) Vd dc link voltage R load

Vd 2 O + Vd 2 C

T1

g1

D1

g2

T2 D2

30

Waveforms, gate signals

Note: m V c V

(1) vg1 and vg2 are complimentary (2) vm is modulating wave (sine) vc is carrier wave (triangular) (3) When vmvc vg1=logic 1

vg1 vg 2 v AO

Vd 2 Vd 2

t t t

vm<vc vg1=logic 0 (4) When vg1=logic 1T1 onvAO=+Vd/2 When vg1=logic 0T2 onvAO=-Vd/2

v AO1

31

Terminology

Amplitude modulation index (ratio) V ma = m V

c

c c

usually 0 < ma 1

How to find fundamental component? use Fourier analysis an =

v AO sin ntdt

32

Spectrum

V AO ,h 0 .8 0.5Vd

0.22

0.818

0.22 h

13 15 17

27 29 31 33

Assume Vd = 100V, VAO,1 = ? AO ,1 V AO ,1 = 0.8 0.5Vd = 0.8 0.5 100 = 40V = 0.8 V 0.5Vd AO ,1 40 V VAO,1 = = = 28.28V 2 2

33

Features

No low order harmonics: in the example, no 3rd, 5th, 7th, 9th, 11th order harmonics High order harmonics can be easily filtered out

34

How to determine harmonic components

Use table 8-1 on text page 207 Note:

mf 9, if mf <9, table 8-1 may not be used Based on half bridge inverter

h 1st mf mf 2 mf 4 2mf 1 2mf 3 2mf 5 ma 0.2 0.2 1.242 0.016 . 0.4 0.4 1.15 0.061 0.6 0.6 1.006 0.131 . 0.8 0.8 0.818 0.22 1.0 1.0 0.601 0.318

35

AO ,h V 0.5Vd

Conclusions

The fundamental component is proportional to amplitude modulation index (ma) The fundamental frequency is determine by the frequency of modulating waveform (vm)

Questions

Q: How to change inverter output frequency? A: Change the frequency of vm (modulating frequency) Q: How to change inverter output voltage? A: Change the amplitude modulation index.

36

Over modulation

m V c V

vg1 vg 2 v AO No switching

Vd 2 Vd 2

t t t

v AO become a squarewave

No switching

39

AO ,1 V 0.5Vd 4 1.0

Fundamental versus ma

Linear

Over modulation

Square wave

1.0

3.24

ma

40

Drawback of over modulation

Low order harmonic components start to appear

V AO ,h 0.5Vd 1 .0

Example : ma = 2.5, m f = 15

mf

41

4.4 Single-phase full bridge inverter with PWM operation Circuit diagram

P

+

T1

g1

C

D1

T3 g3 T2

D3

B D2

Vd

N

A T4

D4 g2

g4

42

4.4 Single-phase full bridge inverter with PWM operation Waveforms, bipolar PWM

m V

c V

Note:

(1) vg1 and vg4 are complimentary signals t vg2 and vg3 are complimentary signals (2) vmvc vg1=vg2=logic 1

vg1 , vg 2 vg 3 , vg 4

v AB

vm<vc vg1=vg2=logic 0

v AB1

Vd

43

4.4 Single-phase full bridge inverter with PWM operation How to determine harmonic components

Use table 8-1 on text page 207 Note:

Table 8-1 is designed for half bridge inverter Half bridge inverter: VAO,p-p=Vd Full bridge inverter: VAB,p-p=2Vd

Given : Full bridge inverter, bipolar PWM, Vd = 300V, ma = 0.8, m f = 39, f m = 47 Hz Find : (1) VAB1,rms = ? (2) Dominant harmonics, m f 2, m f , m f + 2 (rms value)

44

4.4 Single-phase full bridge inverter with PWM operation Waveforms, unipolar PWM

vm vm

Note: (1)vmvc vg1=logic 1,vg4=logic 0

-vm<vc vg3=logic 0,vg2=logic 1

vg1 vg 3

v AB

t

Vd

v AB1

vg1=vg3=logic 0T4 and T2 onvAB=0 vg1=logic 1 and vg3=logic 0T1 and T2 onvAB=Vd vg1=logic 0 and vg3=logic 1T4 and T3 onvAB=-Vd

46

Vd

4.4 Single-phase full bridge inverter with PWM operation Spectrum for unipolar PWM

V AB ,h 0 .8 Vd

1 Bipolar PWM

mf

2mf -1

2mf 2mf +1

47

Table 8-1 can be used for (1) Single-phase half bridge inverter (2) Single-phase full bridge inverter with bipolar PWM Note: coefficient2, dominant harmonics: mf, mf 2, mf 4 (3) Single-phase full bridge inverter with unipolar PWM Note: coefficient2, dominant harmonics: 2mf 1, 2mf 3

50

P + g1 Vd

N

T1 C A

D1

T3

D3

T5

D5 iA iB iC D2 R n

g3

B

g5

C

g4 T4

g6

D4

g2 T6

D6

T2

51

vmA vmB vmC

Note: (1) Modulating waves: three-phase sine waves (vmA, vmB, vmC) with adjustable amplitude and frequency (2) Carrier wave: triangular wave, fixed amplitude, frequency may be adjusted, depends on applications (3) vmAvc T1 onvAN=Vd vmA<vc T4 onvAN=0 vg1 and vg4 are complementary (4) vmBvc T3 onvBN=Vd vmB<vc T6 onvBN=0 vg3 and vg6 are complementary (5) vmCvc T5 onvCN=Vd

t

v AN

t

vBN

t

vCN

t

v AB

v AB ,1

52

Spectrum

53

How to determine harmonic components

Use table 8-2 on text page 228

h 1st mf 2 mf 4 2mf 1 2mf 5 3mf 2 3mf 4 ma 0.2 0.122 0.010 0.116 0.4 0.245 0.037 0.2 0.6 0.367 0.080 0.227 0.8 0.49 0.135 0.005 0.192 0.008 1.0 0.612 0.195 0.011 0.111 0.020

rms value!

VLL ,h Vd

54

Analog circuit

Control wave Carrier wave Comparator + Logic inverter Synchronous PWM: The triangular waveform is synchronized with the sine wave Features: Simple circuit and low cost Sensitive to the noise Gate signal for top device Gate signal for bottom device

Asynchronous PWM: The triangular waveform is NOT synchronized with the sine wave Producing sub-harmonics: the frequency of the harmonic is not integer times of fundamental frequency.

56

Digital circuit

In the interrupt service routine, CPU write the data of sine wave to the compare register Digital comparator Processor

System bus

Compare register

Buffer register

+ -

Counter control

Digital counter Triangular wave is generated by hardware automatically. CPU can control the frequency and the magnitude. Every time when the triangular wave reaches the maximum or minimum value, a interrupt will be generated.

57

Advantages: Stable, very robust to the noise Easy to be controlled by CPU/DSP Reduce the load of CPU/DSP Disadvantages: Expensive hardware High frequency counter

Software

Interrupt request Digital comparator OC1 Processor

System bus

+ -

TCNT

Advantages: Software, less hardware Stable, very robust to the noise Easy to be controlled by CPU/DSP Disadvantages: Increase the calculation load of CPU/DSP

58

Software

vc vm (sine)

' vm (stair )

Ts

Tp = Tg =

k +1 k +2

Interrupt request

Tg

Tp Tg

Ts [1 + ma sin k ] 2 Ts Tp 2

k +1 = k + = t

59

Software programming

At t1, the number in free running counter (TCNT) matches the number of the output compare register (OC1), an interrupt request will be made. Interrupt service routine

Determine the type of interval (gap, or pulse) Set the output pin to logic 0 for gap interval or logic 1 for pulse interval. Calculate the time interval for following T period Clear the interrupt flag and return

If the calculation in the interrupt service routine can not be completed during Tg, the program will crash. What shall we do?

60

Purpose:

To eliminate a number of unwanted low order harmonics To control the fundamental output voltage

Waveforms

61

Waveforms

Three independent switching angles: 1, 2, and 3

Given 1, 2, and 3, the other switching angles are determined due to symmetrical

Eliminate two harmonics (usually 5th and 7th), and To control the fundamental output voltage

Use numerical iteration methods to solve a set of nonlinear equations.

62

Calculations results

Example: At 50% of maximum fundamental voltage, 1=22, 2=36 and 3=52.

Microprocessor programming

Use look-up table

fundamental

1% 2% 3% 4%

63

Block diagram

* ia

Three-phase inverter

g1

ia

Controller

g4

ia

* ia , reference current (phase A)

ia , error signal (phase A)

64

Upper band limit (UBL)

* ia

Note: (1) Assume vg1=1T1 onia until t1 (2) At t1, ia reaches the UBL vg1=0 vg4=1T4 onia until t2 (3) At t2, ia reaches the LBL vg1=1 vg4=0T1 onia

* ia

vg1

t1 t2

As a result, the actual current ia will be kept within the upper and lower band limits

65

Q &A

Q: How to adjust the frequency of ia? A: Adjust the frequency of reference current Q: How to adjust the magnitude of ia? A: Adjust the magnitude of reference current Q: What if the band width is reduces? A: ia will follow reference current more closely. But switching frequency

66

Summary

If reference current is sine wave, actual current is also sine wave on which some high order harmonics are superimposed. High order harmonics can be filtered out easily. No low order harmonics. Inverter output current can be accurately controlled.

67

Implementation

R2

R6

R1

* a

ia R5

R3

R4

ia

vg 4

v g1

R1 = R2 = R3 = R4 = R

Band Width 2

Band Width 2

68

Summary

Voltage source inverter, Topologies

Single-phase inverters

Half-bridge inverter Full-bridge (H-Bridge) inverter

Three-phase inverters

Gating patterns

Square wave operation Pulse width modulation (PWM) Selected harmonic elimination (SHE) Delta modulation

Harmonics

Fourier series Harmonic components, table 8-1 and 8-2 Dominant harmonic component

Waveforms

Gate signals Voltage waveforms

Signal generation

Analog circuit Digital circuit Microprocessor

69

- The Study of PWM Methods in Permanent Magnet Brushless DC Motor Speed Control SystemUploaded byJesse Simmons
- PE Lesson PlanUploaded bymadhuee
- 1Uploaded byIrfan Qureshi
- Springer (IJ 6)Uploaded bySherif M. Dabour
- IETE Journal of ResearchUploaded byPradyumn Chaturvedi
- IRJET-Design and Implementation of an Efficient Soft Switching Inverter Fed Ac DriveUploaded byIRJET Journal
- 76292560 Electric Machines and Drives 259Uploaded byAbhably Ablably
- SVPWM Thesis Prepared by DeekshitUploaded bychunduri_rambabu
- Bd 35310316Uploaded byAnonymous 7VPPkWS8O
- Drives Montado Sempai NelUploaded bykvramanan_1
- EE1351-QBUploaded bySaibalaji
- 6. three phase inverter-1.docxUploaded byAdhi
- 17 Chapter 7Uploaded bySherif M. Dabour
- e2173c7e45f85c960cb4bd78acec2d1c.pdfUploaded byLava Kumar
- Mini Project Report 2.pdfUploaded byRahul Kumar
- untitledUploaded bySherif M. Dabour
- 2010_IEEE_ECEUploaded byArun Kumar Yadav
- IRJET-Hybrid Reference Frame Control of AC-DC ConverterUploaded byIRJET Journal
- WEG Vfds vs Soft Starters White Paper Vfdsvssoftstarters Technical Article EnglishUploaded bycartar
- Basic Drive TrainingUploaded byRaj Singh
- T.Y. B.tech E & TCUploaded byAnkit Desai
- Elimination of LowerUploaded byvalentinmuller
- The System Analysis of Solar Inverter Based on Network ControllingUploaded byThai Dang Vu
- 5715ch9Uploaded byPuneet Mittal
- Conext SW E Datasheet ENG deInverterUploaded byNirob Mahmud
- Ee2304 Lab Manual_optUploaded bySree Ganesh
- SEZEN, 2013Uploaded byEdson
- Pwm ReportUploaded bySai Somayajula
- PEES Ind Fce_Specs & DiagramUploaded byRenato Abalos
- AVERIAS RESUELTAS LCD PLASMA TV.docUploaded byByg Byt

- lyapunovUploaded byTruong Nguyen
- ABB Graduate Engineer ProgramUploaded byTruong Nguyen
- The.Gioi.Quy.Do.T7.2012Uploaded byTruong Nguyen
- CHUONG2_TAPLENH_S7300Uploaded bynguyenvanlin115
- PowerFlex700S User ManualUploaded byTruong Nguyen
- Fuzzy Logic Examples Using MatlabUploaded byUdit Upreti
- Ziegler NicholsUploaded byFendi Tajul
- Ky Thuat Do Khoa WEP Cua Mang WiFiUploaded byngotuannghia1
- ABB Graduate Engineer ProgramUploaded byTruong Nguyen
- Application Form_Rev 1006 (3)Uploaded byTruong Nguyen
- InTech-Magnitude Optimum Techniques for Pid ControllersUploaded byTruong Nguyen
- 22.000 từ THI TOEFL,IELTS của Harold Levine (2)Uploaded bychichky
- 22.000 từ THI TOEFL,IELTS của Harold Levine (2)Uploaded bychichky
- Quy trình công nghệ sản xuất bia tại nhà máy bia Cần ThơUploaded byTruong Nguyen
- Your First PLC_VietnameseUploaded byTruong Nguyen
- CV SampleUploaded byTruong Nguyen

- Antenna FundamentalsUploaded byMahmoudYasienMashhour
- Manpack RadioUploaded byBHATARA88
- TT98-124294-F_0945Uploaded byJ_C83
- AN018 Improving ADC RESUploaded byRicardo Alonso Muñoz Canales
- Chapter 9 the Wireless RevolutionUploaded byAshutosh Mentally Macintosh
- BSNL JTO Question Paper 4 2014Uploaded byJOSE MATHEW
- AFR Raw CountersUploaded byAnudeep Bhattacharya
- QuestionsUploaded bybits_who_am_i
- MDR-8000_7-8GHz_dsUploaded byEhsan Rohani
- TCI 604STUploaded byqlx4
- 6416ijcseit01.pdfUploaded byijcseitjournal
- ece-vii-dsp-algorithms-architecture-10ec751-notes.pdfUploaded byManoj
- High Impedance SurfaceUploaded bylibiriyaz
- 2.4ghz Dish AntennaUploaded byKenneth David
- BLUETOOTH® CD Receiver SONYUploaded byAlfonso Calderon
- 40GHz Wide-Locking-Range Regenerative Frequency Divider and Low-Phase-Noise Balanced VCO in 0p18μm CMOSUploaded byMohamed Mostafa
- 2014.10.14-LTE Security II-NAS and AS Security (En).pdfUploaded bydelafinca55
- Doc8-LTE Workshop TUN Session7 Air Link SetupUploaded byto_prasad771855
- Energy Efficient Data Transmission Schemes in Wireless Sensor NetworksUploaded byIRJIE
- Fast Fourier TransformUploaded byHenry Koehler
- HSUPA(5)-Principles of HSUPA Link Budget and Network Estimation-20070329-A-1.0Uploaded bywatever22
- ECE Syllabus(Total)Uploaded byশেখ আরিফুল ইসলাম
- EPS ArchitectureUploaded byLokesh Kumar
- Design 4 ReportUploaded bymuteey
- MicrowavesUploaded byManoj Rawat
- Ts590sg Rtl Sdr Omnirig Logger32Uploaded byanderm8
- LANUploaded bysaranyathilaga026
- Steganography is the Art of Hiding the Fact That Communication is Taking PlaceUploaded byShubha Bharill
- Huawei GPON Basic Knowledge Training DataUploaded byMarko Maljkovic
- Radar EssentialsUploaded byRandy Keith