Fault Isolation and Diagnosis Techniques for Mixed-Signal Circuits

A Thesis Presented to The Academic Faculty By Sasikumar Cherubal

In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy in Electrical and Computer Engineering

School of Electrical and Computer Engineering Georgia Institute of Technology April 2002 Copyright 2002 by Sasikumar Cherubal

Fault Isolation and Diagnosis Techniques for Mixed-Signal Circuits

Approved:

~~\

Dr. Abhijit Chatterje$ Chairman

Dr. David E. Schimmel

. /7
Dr. 0o\? Laskar Dr./Ze/freTA. bav^T

T-

Dr. Umaki shore Ramachandran

Date Approved

L^lo- aoo^

Acknowledgments
I would like to express my deepest gratitude to Professor Abhijit Chatterjee for being the advisor to my research. His constant support, passionate enthusiasm and motivating guidance have been invaluable during the course of my doctoral studies. His knowledge and insight in a wide variety of subjects, as well as his philosophies on research and life, have helped me become a better researcher. Thanks are also due to Professors David E. Schimmel, Joy Laskar, Jeffrey A. Davis and Umakishore Ramachandran for serving on my dissertation committee. Their insightful suggestions and have led to a number of improvements in this research. I am also indebted to all the professors at Georgia Tech and Indian Institute of Technology, Chennai, who have taught me everything I know in the field of Electrical and Computer Engineering. I would also like to thank Nash Khouzam of National Semiconductor for giving me the opportunity to interact with the best minds in this field of research. My friends have always been there to support me through all the good and the hard times. I would like to thank all my office mates: Pramod, Pankaj, Junwei, Rajesh, Ramki, Alfred, Xiangdong and Andy. A special thanks is due to Pramod who helped me with admission into the graduate school at Georgia Tech, and became my mentor during my time here. My friends from my previous schools, Ajay, Srikrishna and Damu have provided much-needed encouragement and support over the last few years. I would also like

to thank my ex-roommates Ramana Rao, Vijay and Ramanarayanan for being the best roomies in town. Above all, the encouragement and support of my family have made the pursuit of my Ph.D possible. My parents and my elder brother Ravi, who would be very proud today, have always been there for me in every walk of my life.

ii

Table of Contents
ACKNOWLEDGMENTS TABLE OF CONTENTS LIST OF FIGURES LIST OF TABLES SUMMARY ACRONYMS AND VARIABLE NAMES I. INTRODUCTION 1.1 1.2 Motivation State-of-the-Art in Test and Diagnosis of Mixed-Signal Circuits
1.2.1 1.2.2 1.2.3 Production Testing of Analog and Mixed-Signal Circuits Fault Isolation and Diagnosis in Analog and Mixed-Signal Circuits Yield Analysis and Yield Management for lCs

. , ,.

I Ill IX XIV XV XVI 1 1 3

3 3 5

1.3 1.4 1.5

Limitations of Current Diagnosis Methodologies Contributions of Dissertation Dissertation Overview.

5 7 8 10 10 11 13
13

II. PARAMETRIC FAULT DIAGNOSIS FOR ANALOG CIRCUITS 2.1 2.2 2.3 Previous Work Overview Robust Diagnosability Conditions for Analog Circuits
2.3.1 Classical Diagnosability Analysis

iii

2.3.2 2.3.3

Diagnosability Analysis Ambiguity Groups and Diagnosability

15 19

2.4

Measurement Selection for Diagnosis

2.4.1 2.4.2 Node and Signal Selection Augmenting the Measurement Set

20
22 24

2.5 2.6

Regression Model Construction... Diagnosis Procedure

2.6.1 2.6.2 2.6.3 Dependent Input Variables Convergence of N-R On-line Computation Requirements

25 26
27 28 30

2.7

Results
2.7.1 On-line Computational Requirements

30
34

2.8

Summary

34

III. AUTOMATIC TEST GENERATION FOR DIAGNOSIS IN ANALOG CIRCUITS 3.1 3.2 3.3 Previous Work Overview Comparing Tests for Diagnostic Ability
3.3.1 Test Cost Description...

35 35 37 39
40

3.4 3.5

Genetic Algorithms for Test Optimization Results

3.5.1 Results ITC Test BenchMark Opamp..

41 43
45

iv

3.5.2

Results for a Low-Voltage Power Amplifier

49

3.6

Summary

51 53 53 54
55 56 57 57

IV. PROCESS PARAMETER DIAGNOSIS FOR ANALOG ICS 4.1 4.2 Introduction Semiconductor Manufacturing and Testing
4.2.1 4.2.2 Yield loss in Analog and Mixed-Signal ICs Current Yield Management Methodologies 4.2.2.1 Design for Manufacturability Methods 4.2.2.2 Yield Diagnosis Techniques

4.3 4.4 4.5

Limitations of Current Methods Proposed Approach Semiconductor Process Modeling

4.5.1 4.5.2 Modeling Mismatches Using Independent Variables Finding Significant Device Parameters

59 60 63
65 68

4.6 4.7

Cause-Effect Analysis Results

4.7.1 4.7.2 4.7.3 ITC Benchmark Opamp Power Amplifier Low-Power CMOS Opamp

68 69
70 73 75

4.8

Summary

83

V. OPTIMAL LINEARITY TESTING OF ANALOG-TO-DIGITAL CONVERTERS 85

5.1 5.2

Introduction Review of Techniques for Estimation INL and DNL

5.2.1 5.2.2 5.2.3 Servo-loop Technique for Measuring Linearity Metrics Linearity Estimates Using Histogram Techniques Use of Linear Models in ADC Testing

85 87
88 89 90

5.3 5.4

Overview Improved estimation Linearity

5.4.1 Test Length Selection

92 94
97

5.5

Methodology for Predicting Variance of Measurement Error in CT Estimates ....98

5.5.1 5.5.2 Computation of o ey for Ramp Signal Computation of c^for Sine Wave Input Signal 103 104

5.6 5.7

Practical Considerations Results

5.7.1 5.7.2 5.7.3 5.7.4 5.7.5 Verification of seg Estimates via Simulation Selection of Test Length Test Set-up Hardware Measurements for a Linear ramp input signal Simulation Results for a Sine Wave Input Signal

104 106
106 110 112 113 116

5.8

Summary

117

VI. HIERARCHICAL FAULT ISOLATION FOR ANALOG AND MIXED-SIGNAL BOARDS 6.1 Overview 118 118

vi

6.2

Automated hierarchical circuit partitioning

6.2.1 6.2.2 Hypergraph modeling of CUT and hierarchical partitioning Effects of Loading

121
122 123

6.3 6.4

Regression Model Construction Hierarchical fault Isolation

6.4.1 Tolerance Effects

125 127
128

6.5

Results
6.5.1 6.5.2 6.5.3 6.5.4 State variable Filter Leapfrog Filter PLL based FM demodulator Results for fault isolation

128
129 130 131 131

6.6

Summary

132

VII. FAULT SIMULATION AND FAULT ISOLATION FOR MIXED-SIGNAL ICS USING ERROR WAVEFORMS 7.1 7.2 7.3 7.4 Introduction Overview Fault Models Fault Effect Characterization and Fault Clustering
7.4.1 7.4.2 Fault Syndrome Extraction Using LPC Fault Syndrome Clustering

133 133 137 139 140

140 141

7.5

Case Study
7.5.1 Results

142
144

vii

7.6

Fault Isolation
7.6.1 7.6.2 7.6.3 Effects of Tolerances. Nearest Neighbor Approach Failures in ADC

146
146 147 148

7.7 7.8

Case Study 2: Charge-Pump PLL Summary

149 151 152 153 I I

VIII. CONCLUSIONS AND FUTURE WORK 8.1 Future Work REFERENCES VITAE

viii

List of Figures
Figure 1.1 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6
Figure 2.7

Applications of Diagnosis Overview of fault diagnosis methodology Illustrating the Effect of Measurement Noise State Variable Filter Measurement Selection Methodology Overview of diagnosis procedure Leap-Frog Filter
8-bit Ladder Digital-to-Analog Converter

2 12 14 21 22 27 30
31

Figure 2.8 Figure 3.1 Figure 3.2 Figure 3.3 Figure 3.4 Figure 3.5 Figure 3.6 Figure 3.7

Prototype of Leapfrog filter Overview of Test Generation Methodology Automatic Test Generation Successive Approximation GA MiST Benchmark opamp Test Configuration for CMOS opamp Optimized test and Response for CMOS opamp Comparison of Simulated and Computed Device Parameters for CMOS opamp

32 37 38 44 45 46 46

48 49 50 50

Figure 3.8 Figure 3.9 Figure 3.10

LM386 Low-Voltage Power Amplifier Diagnostic Test Configuration for LM386 Test Stimuli for the LM386

ix

Figure 3.11 Figure 3.12 Figure 4.1 Figure 4.2 Figure 4.3 Figure 4.4 Figure 4.5 Figure 4.6 Figure 4.7 Figure 4.8 Figure 4.9

Response of LM386 to Diagnostic Tests Diagnosis Results for the LM386 Power Amplifier Semiconductor Manufacturing and Test Yield Loss in ICs DfM Methodologies Yield Management Methodologies Model for IC Manufacturing Process Overview of Diagnosis Methodology..... Process Modeling Methodology Simple Sub-circuits to Illustrate the Modeling process

51 52 54 56 57 58 60 61 65 67

Effect of change in Device Parameters on Opamp Performance Parameters

71

Figure 4.10 Figure 4.11 Figure 4.12 Figure 4.13 Figure 4.14 Figure 4.15 Figure 4.16 Figure 4.17 Figure 4.18 Figure 4.19

Cause Effect Analysis of Slew Rate for Opamp Cause Effect Analysis of PSRR for Opamp Cause Effect Analysis of Supply Current for Opamp Cause Effect Analysis of Large Signal Gain for Opamp Normal and Modified Specifications for LM386 Cause-Effect Analysis of Low-Frequency Gain for LM386 Cause-Effect Analysis of High-Frequency Gain for LM386 Cause-Effect Analysis of Supply Current for LM386 Cause-Effect Analysis of THD for LM386 Test Configuration for Opamp

71 72 72 73 74 74 75 75 76 76

Figure 4.20 Figure 4.21 Figure 4.22

Stimuli and Opamp Response for Common-Mode Stimuli Stimuli and Opamp Response for Power Supply Stimuli Stimuli and Opamp Response for Combination of Common-Mode and Differential-Mode Stimuli

77 77

78

Figure 4.23 Figure 4.24 Figure 4.25 Figure 4.26 Figure 4.27 Figure 4.28 Figure 4.29 Figure 4.30 Figure 4.31 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 5.7

Correlation Coefficients Between Simulated and Diagnosed Parameters.78 Specification Distributions for Operational Amplifier Cause-Effect Analysis of CMRR for Low-Power Opamp Cause-Effect Analysis of Vos for Low-Power CMOS Opamp Cause Effect Analysis of PSRR for CMOS Opamp Cause-Effect Analysis of Supply Current for CMOS Opamp Cause-Effect Analysis for Gain for CMOS Opamp Cause-Effect Analysis of Voltage Swing for CMOS Opamp Cause-Effect Analysis of Slew Rate for CMOS Opamp Proposed ADC Test Strategy Model for Computing oey Output of ADC in Response to Linear Ramp Input Errors in Histogram Simulation Model for ADCs Comparison of Theoretical and Simulated a ey for a Ramp Signal 80 81 81 82 82 83 83 84 94 99 100 101 107 107

Comparison of Error in oey for Proposed Approach vs. Earlier Approaches [89] 108

Figure 5.8

Comparison of Theoretical and Simulated cey for a Sine Wave Signal ..108

*:i

Figure 5.9

Comparison of Theoretical and Simulated w.c Geyfor Sine Wave Signal 109

Figure 5.10 Figure 5.11 Figure 5.12 Figure 5.13 Figure 5.14 Figure 5.15 Figure 5.16 Figure 5.17 Figure 5.18 Figure 5.19 Figure 6.1 Figure 6.2 Figure 6.3 Figure 6.4 Figure 6.5 Figure 6.6 Figure 6.7 Figure 6.8 Figure 6.9 Figure 6.10

Variation in cey vs. Test Length for a Ramp Signal Variation in cey\s. Test Length for a Sine Wave Signal Experimental Set-up for ADC Measurements Comparison of Predicted and TRUE INL for a Ramp Input Comparison of Predicted and TRUE DNL for a Ramp Input R.M.S Error in INL and DNL Error in Peak INL and DNL Comparison of Measured and TRUE INL for a Sine Wave Input Comparison of Measured and TRUE DNL for a Sine Wave Input R.M.S and Error in Peak of Estimated INL and DNL Overview of fault isolation technique..... Hierarchical Circuit Partitions A simple Circuit and its hypergraph representation Hypergraph partitioning Example circuits to illustrate the effects of loading..... Methodology for building regression functions Hierarchical Partitions for State Variable filter Hierarchical Partitions for leapfrog filter PLL based FM demodulator Hierarchical Partitions for PLL based FM demodulator
xii

110 Ill 112 113 114 114 115 116 116 117 119 120 122 122 124 126 129 130 131 132

Figure 7.1 Figure 7.2 Figure 7.3 Figure 7.4 Figure 7.5 Figure 7.6

Representation of fault effects using error waveforms Fault Simulation methodology Example circuit (a)Anti-Aliasing Filter (b) A/D converter and (c) Digital Filter (a)Fault-free response of system, (b) FFT of Fault-free response

137 138 142 143 143

Error waveforms for (a) Biq Filter (b) A/D converter and (c) Digital filter.. 144

Figure 7.7 Figure 7.8 Figure 7.9 Figure 7.10 Figure 7.11 Figure 7.12

Fault Syndromes for (a) Biquad filter and (b) A/D Converter Fault syndromes for digital filter

145 145 148 149

Analog/digital partitioning for the A/D converter Charge-pump PLL

Sub-circuits of PLL (a) VCO (b) Charge Pump and (c) Phase Detector. 149 Fault-free output of PLL 150

xiii

List of Tables
Table 0.1 Table 0.2 Table 2.1 Table 2. 2: Table 2. 3: Table 2. 4: Table 2. 5: Table 3.1 Table 3. 2: Table 6.1 Table 7.1 Table 7. 2: Table 7. 3: Table 7. 4: Acronyms Used Variable Naming Conventions in Equations Parameters of the three circuits Accessible Nodes and Test Signals for the three Circuits Nodes and Test Signals Chosen Diagnosis Results CPU time Required for diagnosis Device parameters for CMOS opamp Device parameters of LM386 Results for fault isolation. Results for fault clustering Fault diagnosis using nearest neighbor for example circuit Fault Clustering results for PLL Fault isolation using nearest neighbor for PLL xvi xvi 31 31 32 33 34 45 49 132 146 148 150 151

XIV

Summary
Algorithms for the diagnosis of parametric faults in analog and mixed-signal circuits were proposed. The effects of measurement noise and other inaccuracies that accompany analog measurements, on the accuracy of the diagnosed parameters, was analyzed. A methodology for approximating the relationship between the circuit parameters to be diagnosed and the measurements made on the circuit, using nonlinear regression techniques, was proposed. This results in significant reduction in the computational work required for diagnosis. In cases that complete diagnosis was not possible, a procedure to generate optimized tests to aid diagnosis was proposed. The test generation methodology explicitly accounts for the effects of measurement noise for robust test generation. The algorithms for diagnosis and test generation were applied to the problem of diagnosing the causes of parametric yield loss in analog integrated circuit manufacturing. The algorithms were also applied to reducing the production test time for analog-to-digital converters. To extend the proposed algorithms to larger systems, two heuristic-based approaches were explored. A methodology to model the fault-free behavior of parts of the circuit, to isolate faults, was proposed. Methods to model fault effects in mixed-signal systems using error waveforms were also proposed for isolating faults to either the digital or the analog portion of a mixed-signal circuit. Experimental results to verify the methods are presented and avenues for future research are discussed.

XV

Acronyms and Variable Names

Table 0.1: Acronyms Used
Acronym ADC BIST CMRR CMOS CUT DfM DfT DNL DUT ET FV GA IC INL MARS PI PLL PSRR PWB SAT SBT SoC SVD Built-In-Self-Test Common-Mode-Rejection-Ratio Complimentary Metal Oxide Semiconductor Circuit-Under-Test Design-for-Manufacturability Design-for-TestabiJity Differential Non-linearity Device-Under-Test Electrical Test Fault Verification Genetic Algorithm Integrated Circuit Integral Non-linearity Multivariate Adaptive Regression Spline Parameter Identification Phase-Locked Loop Power-Supply-Rejection-Ratio Printed Wiring Board Simulation-After-Test Simulation-Before-Test System-on-Chip Singular Value Decomposition Expansion Analog-to-Digital Converter

Table 0.2: Variable Naming Conventions in Equations

Naming Convention Meaning

Italics (a, b) Italics, bold, over-line {a, b) Bold (A, B)

Scalar Vector Matrix

xv i

CHAPTER I INTRODUCTION

Electronic systems with computational, multi-media and communication capabilities are driving today's consumer electronics market. These systems require both digital and
analog functionality. Shrinking device geometries and advances in design methodologies

have made possible the integration of whole systems, once manufactured as discrete components, onto a single chip. These mixed-signal System-on-Chips (SoCs) enjoy price advantages over systems manufactured using discrete components. The increasing complexity of electronic systems, along with the growing need for tighter quality control, has created significant challenges in testing these systems. A particularly vexing problem is the finding or diagnosing the cause(s) of failure of circuits, as low yields in manufacturing can lead to high cost of manufactured parts.The need for diagnosis algorithms in the design and manufacture of analog and mixed-signal circuits is explained in the next section.

1.1 Motivation
It is often necessary to find the cause of failures in mixed-signal systems for design debug, repair, or to tune the manufacturing process for improving yield. The typical pro-

cess in creating an electronic circuit is shown in Figure 1.1. An electronic circuit undergoes testing during the design-prototype phase and during manufacturing before being shipped, where it is tested to determine whether the circuit meets its performance specifications. Typical performance specifications for an analog or mixed-signal circuit are gain and bandwidth of an amplifier, total harmonic distortion for an Analog to Digital Converter (ADC), etc. During the prototype phase, if the circuit fails to meet its performance specifications, it is necessary to find the causes of failure in order to change the design or the prototype, to ensure correct operation of the circuit. During manufacturing test, if the causes of failure of a product can be easily found, the information can be used for repair, or to tune the design or the manufacturing process in order to improve yield.
^>

Design

Prototype

Test

Manufacture

r
cd

Test

a Change Design Diagnose

Tune Design Figure 1.1 Applications of Diagnosis

Tune Process Diagnose

The remainder of this chapter is organized as follows. The state-of-the-art in test and diagnosis of analog and mixed-signal circuits is presented in Section 1.2. The limitations of current approaches are explained in Section 1.3. A summary of the contributions of the research described in this thesis is presented in Section 1.4. An overview of the remainder of this thesis is presented in Section 1.5.

1.2 State-of-the-Art in Test and Diagnosis of Mixed-Signal Circuits

In this section, the state-of the art in analog and mixed-signal test and diagnosis is described. In Section 1.2.1, the production testing of analog and mixed-signal circuits is examined. In Section 1.2.2, the techniques used for diagnosis of analog and mixed-signal circuits, proposed in the literature, are discussed. In Section 1.2.3, an important application of diagnosis, i.e. methodologies for diagnosing the cause of yield loss in semiconductor Integrated Circuits (ICs), is described in detail.

1.2.1 Production Testing of Analog and Mixed-Signal Circuits

Every analog/mixed-signal electronic system is defined by a set of performance parameters, such as gain and bandwidth of an amplifier. These performance parameters are defined by (i) customer requirements, (ii) product differentiation needs and/or (iii) requirements for standard compliance. During production testing of these systems, these performance parameters are measured (fully or partially) and tested against defined limits, called specifications. This process is known as specification testing.

1.2.2 Fault Isolation and Diagnosis in Analog and Mixed-Signal Circuits Fault isolation and diagnosis techniques are concerned with the problem of finding the cause of failure of an electronic circuit. Fault isolation is defined as the process of finding a failed part in an electronic circuit, while fault diagnosis is defined as the process of finding the values of failed parameters or the root cause(s) of failures. Failures in analog and mixed-signal circuits can been classified into two: (i) catastrophic faults and (ii) parametric faults. Catastrophic faults cause complete loss of functionality of the circuit. Cata-

strophic faults are often described in terms of open-circuit or short-circuit failures. Parametric faults cause a degradation in the performance of the circuit. The performance of a circuit is controlled by a set of circuit parameters, such as values of resistors and capacitors in a discrete circuit, or a set of process parameters for an IC. Parametric faults are represented by the variations in these circuit parameters. Fault isolation and diagnosis for analog circuits have been investigated extensively in the past. Bandler and Salama [1-2] and R. W. Liu [3-4] have given a review of the early work on fault isolation and diagnosis for analog circuits. Existing approaches to fault isolation and diagnosis can be divided into two classes- (i) Simulation Before Test (SBT) and (ii) Simulation After Test (SAT). SBT [21-28] approaches are based on the principle of building a fault dictionary'-i.e. a list of all possible faulty behaviors of the circuit. The behavior of the Circuit-Under-Test (CUT) is compared against a catalog of faulty responses of the CUT, stored in the fault dictionary. The fault condition whose response matches most closely with the observed response is picked as the diagnosed fault. SBT techniques classify discrete faults and usually perform fault isolation, i.e. they identify the failed part of the circuit.

SAT techniques perform circuit simulations after obtaining measurements from the CUT, for fault isolation and diagnosis. SAT techniques are further classified into Parameter Identification (PI) techniques and Fault Verification (FV) techniques. PI techniques [516] explicitly solve for the values of internal parameters of the CUT from a set of measurements on the CUT using on-line circuit simulations. PI techniques are able to diagnose faults caused by the variation in multiple circuit parameters, since they solve for all the

parameters of the CUT. PI techniques identify all the parameter values of the CUT, i.e they perform fault diagnosis. FV techniques [17-20] check constraints (Kirchoff's current and voltage law, for example) that must be satisfied by the fault-free circuit to isolate faults. FV techniques identify faulty parts of the CUT, i.e they perform fault isolation.

1.2.3 Yield Analysis and Yield Management for ICs

Semiconductor IC manufacturing is one of the most important areas in the electronics industry. The increasing requirements of quality control and intense price pressures have fuelled a large amount of research on the problem of achieving and maintaining high yields in the manufacture of ICs. Yield is defined as the ratio of the number of functional ICs to the total number of ICs manufactured. ICs are manufactured in semiconductor wafers which contain hundreds or even thousands of ICs. These wafers contain special test sites which are used to monitor the parameters of the manufacturing process (Electrical Test or ET parameters). Yield analysis and management tools [34-46] try to improve yield by relating the parameters measured on these test sites to the yield obtained on the wafer using advanced statistical techniques.

1.3 Limitations of Current Diagnosis Methodologies

Currently, ICs are tested for their functionality by measuring their performance parameters, as described in Section 1.2.1. The chief limitations of current methodologies for test and diagnosis of analog and mixed-signal circuits are: 1. Specification tests are expensive in terms of test time and test equipment. This has caused the test costs of mixed-signal circuits to become increasingly large in proportion

to the of the total manufacturing cost of these circuits. Also, specification testing does not give information about the cause of failure of the circuit being tested. 2. There exist no techniques to automatically generate optimized tests to aid diagnosis. Most fault isolation and diagnosis tools assume that a set of measurements to be made on the CUT are known. Chakrabarti and Chatterjee [93-94] have presented a method to automatically generate tests for distinguishing the effects of faults caused by the variation in a single circuit parameter, but the problem of generating tests for fault diagnosis for faults caused by multiple parameter variations remains unsolved. 3. There exist no systematic methodology to separate failures caused by faults in the analog and digital portions of a mixed-signal IC. Most techniques available concentrate on the problems of isolating faults in either analog or digital systems. The problem of mixed-signal fault isolation is becoming increasingly important with increasing fractions of electronic systems having mixed-signal content. 4. Current yield management methodologies concentrate on correlating yield loss with ET measurements. However, ET measurements do not give complete information about the causes of yield loss. Often, yield loss is caused by the interaction between many process parameters, resulting in the yield loss being uncorrected with any particular ET measurement. Also, estimating correlations between yield loss and ET measurements requires data from a large number of wafers. This implies that a large number of low-yield wafers have to be processed before the cause of failures can be diagnosed and corrective action attempted.

1.4 Contributions of Dissertation

The contributions of the proposed research in the areas of test and diagnosis of analog and mixed signal systems are summarized below: 1. A methodology has been developed to identify the values of parameters that control a circuit performance, from measurements made on the circuit, in the presence of measurement noise. Conditions to be met by a set of measurements made on the CUT, for the accurate computation of circuit parameters, are derived. 2. A technique to automatically optimize test stimuli for analog circuits, in order to facilitate the diagnosis of parameter values, has been developed. The methodology uses stochastic optimization techniques to search large, multidimensional waveform spaces to obtain optimal tests to aid fault diagnosis. 3. The diagnosis techniques developed in this thesis have been applied to the problem of diagnosing causes of yield loss in analog and mixed-signal ICs. The application of these methodologies will result in faster yield ramps for analog and mixed-signal ICs, resulting in faster time-to-volume production. It can also be applied to improve manufacturing yields in mixed-signal ICs currently in production. 4. The diagnosis methodology has been applied to the test time reduction for ADCs, resulting in a reduction of one order of magnitude in test time. For example, the application of the technique to a commercial ADC from National Semiconductor Corporation resulted in a test time reduction from 1.1 seconds to 130 milliseconds. 5. A technique for isolating the failed parts in analog and mixed-signal printed-wiring boards (PWBs) has been developed. The method allows for arbitrary, multiple paramet-

ric variations in parts of the circuit being tested and is robust under the tolerances of analog components and measurement noise. 6. Methodologies for fault isolation in mixed-signal circuits have been developed, which enable the extension of the diagnosis techniques to larger systems. These methodologies can be used for rinding whether the analog or the digital part of the CUT is faulty, prior to applying specialized techniques for fault isolation or diagnosis for the analog or the digital part of the CUT.

1.5 Dissertation Overview

The primary objective of this research is to find comprehensive diagnosis methodologies for analog and mixed-signal circuits. The methods presented in this dissertation are focused on the problem of diagnosing faults caused by multiple parameter variations in analog and mixed-signal circuits. In Chapter II, the mathematical foundations of the proposed diagnosis methodology are presented. Conditions for the diagnosability of an analog circuit, in the presence of measurement noise, are derived and the effects of measurement noise and modeling accuracy on the accuracy values of diagnosed circuit parameters is computed. In many analog ICs the set of performance specification tests area not sufficient to accurately diagnose the parameters of the circuit. In Chapter III, the methodology for generation of optimized tests to aid diagnosis is presented. Again, the technique presented emphasizes robust fault diagnosis in the presence of measurement noise and other impairments that accompany analog measurements.

In Chapter IV, the diagnosis methodologies are applied to the problem of diagnosing the causes of parametric yield loss in analog ICs. A method to compute the contributions of each process parameter to the variation in performance parameters of analog ICs in the presence of changes in process statistics, is presented. In Chapter V, the diagnosis methodology is applied to the linearity testing of ADCs. The methodology is shown to be superior to currently available techniques and has been verified using hardware measurements on a commercially available IC. Extension of the diagnosis methodology to analog and mixed-signal boards is presented in Chapter VI. A method to isolate the faulty pars of a Printed-Wiring-Board (PWB) using steady-state voltage measurements on the internal nodes of the CUT, is presented. A fault isolation technique, that determines whether the digital or the analog portion of a mixed-signal circuit is faulty, is discussed in Chapter VII. Finally, Chapter VIII presents conclusions and recommends avenues for future research.

CHAPTER II PARAMETRIC FAULT DIAGNOSIS FOR ANALOG CIRCUITS

In this chapter, the conditions for diagnosability of a circuit parameters from a set of measurements made on the circuit are derived and a fault diagnosis algorithm for parametric faults in analog circuits is described.

2.1 Previous Work

As noted in Section 1.2.2, diagnosis methodologies, proposed in the literature can be classified into Simulation-Before-Test (SBT) and Simulation-After-Test (SAT) methodologies. SBT techniques [21-27] use pattern matching algorithms to classify faults into one of the fault classes stored in a. fault dictionary (a list of all classes of faulty behavior, created through simulation). These techniques have been applied mainly to discrete, catastrophic faults. Chatterjee et. al [26-28] have developed an SBT approach for parametric faults using a fault sampling approach, but the technique is limited to parametric failures caused by single parameter variations. Parameter identification (PI) [5-16] techniques have been used for the diagnosis of multiple parameter failures in analog circuits. However, PI techniques simulate the Circuit-Under-Test CUT repeatedly, after obtaining mea-

10

surements from it, for fault diagnosis. This computational complexity has limited the application of PI techniques to linear circuits and small, non-linear circuits. Another important limitation of the methods proposed in the literature is that the effect of measurement noise, which can lead to errors in the diagnosed circuit parameters, is not considered in the diagnosis process.

2.2 Overview
As noted in Section 2.1, the major obstacle in the extension of PI techniques to large analog circuits is the need to perform circuit simulations based on measurement data. It is proposed to build a nonlinear regression model to approximate the functional relationship between parameters of the CUT and measurements made on it, which is denoted by fpm(P) -The regression model is given by

fPm(P) = m

pemap

me<Rnm

(2.1)

where np is the number of parameters of the CUT and nm is the number of measurements. This regression model is constructed using prior circuit simulation. A nonlinear regression tool -Multivariate Adaptive Regression Splines (MARS)[128] is used to generate the regression model. Given a set of measurements from the CUT, a set of parameter values, /?*, that satisfies (2.2) are solved for.

fpm(P*)

- mc

(2.2)

where mc is the set of measurements obtained from the CUT. This is a set of nonlinear equations in several variables and is solved using iterative techniques similar to NewtonRaphson's algorithm [130].
n

The proposed methodology can be seen as a 'Pi-like' technique in which time consuming circuit simulation has been replaced by a simple evaluation of the regression model. This means that the proposed technique can be used to diagnose large analog circuits where simulation complexity makes conventional PI methods difficult to apply. Since all the circuit parameters are solved for, in the proposed methodology, faults caused by variation in multiple circuit parameters can be diagnosed. Also, like PI techniques, The proposed methodology is immune to fault masking due to tolerances of analog parameters. An overview of the proposed methodology is shown in Figure 2.1. Given (i) a netlist of Off-line Computations CUT Netlist, Accessible Nodes, Specifications V Select Nodes & Specifications Diagnosis Procedure Circuit-Under-Test

Selected Measurements Regression Models Iterative Soln of

Make Measurements

Regression Models for Selected Measurements

ifpmiP) = c)
Diagnosed Parameter Set

Figure 2.1 Overview of fault diagnosis methodology the CUT (simulation model), (ii) a list of all accessible nodes and (iii) tests to be applied on the CUT, algorithms are proposed to assess the accuracy of the diagnosed parameters in the presence of measurement noise. Then, a set of measurements that minimizes the test time and the number of internal nodes accessed, without compromising diagnostic accuracy, is chosen from the given set of measurements. Then, regression models are built relating the parameters of the CUT to the selected measurements. During test, the selected

i:?.

measurements are made on the CUT and values of the parameters of the CUT are computed that satisfy (2.2), using iterative numerical techniques. The remainder of this chapter is organized as follows. In Section 2.3, conditions for the parameters of an analog circuit to be diagnosable (i.e. the circuit parameters can be computed accurately from the given set of measurements), in the presence of measurement noise and other modeling impairments, are derived. In Section 2.4, the procedure for selecting a minimal set of measurements while ensuring diagnosability, is presented. In Section 2.5, the procedure for building the non-linear regression model, given in (2.2), is described. The numerical methods used for diagnosis are discussed in detail in Section 2.6 and experimental results are presented in Section 2.7.

2.3 Robust Diagnosability Conditions for Analog Circuits

In the proposed methodology, sensitivity-based heuristics are used to check if the circuit parameters can be accurately computed from the set of measurements for the given circuit. In Section 2.3.1, the classical methods for diagnosability analysis, proposed in the literature are discussed and their limitations are analyzed. In Section 2.3.2, the conditions for the accurate computation of device parameters from measurements made on a circuit, in the presence of measurement noise, are described.

2.3.1 Classical Diagnosability Analysis Classical diagnosability analysis has relied on computing the rank of the sensitivity matrix, that relates the parameters to the changes in measurement values. Visvanathan and

13

Vincentelli [56] have shown that the number of parameters of a circuit that can be uniquely solved for, from a set of measurements made on the circuit is given by

nd = rank(S) where S is the sensitivity matrix given by

(2.3)

dm ] dm{ P\ dp2 Pi dp{ S = dm 2 dm2 P\ dpx dp2 dm dp{

rx P\

Kp">
dm7
'
d

dm^

Pi

Pn

(2.4)

dm dp2
2

dm, ' ' dpnp

Pn,

The rank of a matrix is given by the number of its non-zero singular values. However, the parameters cannot often be computed accurately even though the condition in (2.3) is satisfied, due to the effects of measurement noise and modeling inaccuracies. Each meaA \ """" 7/

: API :
r*=

=*"!

>

(b) Figure 2.2 Illustrating the Effect of Measurement Noise surement made on an analog circuit can be seen as an equation in the multi-dimensional

14

parameter space, which is an (np - 1) dimensional surface in the parameter space. The rows of the sensitivity matrix represent the normals to these surfaces. A rank-deficient sensitivity matrix would result in the normals to the surfaces being linearly dependent. The effect of measurement noise on the accuracy of diagnosed parameters is illustrated for a two dimensional parameter space with two measurements in Figure 2.2(a) and Figure 2.2(b). The two lines represent two measurements made on the CUT and the gray areas around the lines represent an uncertainty in the measurements due to noise. The intervals marked Apj and Ap2 in the two figures represent the uncertainty in diagnosed parameters due to measurement noise. The two sets of measurements illustrated in
Figure 2.2(a) and Figure 2.2(b) satisfy the condition of diagnosability given by (2.3), but

they show widely varying effects on the accuracy of the diagnosed parameters. It is seen that the parameters are diagnosed accurately in the system of Figure 2.2(a), but there can be a large error in the values of diagnosed parameters in Figure 2.2(b), depending on the value of measurement noise. The effect of measurement noise on the accuracy of diagnosed parameters is quantitatively analyzed in Section 2.3.2.

2.3.2 Diagnosability Analysis The effect of measurement noise on the accuracy of diagnosed parameters is analyzed below. The analysis technique relates the standard deviation in the diagnosed parameter values to the standard deviation in measurement noise in each of the measurements. For this purpose, it is found to be more convenient to use a different normalization for the sensitivity matrix than the one given in (2.4). The normalized sensitivity matrix is given by

dml

dml
3/? 2

3m, a p2

5v
mi-

s=
dm, 3Pl

a.

dm 2 dp2 aP 2

^ .

(2.5)

3m, o " 3/>2

3m, V2 " 3 / ^

a,

;th where a Pi represents the standard deviation of the variation in the i parameter/?/.

Let each of the measurements in in be affected by measurement noise em having a vari2

ance of cm. If different measurements have different variances in measurement noise, the measurements can be normalized, so that they all have the same variance in measurement noise. In the presence of noise (2.1) becomes

^0 + Am + em=f(p0

+ Ap)

(2.6)

where m0 and p0 are the nominal values of measurements and parameters respectively. Assuming that the measurement noise and the change in measurements from the nominal are small, the function ftp) can be approximated by a linear function about p0 to get ~f(p0 + Ap) =f(p0) + S ^ . Using the fact that ~m0 =}(p0), (2.7) is obtained.

- Am + e. a,

(2.7)

Here, Ap is the computed (or diagnosed) change in parameters which is different from the true change in parameters, which is denoted by Apt. The effect of measurement noise

16

on the accuracy of the diagnosed parameters can be analyzed using the Singular Value Decomposition (SVD) [126] of S. SVD decomposes a matrix into the product of 3 matrices as

S = U X VT
T T

(2.8)

where U and V are orthonormal matrices (U U = I , V V = I where I is the identity matrix) and X is a diagonal matrix with decreasing positive diagonal elements. Using (2.8) and the orthonormal property of U and V, the following equation is obtained for the diagnosed parameters. & = V X l UT (Am + em) = V S P
T T
l

(Am} + e}m)

(2.9)

where Am' = U Am and e'm = U em. Since U is orthonormal, it can be shown

2

that the variance of e}m is <3m. It can easily be seen that if the diagonal elements of have small values compared to the standard deviation of the measurement noise, the relative Ap- Apt error in the diagnosed parameters ( ) will be large due to the measurement noise P values (e'm) being divided by small numbers. Therefore, the part of the matrices V and X, which cause large errors in diagnosed parameters must be ignored. If the last nn singular values are ignored while computing the diagnosed parameters, the error in the computed parameters will be
kp-Apt _i T Ap,

?*-^
G

= \l.Tl '?m

+V2-\l-^
P

(2.10)

where V] and V2 are the first {np - nn) and the last nn columns of the matrix V, respectively, and Xj is the square, diagonal matrix consisting of the first {np - nn) diagonal elements of the matrix Z. It can be seen from (2.10) that the error in the diagnosed parameters is partly due to measurement noise (V 1 Ej e'm) and partly due to taking an incomplete
T

Aft

inverse of the sensitivity matrix (V 2 V 2 ^=r )

The relative error in diagnosed parameters,

Ap Apt , is denoted by ep. The expected

G

squared error in the i device parameter is computed using

7=1 where a
%

j = np-n+\

is the expected squared error in the i parameter and V^ is t h e / element of

the zth row of V. The fact that E

= I , i.e. the parameter variations are inde-

pendent, has been used in order to derive (2.11). The number of circuit parameters that can be accurately computed, is given by counting the number of parameter values that can be computed with a minimum accuracy level. From (2.11) it can be seen that nw the number of singular values chosen for diagnosing the parameter values should be such that

nn = max(i) s.t. Z. > a w

(2.12)

The condition given in (2.12) is based on differential sensitivity, which is valid only for small changes in parameters. Therefore, it has to be evaluated at every point in the device
18

parameter space (the space spanned by the range of possible variations of parameters) for ensuring diagnosability across the whole space. However, this may prove to be computationally too expensive. Therefore the heuristic of evaluating (2.12) only for the nominal values of parameters and at points at the extremes of the parameter space, has been used to estimate diagnosability. Details of this approach are described in Section 2.4.2.

2.3.3 Ambiguity Groups and Diagnosability

In many cases of circuits with large number of parameters, complete diagnosis is not possible with the set of given measurements. In these cases, it is important to identify the parameters which cannot be diagnosed accurately. This can be done using (2.11), which gives the expected squared error in the diagnosed parameters. It is also important to identify groups of parameters whose values are sensitive to the output variables, but cannot be diagnosed accurately because the sensitivities of the parameters are linearly dependent. Groups of parameters that cannot be uniquely solved for from the given set of measurements, and whose values are dependent, are called ambiguity groups [116-118]. Stenbakken et. al. [116-117] have given the basic definitions of ambiguity groups and an algorithm to compute ambiguity groups. Liu et. al [118] have given an efficient algorithm to compute ambiguity groups, These two approaches have ignored the effects of measurement noise while computing ambiguity groups. The conditions used are: Two parameters Pi andp; are part of the same ambiguity group iff 1. The errors in the diagnosed parameters are greater than a given fraction (e) of the standard deviation of the parameter variations, i.e.

19

2
'i

-.

2 _
^7

(2.13)

This condition verifies that the values ofp^i and/?,cannot be diagnosed accurately. yj 2. The errors in the two parameters have a correlation coefficient above a given threshold (Pm/V;)' 1>e-

E e G

^ p,
'Pi

g p ,>
"Pj

\PUpPmin

( 2 - 14 )

e e,

The correlation coefficient between the two errors give the degree to which the errors in the parameters are related to each other. This is because the error in estimated value of p^ given that the value of p; is known, is given by a
p. = k 2
Pi

2
i

a (1 - p, ,). Substituting
ij

(2.10) in (2.14),

np

"V,;l-

=v - ^ ^ - c r ;2 +. K 2 r ^

Fi..

*= 1

^ A :
Pi Pi

> 2

0 rmil

(2.15)

1 where V\ - is the / row of Vo. It should be 7 \ik n, is the Jc element of the i row of Vi and2/Ko

noted that, if measurement noise is ignored, the expression in (2.15) becomes equivalent to the one derived by Liu et. al. [118].

2.4 Measurement Selection for Diagnosis

Stenbakken and Sounders[119] and Spaandonk and Kevenaar[120], have used matrix decomposition techniques on the sensitivity matrix, to select a subset of performance parameters (such as gain, bandwidth, THD) of the CUT from which all the performance

20

parameters are predicted. In these papers, the aim of measurement selection is prediction of the CUT performance parameters and not fault diagnosis. It is assumed that a list of all possible measurements that can be made on the CUT is given. The objectives of the measurement selection procedure are 1. Minimize the number of nodes accessed during testing and 2. Minimize the test time. To achieve these goals, the testing process is examined. As an example, consider the frequency domain testing of a state variable filter shown in Figure 2.3. Sine-waves of dif-

Figure 2.3 State Variable Filter ferent frequencies are applied to the input and the gains at the different nodes are measured. The set of gains at the different frequencies are the set of measurements on the CUT. Each measurement on the CUT has the following two attributes: (a) a test signal which consists of the state of all inputs to the CUT (in this case, frequency of the input signal) and (b) the node where the measurement is made. Since test signals are applied sequentially to the CUT, test time will be minimized by minimizing the number of test signals. An overview of the measurement selection algorithms is given in Figure 2.4.

::i

Circuit Netlist, Accessible Nodes Compute Sensitivity Matrix at Nominal

i
Choose Nodes & Test Signals

Sensitivity Matrix

Choose points where measurement set is likely to change Critical parameter Values

Check Measurements at Critical Points "^Measurements^^^-^Valid?^-"^ if Yes Set of Nodes, Test Signals

ee

No

Augment Measurement set

Figure 2.4 Measurement Selection Methodology

2.4.1 Node and Signal Selection

It was shown in Section 2.3.2 that the number of parameters that can be diagnosed, from a set of measurements, can be derived from the sensitivity matrix (2.11). This number is used as a measure of the diagnostic information contained in a set of measurements. The aim of the measurement selection algorithm is to select a subset of measurements which has the same diagnostic information as the whole set of measurements. If the number of parameters that can be diagnosed from a sub-set of measurements is the same the number of parameters that can be diagnosed from the whole set of measurements, the subset is defined to have complete diagnostic information. The primary aim is to minimize the number of nodes that have to be accessed during testing. Therefore, it is initially assumed that all the test signals are applied on the CUT

22

and try to find a minimum set of nodes with complete diagnostic information. The following greedy procedure has been used to search for the set of nodes. 1. {Selected Nodes} = < > | , {Selected Measurements, m} = (j). 2. Find node which, if added to the set of selected nodes, will cause a maximum increase in diagnostic information. Let this node be k. 3. Add node k to Selected Nodes. 4. Add all measurements made on node kXom. 5. If m does not have complete diagnostic information, go to step 2, else end. Once a set of nodes has been selected, the number of test signals that have to be applied are minimized, to minimize test time. In order to achieve this, a greedy search similar to the one used for node selection has been used. For each test signal applied, the list of measurements consists of all the measurement(s) of the test signal performed on the selected nodes. Test signals are sequentially added to the set of selected test signals till the set of selected measurements has complete diagnostic information. After signal selection, a minimal set of nodes and test signals for the CUT is obtained. Since these nodes and test signals are selected using the sensitivity matrix computed with the nominal values of the CUT's parameters, these may not give complete diagnostic information at other points in the parameter space. Therefore, the set of measurements must be checked at points of the parameter space where the relationship between parameters and measurements is likely to have changed.

23

2.4.2 Augmenting the Measurement Set The relationship between parameters and measurements can change under fault. For example, the output of an opamp can saturate or a transistor can be in "cut off due to parametric faults, making measurements made on the circuit insensitive to parameter variations in the circuit. Such change of behavior is most likely to occur when the measurements take extreme values. Therefore, the heuristic of identifying points in the parameter space where the selected measurements take extreme values, is used. To find these points, for each selected measurement mt, two sets of parameters Ui = [uj, u2, .., Uj,.., un] andX/ = [lh l2, .., lj, .., ln] are computed. The parameters Uj and lj are given by

Uj = Pj+sgn(S^)-APj lj = Pj-smi^pApj

(2.16) (2.17)

respectively, pj is the nominal value of the j parameter and A/?.- is the maximum expected deviation in the parameter pj, is the sensitivity of mi to pj. The measurement mt is taken to its upper extreme value by the parameter set by the parameter set Uj and it is taken to the lower extreme value by the parameter set Lj. A set of points P = [U\, U2,.. , U^ L\, L^ L]J is computed, where the selected measurements take extreme values. At each of the points in P, the sensitivity of all the measurements is recomputed. Now, it is checked if the set of selected measurements is a set having complete diagnostic information. If not, additional nodes/signals are selected using the algorithms described in Section 2.4.1, till the set of selected measurements has complete diagnostic information.

24

2.5 Regression Model Construction

Once the measurements to be made on the CUT are identified, a regression model is built relating the parameters of the CUT to the selected measurements. The regression model is built from a set of training data generated through simulation of the CUT. Instances of the CUT are generated by randomly varying the parameters of the CUT according to the fault statistics given. If no information is known about the specific kinds of faults that can occur, uniform, independent distribution of the different parameters is assumed. The Cadence circuit simulator, Spectre, was used for circuit simulations. To extract measurements from the simulation data the Cadence waveform processing tool, Artil, was used. A nonlinear regression tool, MARS [128], has been used to generate the regression model from the simulation data. MARS has been used to model the measurements made on analog circuits with applications to statistical fault simulation [140], test generation [139] and fault diagnosis [14]. The tool is able to model highly nonlinear functions of large number of input variables. The regression tool is adaptive, in the sense that the order of the regression model adapts to the non-linearity of the function being captured. The regression model constructed consists of piece-wise polynomial functions of the form

y-= J^afifit)
= l

(2.18)

where Bm(x) are spline functions of a set of parameters x. The functions Bt(x) are of the form

25

where x^* is one of the input variables in x chosen for the basis function, tjj is the

break-point for the basis function, s^ takes values of 1 and [x]+= \ x x > . A more l 0 x<0 detailed description of the tool can be found in the original paper by Friedman [128].

2.6 Diagnosis Procedure

The proposed methodology solves for the values of circuit parameters using a modified Newton-Raphson (N-R) [130] method. For the system of nonlinear equations f pm(p)
=

tnc , an iteration step of the N-R algorithm is given by

Pk+1 ~Pk

= J

W*

(fpm(Pk) ~ mc)

(2.20)

where mc are the measurements obtained from the CUT and JQfy) is the Jacobian matrix of ~fpm{p) at/?^. Here, the Jacobian is the sensitivity matrix given in (2.4). Instead of the exact sensitivity matrix, an approximate sensitivity matrix is computed by varying each parameter by a small amount 6 and computing the difference in ~fpm(p) . An overview of the diagnosis procedure is given in Figure 2.5. There are several issues involved in diagnosis using N-R iterations. They are 1. The set of measurements may not uniquely identify the parameters of the CUT 2. Convergence: N-R is only locally convergent- i.e. the iterations converge to a solution only if the starting guess is close to the solution

26

Measurements from CUT m^

MARS regression Models

=^-

-s&=

Coarse Search for Solution

Poy<
Compute Sensitivity Matrix at p

I
Find and Eliminate Ambiguity Groups

T
Update Guess (Equation 2.21) No

Vpm&k*-^ <thresh yes Diagnosed Parameter^ Ambiguity Groups

Figure 2.5 Overview of diagnosis procedure These issues are dealt with below

2.6.1 Dependent Input Variables

To solve for the parameters of the CUT, the sensitivity matrix has to be inverted in each iteration. Dependent or approximately dependent variables can cause the sensitivity matrix to be ill-conditioned, resulting in large errors in diagnosed parameters and nonconvergence of the N-R iterations. Therefore, estimates for pk+
{

-pk

are computed at

each iteration using the mathematics outlined in Section 2.3. The Jacobian matrix is substituted for the sensitivity matrix in the computations. An SVD of the jacobian matrix is computed and the columns of the matrices, U, X, and V are removed as outlined in Section 2.3.2. Then a pseudo-inverse of the Jacobian is computed using

1:7

J V

-Vr^l-U?

(2.21)

where U1? Zj and V] are obtained by removing the columns of U, Z and V corresponding to the singular values in Z that have values less than the standard deviation of the measurement noise. This procedure makes the N-R iterations less sensitive to noise in the measurements obtained from the circuit. The solution for the diagnosis equations will contain ambiguity groups if all the parameters cannot be computed accurately. Therefore, the approach outlined in Section 2.3.3 is used on the Jacobian matrix, to identify ambiguity groups, once a solution to the diagnosis equations has been found.

2.6.2 Convergence of N-R N-R methods can fail to converge if the starting point of the iteration is far from the solution. Therefore, a coarse search procedure is needed to get fairly close to the actual solution. A simple heuristic of varying one parameter at a time till the maximum value of the error (fpm{pj^-fnc) is minimized, is used to get an approximate solution for the

parameter values. These values of parameters are used as the initial value for N-R iterations. Also, damping of the iteration sequence, which is a very common way of improving convergence [130] has been implemented. In a damped N-R iteration, the iteration equation is given by

Pk+\-Pk=

' J'tfftF 1 (fpmiPk) ~ mc)

( 2 - 22 )

where. The starting value for X is 1 and the value is geometrically reduced till the error in the current iteration becomes smaller than the error in the previous iteration.

>S

The detailed procedure for diagnosis is given below.: Notation Pnom ' Nominal Value of parameters pk: parameter estimate in current iteration pk+]'. parameter estimate in next iteration J(pk): Jacobian matrix at pk Ji(pk): /th column of Jacobian matrix <5n\ standard deviation of measurement noise Procedure k<^0,pk<-pnom //compute coarse guess for solution for i <r- 1 : np{ ={x, s.t. max(fpm(pk) - mc) is minimized Vx, p imin < x <pimax} }//end for //begin N-R Iteration while (max(fpm(pk) - mc) < e & k< max iterations) {
Pi

- . , fon<-l:np

, - > , _ , fpm(Pl,-,Pi {Ji(pk) <

+ ^

&,-,Pn)-fpm(Pk), *} 5^ <^ first ns rows

[U, 2, V] <- SVD(J(pk)),

ns <- max(0 s.t ^ > <sn,

Uj <first ns columns ofV, Vj <r~firstns columns of\, and columns of S. A p ^ V ! - ^ //N-R Damping A,<-1
<fo{
1

- ^ . ^ ^ ) - ^ )

Pk+\^Pk

X A

- Pk>&t-l/2 - mc) < max(fpm(pk+ ,) - roc) )//end of Damping

} while (max(fpm{pk) *<-*+l>P*-P*+i } //end of N-R

if(max(fpm(pk) - mc) < ){ compute ambiguity groups, return success } e/se { return failure
>

29

2.6.3 On-line Computation Requirements

The major on-line computation requirements for diagnosis is computing the new guess for the parameters using Equation 2.22. This requires the inversion of an matrix which is 0(n ), where n is the number of parameters. This complexity can become large when n becomes high. It is noted that for many large analog circuits, every measurement is not affected by the variations in every parameter. This makes the sensitivity matrix sparse. Therefore, the computational complexity can be reduced by using a sparse matrix routine for matrix inversion.

2.7 Results
In this section, the proposed methodology is applied to three ITC mixed-signal test benchmark analog circuits [138] and show diagnosis results. The circuit schematics are shown in Figure 2.3, Figure 2.6 and Figure 2.7, The list of parameters for each circuit is
I CZZI3

Figure 2.6 Leap-Frog Filter given in Table 2.1. Since a voltage input signal is being used and only voltages are being measured, the values of individual resistors or capacitors cannot be solved for. Therefore,

3o

Vref
Rend

out

Figure 2.7 8-bit Ladder Digital-to-Analog Converter the parameters of the CUT are resistor ratios and R-C products. The list of all accessible node and test signals for the circuits is given in Table 2. 2. The two linear filters are tested in the frequency domain using sine waves. For the DAC, the list of measurements consists of Integral Non-linearity (INL) for inputs 00000000 to 11111111, voltages at nodes 1 to 7 and the rise-time for a 00000000 > 11111111 transition. Nodes and test signals were chosen using the measurement selection algorithms. The selected nodes and test signals are shown in Table 2. 3.
Table 2.1: Parameters of the three circuits Circuit State Variable Filter Leapfrog Filter 8-bit ladder DAC Parameters (Nominal Values) R2/R1(1), R5/R1(1), 1/R3C2(5000), 1/R4C2(5000), R6/R7(0.428) R2/R1(1), R3/R1(1), R5/R4(l), R13/R4(l), R9/R8(l), R12/R7(l), R10/ Rll(l), 1/R1C1(10000), 1/R6C2(5000), 1/ R7C3(5000), 1/R11 C4( 10000) R10/Rfb(0.5), R20/Rfb(l), Rll/Rfb(0.5), R21/Rfb(l), R12/ Rfb(0.5), R22/ Rfb(l), R13/Rfb(0.5), R23/Rfb(l), R14/ Rfb(0.5), R24/Rfb(l), R15/ Rfb(0.5), R25/Rfb(l), R16/ Rfb(0.5), R26/Rfb(l), R27/Rfb(l),Rend/Rfb(l), (GBW(2.5e6), PM(45), SR(2V/us), Vos(0)) of opamp

Table 2. 2: Accessible Nodes and Test Signals for the three Circuits Circuit State Variable Filter Leapfrog Filter 8-bit ladder DAC
h

Test Signals 400Hz, 800Hz, ..., 4kHz 200Hz, 400Hz, ..., 4kHz !IN(0-255), V(l), V(2), V(3), V(4), V(5), V(6), V(7), Rise-time(0 - 255 )

Accessible Nodes 1, 2, out, 7 4,7, 10, 13, 16, out out, 1,2,3,4,5,6,7

31

Table 2. 3:: Nodes and Test Signals Chosen Circuit State Variable Filter Leapfrog Filter 8-bit ladder DAC Nodes Chosen 1, 2, out 4, 7, 10, 13, 16, out out, 1, 2, 3, 4, 6, 7 Test Signal Chosen 400Hz, 800Hz, 3.6kHz 20GHz, 600Hz, 1400Hz, 2000Hz, 2200Hz, 2400Hz INL for (128, 64, 32, 31, 16, 14, 8, 5, 3) V(l), V(2), V(3), V(4), V(5), V(7), Rise-time (0->255)

Regression models were built for the selected measurements. Prototypes of the circuits

Figure 2.8 Prototype of Leapfrog filter were built to test the diagnosis algorithms. Prototypes of the three circuits were built to test the fault diagnosis algorithms. A photograph of the prototype leapfrog filter is shown in Figure 2.8. Faults were injected into the circuit by varying the circuit parameters. The R-C time constants of the filters were varied by selecting different values for the respective resistors and capacitors. For varying the gain-bandwidth (GBW), slew rate and phase margin of the opamp, an LM346 programmable opamp [143] was used. The GBW and slew rate of this opamp can be varied by varying an external bias resistor. The selected measurements were made on the CUTs. Test signals were generated using an HP33120A signal generator and measurements were made using an HP54645D digital storage oscilloscope. HP54645D has an 8-bit quantizer. This implies an uncertainty of about 0.4% (1/ 256) in the measurements. The diagnosis algorithms were run on the measured data.The
32

parameters of the circuit (values of resistors, capacitors, etc.) were measured using an HP974A 4.5-digit multimeter. The results for diagnosis is shown in Table 2. 4. The average error in the diagnosed parameters for the state variable filter and leapfrog filter are 2.07% and 2.83%, respectively. For the ladder DAC, complete diagnosis was not possible
Table 2. 4: Diagnosis Results Measured values of parameters ^ 1.223, 1.226, 4280, 6079, 0.4049 1.222, 1.226, 7545, 3724, 0.3326 1 1.414, 1.232, 7350, 6063, 0.2703 1.230, 1.225, 1.001, 1.200, 0.8142, 1.225, 0.8119, 11970,7403,6157,10220 1.476, 1.225, 0.6807, 1.200, 0.8142, 1.225, 1.198, 1 11959,7403,6157, 15085 1.000, 0.450, 0.996, 0.450, 0.997, 0.448, 1.000, 0.449, 1.005, 0.450, 0.996, 0.450, 0.997, 0.449, 0.998, 1.002, I.le6,4.05e5, 3e-3 1.131, 0.581, 0.996, 0.450, 1.129, 0.579, 1.000, 0.449, 1.005, 0.450, 0.997, 0.449, 0.996, 0.449, 0.998, 1.002, 2.3e6, 0.937e6, 3e-3 State Variable Filter 1.232, 1.240, 4325., 6113., 0.4172 1.241, 1.24, 7401., 3825, 0.3295 1.393, 1.252, 7678, 6070, 0.2924 Leapfrog Filter 1.226, 1.265, 0.977, 1.176, 0.8193,1.201, 0.7984, 12657, 7458, 6266, 10885 1.412, 1.331,0.6818, 1.168,0.8277, 1.180, 1.187,12728,7301,6050, 14536 1.006, 0.468, 0.4660, 1.039, 0.480, 1.037, 0.490*, 0.984*, 0.410*, 0.931*, 0.515*, 0.894*, 0.581*, L25*, 0.886*, 2.18e6*, 4.74e6, 4.30e-3 1.141, 0.586, 1.029, 0.463, 1.197, 0.590, 1.155, 0.486*, L251*, 0.562*, 1.091*, 0.520*, 1.11*, 0.639*, L25*, 0.7009*, 1.876e6*, 1.079e6, 4.5e3 Diagnosed Values of parameters

8-bit Ladder DAC

from the given set of measurements. The parameters which do not represent unique values are marked by an asterisk (*). The gain-bandwidth and phase margin of the opamp do not affect any of the measurements. Also, the parameters which control the LSBs of the DAC cannot be identified uniquely because of low sensitivity values. It is seen that the methodology is able to accurately solve for parameters of the different circuits for single and multiple faults. Some inaccuracy is found in the diagnosed values for the slew rate of the opamp. This is because a behavioral model was used in simulations for building the regression models, and the behavior of the opamp under large signal input is slightly different from that predicted by the behavioral model. The accuracy of estimation of slew

33

rate can be improved by using a detailed (transistor-level) simulation model for the opamp to construct the regression models.

2.7.1 On-line Computational Requirements

For the three circuits, the average CPU time for diagnosis was computed. Experiments were run on a SUN Ultra-2 workstation. The average CPU time requirements of the three circuits is given in Table 2. 5.The second column shows the CPU time required for diagTable 2. 5: CPU time Required for diagnosis Circuit State Variable Filter Leapfrog Filter 8-bit Ladder DAC Average CPU Time for Diagnosis (sec) ,0.0284 0.252 0.2186 Average # of iterations 1.44 2.3 3.1

nosis, and the third column gives the number of iterations required by the N-R algorithm for convergence. This is the number of times that the inverse of the sensitivity matrix was computed during the diagnosis process.

2.8 Summary
In this chapter the basic framework for diagnosis of analog parameters from measurements made of the circuit was described. The effect of measurement noise on the accuracy of diagnosed parameters was analyzed. An efficient algorithm for diagnosis of multiple parameter faults was described, that can be extended to large circuits with significant simulation times. Measurement results to verify the accuracy and computational efficiency of the algorithms were presented.

34

CHAPTER III AUTOMATIC TEST GENERATION FOR DIAGNOSIS IN ANALOG CIRCUITS

In this chapter, automatic test generation to enable the accurate computation of analog circuit parameters from measurements made on the circuit, is described. The methodology uses a heuristic cost function that takes measurement noise into account, and uses a global search methodology based on genetic optimization, for test generation.

3.1 Previous Work

Complete diagnosis of parameter values is not always possible from performance measurements made on the circuit. This was illustrated in Section 2.7, where the diagnosis was incomplete, in terms of the parameters, for the digital-to-analog converter. Therefore, it is necessary to find new tests to enable complete diagnosis. Some of the early research into automatic test generation for analog circuits, has concentrated on finding tests to separate fault-free circuits from faulty ones. The initial approaches to automatic test generation concentrated on testing for the presence of discrete faults (manufacturing defects) in the CUT. Nagi et. al. [101] presented an algorithm

35

for frequency selection using behavioral modeling and fast fault simulation. B. Kaminska et. al. [91-92] have extended this test generation approach for catastrophic faults and presented a sensitivity-based test generation tool called LIMSoft. Tsai [97] formulated test generation as a quadratic programming problem, trying to maximize the difference between faulty and fault-free responses. G. Devarayanadurg and M. Soma [98-99] have formulated test generation as a min-max optimization problem where the difference between fault-free and faulty circuit responses was maximized under worst-case variations in manufacturing tolerances of analog parameters. The approach was used for the generation of DC, AC and transient test stimuli. These test generation approaches try to test for the presence or absence of manufacturing defects, rather for the circuit performance specifications. In recent years, there have been approaches to generation of stimuli that test a circuit's specifications using alternate tests. These tests are optimized for minimum test time, simpler test set-ups, etc. These approaches related the results of alternate tests to the results of specification tests. Lindermeir et. al [110-112] have used this approach to generate tests that are simpler in terms of test hardware, while P. N. Variyam et. al [106-108] have used alternate test that are much shorter in test time than conventional specification tests. R. Voorakaranam et. al. [109] have used a similar approach, including the effects of measurement noise in the test generation process. K-T Cheng et. al [113] have used simpler tests to allow for the implementation of test hardware on-chip for Built-In-Self-Test (BIST). S. Chakrabarty et. al. [93-94] have presented an approach to test generation that tries to distinguish or diagnose die effect of different faults from the circuit response. The

36

approach is applied to fault isolation for catastrophic faults, or single parametric faults in analog circuits. The authors present an approach for reducing the number of faults to be considered during test generation through a. fault sampling algorithm. In this chapter, an approach to generate tests for analog circuits is presented that is targeted at multiple parametric failures [115]. The approach is based on genetic optimization and the robust diagnosability conditions derived in Section 2.3.

3.2 Overview
An overview of the proposed methodology is shown in Figure 3.1. The process for diagDUT Netlist Parameter Info. Performance Meas Diagnosability Analysis DUT Performance Measurements ^ New Step Automatic lest Generation

Apply Tests

Optimized

Tests Diagnose

Build MARS Models

Diagnosed Parameters

Figure 3.1 Overview of Test Generation Methodology nosis remains the same as what was described in Chapter II. The only new step is the automatic generation of test stimuli to aid diagnosis, if complete diagnosis is not possible from the performance parameter measurements. The newly generated tests are such that, when added to the performance parameter measurements, they enable a greater degree ofdiag-

37

nosis than afforded by performance tests alone. The automatic test generation algorithm searches for an optimal waveform in a defined search space for possible input waveforms to the DUT. An overview of the test generation procedure is shown in Figure 3.2. The

Waveform Parameters

Generate Candidate Waveforms

Specification Sensitivities Process Info

Compute "Test Cost"

Figure 3.2 Automatic Test Generation automatic test generation algorithm consists of two main procedures: 1. A search algorithm, used which is used to generate candidate waveforms in the space of possible waveforms, based on the quality of the current waveforms. This space has large number of dimensions (i.e. a large number of parameters will be needed to specify a complex waveform) and may have many locally optimal points. Therefore, a stochastic search algorithm based on genetic optimization [133] has been chosen to find the optimal test stimuli for diagnosis. 2. A search criteria, which can be used to compare different test stimuli for the ability to diagnose the CUT's parameters. This search criteria is denoted as a test cost. The expected squared errors in diagnosed parameters, in the presence of measurement noise

38

was derived to in Chapter II (2.11). This is used as the basis to derive a test cost to compare the abilities of tests to diagnose parameters. The remainder of this chapter is organized as follows. In Section 3.3, the test cost that is optimized for diagnosis, is described. In Section 3.4, the search algorithms for test optimization, based on Genetic Algorithms (GAs), are described. In Section 3.5, simulation result for two circuits are presented. The chapter is summarized in Section 3.6.

3.3 Comparing Tests for Diagnostic Ability

Any automatic test generation algorithm operates on the basis of a test cost that can be used to compare the goodness of tests during optimization. In Chapter II, it was shown that the expected squared errors in the ith parameter was equal to

./=1

J=

np-nn+\

Taking the sum of the expected squared errors in the parameters,

2 i= 1

Vi /= 1

2 The fact that V is orthonormal, i.e. V VJ. = 1 has been used to simplify the expression.
/= l

Hp

Equation (3.2) is used as a basis to derive a criterion or test cost, to rank the ability of a test to diagnose the parameters of the DUT, as described in Section 3.3.1.

19

3.3.1 Test Cost Description The tests needed are such that, when augmented with the performance measurements, will enable the accurate computation of device parameters. Test cost is computed from the augmented sensitivity matrix, given by

S =

(3.3)

where S^ is the sensitivity matrix of the performance measurements and Sn is the sensitivity matrix of the newly generated test. An SVD is performed on S and the singular values Z; are computed. Equation (3.2) can be used as a test cost for optimization, but it has the following weakness when used as a cost function with genetic optimization: Genetic optimization uses parts of sub-optimal solutions, randomly combined, to form increasingly better solutions. However, (3.2) ignores all singular values less than an. Therefore, the variation in the smaller singular values, which need to be optimized (increased) are ignored by (3.2). Therefore, a modified cost function has been used for test optimization. The test cost is given by

nr

/
y

C = sat
i= 1

v2 > __L

y2

sat(x) = =

x x<\ 1 x>l

(3>4)

where E max is a constant related to the minimum accuracy in computed parameters, i.e. Zmax = am- K, where K is a constant.lt is noted that this cost function is maximized, for optimizing tests. This cost function maximizes the singular values, which has the same

40

effect as minimizing the reciprocals of the singular values. A saturating function sat() is applied to Z,- so that the cost function cannot be dominated by a few large singular values.

3.4 Genetic Algorithms for Test Optimization

GAs are stochastic optimization algorithms which encode a given problem into a genetic strings or chromosomes, and perform operations similar to evolution for optimization. GAs maintain a set of potential solutions to the given problem from which new solutions are created by the genetic operations of selection, crossover and mutation. Using a GA for test generation consists of the following steps 1. The parameters of the test waveform are encoded as a genetic string. Any waveform can be expressed as a function of a few parameters which can be quantized to have only discrete values. For example, for multi-frequency tests, the waveform parameters are the amplitudes and frequencies of the individual sine waves. Assuming 1% accuracy is required for these parameters, each of the parameters can be quantized to 7 bits and the genetic string can be formed by concatenating the strings for each parameter. 2. A set of possible solutions (a population) are generated randomly or chosen according to some specific rule. The test cost is computed for each generated solution or individual in the population. 3. New populations (new generations) are created from the initial population using the genetic operators of selection, crossover and mutation.

41

Selection: In this process the, individuals with a larger cost function have more probability of surviving to the next generation. By the selection process, the average fitness of the population increases with each generation, finally leading to an optimal solution. Crossover: This is a process by which two individuals of a population are combined to create two new individuals or children by swapping the genes to the right of a chosen crossover location (a randomly chosen within a genetic string) of the two individuals undergoing crossover. Mutation: This causes a gene chosen with a certain probability (mutation probability) to be changed to a randomly chosen value. 4. The process of generating continuously improving populations is continued till there is no improvement in the values of the cost function. Then, the member of the population with the best cost function is chosen as the optimal test waveform. The most important step in a GA is the encoding of the problem-specific parameters into a genetic string. In choosing the space of test waveforms, it must be ensured that the waveform has enough degrees of freedom (parameters that can be varied) and that the parameters are computed to a sufficient accuracy, so that an optimal test that enables the accurate computation of all the device parameters. However for a test waveform with nw waveform parameters, each to be determined to an actuary of b bits, the search space (number of possible solutions) for the GA is given by

N=2b'"w

(3.5)

i.e. the search space is exponential in the number and the accuracy of the waveform parameters. An extremely large search space can result in the GA taking a large number of
^2

generations to converge to an optimal solution. Therefore, the approach of Successive Approximation has been used to reduce the search space. In this strategy, the first few most significant bits (MSBs) of the waveform parameters are optimized in the first stage of the optimization and the lower order bits are optimized in subsequent stages with the MSBs set to the optimal settings found in the previous stages. The search space in the case
b n

of a successive approximation GA is reduced to 2

b/bs, where bs is the number of

bits being optimized at a given stage. This results in a much smaller search space for the GA and hence, faster convergence. Setting bs equal to one would result in the smallest search space for the GA. However, this can lead to a sub-optimal solution due to the coarse quantization of the search space. Piece-wise linear (PWL) transient waveforms have been used as the test signals being optimized. PWL waveforms have shown great promise in automatic test generation for replacing performance tests [102-114] and for distinguishing failure modes [93-94]. PWL waveform optimization using successive approximation GA is illustrated in Figure 3.3. The waveform is optimized two bits at a time, which gives four possible values for every voltage point in the PWL waveform. This optimization process is general and can also be applied to other types of waveforms such as multi-frequency tests.

3.5 Results
In this section, the proposed methodology is applied to a CMOS opamp described in the ITC mixed-signal test benchmarks [138], and a low-power audio power amplifier [148]. The diagnosability of device parameters for the circuits were analyzed and tests were generated to aid the computation of device parameters as described in Section 2.3. Regression

43

A i

Genetic string

Optimal Genetic string

First Stage

Second Stage

Figure 3.3 Successive Approximation GA models were built relating the device parameters to the output response of the circuits as described in Section 2.5. 400 circuit simulations were needed to create the regression models for both circuits. In Section 3.5.1, the computation of device parameters from the automatically generated tests and performance measurements for the ITC benchmark opamp is described and in Section 3.5.2, the same steps are described for the LM386 lowvoltage audio power amplifier. This is done by simulating random variations in all device parameters of the opamp for a set of devices, and then attempting to compute the device parameters from the test response.

44

3.5.1 Results ITC Test BenchMark Opamp

The schematic diagrams for the CMOS opamp is shown in Figure 3.4. The process
r-Vrfd

m8

'
m3 ml

m5

m6

inl

m2^|
in2

out
C,

m4

W\r

H
m9

m7
V
s

Figure 3.4 MiST Benchmark opamp

parameter variations for the opamp is shown in Table 3.1. Performance tests for the Table 3.1: Device parameters for CMOS opamp
Parameter xlp xwp
ld

Max 0.3 urn 0.3 urn 0.03um -0.65 V

Min -0.3 ym -0.3nm 0.1|im -1.05 V

Parameter xln xwn ldn Vtn Y n toxn Re

Max 0.3 jim 0.3 jim 0.03|im 0.60 V

Min -0.3 |im -0.3 fim 0.1 um 1.0 V 0.8,/V 275 A 0 1.5kQ

p p

vt

Y p toxp Cc

0.2VV
225 A0 1.1 pF

o.ejv
275 A 0 0.9 pF

OJVV
225 A0 2.5kQ

opamp included offset voltage, slew rate, large signal gain, Common-Mode-RejectionRatio (CMRR) and Power-Supply-Rejection-Ratio (PSRR). Accurate computation of device parameters was not possible from performance tests alone. Alternate tests were generated for the CMOS opamp using the circuit configuration shown in Figure 3.5. This test configuration was first described by R. Pease [149] for the measurement of CMRR of opamps. The optimized tests and nominal circuit response for the CMOS opamp are

45

1(M2

-AA/V
Vinl K \ J

wv ( r \ , )Vin2 ~ - ikQ

10k^

Figure 3.5 Test Configuration for CMOS opamp shown in Figure 3.6. The test response was sampled at a frequency of 100 kHz to form the

0.002

0.004

0.006

O.OOS

0.01

0.002

0.004

0.006

0.008

Figure 3.6 Optimized test and Response for CMOS opamp

alternate test measurements. A measurement noise of 6mV peak-to-peak was assumed for the transient response and that of ImV peak-to-peak for DC measurements. To test the

device parameter computation technique, random circuit instances were generated by varying all the device parameters of the circuit. Measurement noise was simulated by adding Gaussian distributed random numbers to the simulated test responses. Device parameter computation was attempted from the simulated test responses. The comparison of the simulated and computed parameters for the device parameters of the opamp is given in Figure 3.7. The 'true' (simulated) value for each parameter is given by the straight line while the computed values for the device parameters are marked by '+' signs. The device parameter computation algorithm is able to compute all but 4 parameters (Re, ldp, ldn, xwp) accurately. It is seen that the computed parameters track the simulated parameters,
proving the effectiveness of the generated test and the device parameter computation algorithm.

47

u_ 5=1.05 o O
73

J*
+ %

"3

fo.95
O
0.9

+ +$ + $% + 0.95 1 1.05 Simulated Cc (pF) 1.1 - 0 . 2 -0.1 0 0.1 0.2 Simulated xl (um)

-0.2 -0.1 0 0.1 0.2 Simulated xl (um) ^0.9 > 0.8

C

-0.2 - 0 . 1 0 0.1 0.2 Simulated xw (urn)

fP^+
,
f

+ A W ' y+ w

uted

CL

-H

cS0.6
-t*-

ft

w +
0.7 0.8 0.9 Simulated Vt (V) . 1 *
-KjUfcT

+l<$
* & *

0.6

-1 0.8

-0.9 -0.8 -0.7 Simulated Vt (V)

0.6 > ^0c .5 >0.4 "3 0.3 o

>
+*$^%*%- +
+%*& ^ c
* a C D

4 - <& + +
+ +$>*+ +
+

5*-0.6
-th, %dp\ + ?

+J^

+<* + + ++ 0.2 0.3 0.4 .0.5 Simulated y (Vv) 0.6

0.2

0.4 o

z> a.

\#>

+ <r*T+

0*
+

A+ +

*%+

0.3

0.4 0.5 0.6 , 0.7 Simulated y (VV)

o~270 $260 o ^250 a. 240 E O230f

; + ^W y+z*
+
+
+

*-%M% *&Sf+

tr+

$F
+

5.240 E Q 230 230 240 250 260n 270 Simulated tox (A)
Pv '

.&f W.+
230

240 250 260, 270 Simulated tox (A)

Figure 3.7 Comparison of Simulated and Computed Device Parameters for CMOS opamp

48

3.5.2 Results for a Low-Voltage Power Amplifier

A simplified schematic of the bipolar, low-voltage, power amplifier is shown in Figure 3.8. The list of device parameters simulated for the power amplifier is shown in
-eVcc

R1(30K)

R3(15K) )+Input -oVout

R2(1.5K) Input o-t< <

<
CC (30pF) 50K

50K

>

<

Figure 3.8 LM386 Low-Voltage Power Amplifier Table 3.2. The performance parameters of the power amplifier included gain, bandwidth, Table 3. 2: Device parameters of LM386
Parameter Max Min Parameter Max Min

P n "
rbn | Van isn isen iscn P Rl-R3mis

300 220Q 195V 2.5fA 1.5fA 37.5fA 1200Q/D +5%

"100 180H 165 V 7.5fA 0.5fA 12.5fA 8 000/D -5%

Pp
rbp Vap is p isep iscp Rl-R2mis

150" 220^ 75.0V 3.Of A 0.6fA 15fA +5%

50

i8oa
25.0 V l.OfA 0.3fA 5fA -5%

bias current and total harmonic distortion. The test configuration used to generate diagnostic tests for the LM386 is shown in Figure 3.9. The output of the digitizer, as well as the transient current through the power supply (VDD) were digitized at 250 kHz for the

49

VDD

To Digitizer

Figure 3.9 Diagnostic Test Configuration for LM386 diagnostic waveforms. The generated test stimuli for the LM386 are shown in Figure 3.10,

0.4 0.6 Time (msec)

Figure 3.10 Test Stimuli for the LM386 and the response of the LM386 to the test stimuli rae shown in Figure 3.11. The results for parameter diagnosis for the power amplifier are shown in Figure 3.12. Only eight parameters of the LM386 are accurately diagnosable from the generated test. The remaining parameters form ambiguity groups, and therefore cannot be uniquely identified. Again, it

50

0.2

0.4

0.6

0.8

M pV
J
I

I
0.8

V
1

0.2

0.4

0.6

Time (msec)

Figure 3.11 Response of LM386 to Diagnostic Tests is seen that device parameter diagnosis is possible from measurements made on a circuit, with the help of diagnostic tests.

3.6 Summary
In this chapter, an algorithm for automatically generating test stimuli for analog circuits to aid diagnosis, was presented. The algorithm generates test for diagnosis of arbitrary, multiple parameter, faults. Experimental results to demonstrate the efficacy of the algorithms were presented.

51

Simulated p (fi/Square)

Simulated R1-R2 mismatch

-0.05

0 Simulated R1-R3 mismatch

0.05

1.5

2 2.5 Simulated is p (fA)

4 6 Simulated is (fA)

150

200 250 Simulated pn (A/A)

300

Figure 3.12 Diagnosis Results for the LM386 Power Amplifier

52

CHAPTER IV PROCESS PARAMETER DIAGNOSIS FOR ANALOG ICS

In this chapter, the algorithms for test diagnosis and generation, developed in Chapter II and Chapter III respectively, are applied to the problem of yield enhancement for analog ICs. A unique fault modeling methodology and a novel data analysis technique are presented, which enable the accurate diagnosis of the causes of yield loss for complex analog ICs.

4.1 Introduction
The price-pressures of today's competitive markets has made the achievement and maintenance high yields in manufacturing of ICs of paramount importance. Yield is defined as the ratio of the number of functional chips to the total number of chips manufactured. To achieve and maintain high yield in the manufacturing of mixed-signal ICs, it is often necessary to diagnose the causes of yield loss. To understand the difficulty in determining the cause of yield problems, the IC manufacturing and test process is examined in Section 4.2.

53

4.2 Semiconductor Manufacturing and Testing

The semiconductor manufacturing and test process is shown in Figure 4.1. The steps in

IC Fabrication Wafers C Failed WafersProcess Test Pass Wafers Wafer Probe test Pass Die Packaging Packaged Die Final Test Sample ICs QA Failures Alarms

Failed Die

i.
Sample Burn-in Good Die (ICs)

Quality Assurance Test

Figure 4.1 Semiconductor Manufacturing and Test

54

which tests are performed on the ICs is marked in gray. Semiconductor ICs are manufactured in lots of wafers, which contain large (typically thousands) of ICs. Each wafer contains a few sites which have special test structures which enable the measurement of device or process parameters such as resistivity, oxide thickness and threshold voltages (Electrical Test or ET measurements). The ET parameters of each wafer are measured and compared against prescribed limits. The limits on the ET tests are usually set to be very wide, so that a wafer containing some good ICs is not rejected. If the ET parameters are within prescribed limits, specification tests are performed on the ICs in the wafer (Wafer Probe Test). The tests at this stage are limited to DC and low-frequency tests, due to the high capacitance of the probes used. The 'good' ICs (die that pass tests) are diced and

packaged and tested again against a full set of specifications. A sample of the packaged ICs are subjected to burn-in and an exhaustive test of functional test are performed on them.

4.2.1 Yield loss in Analog and Mixed-Signal ICs Yield loss is caused by ICs or wafers failing any of the test steps. Yield loss can be classified into 1. ET failures: This occurs when the ET parameters are out of limits and the whole wafer is deemed to be faulty. These failures can be controlled by better control of the process variables. 2. Random Yield Loss: This is caused by random defects in the manufacturing process, (such as extra or missing metal, oxide pin-holes, etc.) which result in failed ICs.

55

3. Parametric Yield Loss: These are caused by parametric variations or excursions in the manufacturing process. Analog and mixed-signal ICs often face yield problems where

Specifications

Specifications

><
r

-t~i

Performance

o 55

(a)

Performance

Figure 4.2 Yield Loss in ICs

a portion of the ICs on a wafer fail the specification tests, while the ET data is within limits. Two typical yield problems are shown in Figure 4.2(a) and Figure 4.2(b), which show possible histograms of performance parameters of ICs. In Figure 4.2(a) a shift in a process parameter causes yield loss (shaded region) while in Figure 4.2(b) a large variance in a performance parameter causes loss in yield. These yield problems are often caused by the variation of device parameters across a wafer, i.e chip-to-chip variation in device parameters. In this chapter, methodologies to diagnose causes of parametric yield loss are presented.

4.2.2 Current Yield Management Methodologies

Current yield management methodologies can be divided into two: (i) Design-for-Manufacturability techniques that optimize a design for maximum yield under a given set of process parameter variations and (ii) yield diagnosis methodologies that try to find the causes of parametric yield loss.

56

4.2.2.1 Design for Manufacturability Methods Design for Manufacturability (DfM) methods [29-33] can be summarized by the blockdiagram shown in Figure 4.3. The ET measurements obtained from wafers in production Wafers

ET Data

V ^ Extract SPICE Parameters

Statistical (M.C) Simulations Figure 4.3 DfM Methodologies

Yield Optimized Circuit

are used to create statistical distributions for SPICE (circuit simulation model) parameters. These statistical distributions are used to perform Monte Carlo simulations that are more representative of the actual process variations seen in production. These accurate simulations are used for yield optimization and design centering using various optimization methods. It should be noted that these techniques are only used for the design of new ICs, i.e they are not used for yield optimization in existing IC designs. Yield optimization for IC designs in volume production is performed using yield diagnosis techniques, which are described in Section 4.2.2.2.

4.2.2.2 Yield Diagnosis Techniques Current yield management methodologies try to identify causes for yield loss by correlating the yield loss with the measured values of ET parameters. The methodology is summarized in Figure 4.4 [42-48]. The technique uses the following steps to identify causes of yield loss.

57

Multiple Die Analysis

Spatial Analysis

Separate Yield Comps

Statistical Modeling

Yield Improvement Plan Figure 4.4 Yield Management Methodologies 1. The yield loss components are divided into random yield loss and systematic yield loss using multiple die analysis [42J. In this analysis, the yield loss corresponding to group of adjacent die are computed. From this analysis, the portion of yield loss caused by random defects can be estimated, since the random yield loss is proportional to the area of the die 2. A spatial analysis [47-48] of the failed die is performed, to diagnose possible causes of yield loss. The spatial distribution (across a wafer) of certain manufacturing steps are known and matching the pattern of failed ICs to these spatial distributions can be used to identify causes of yield loss. For example, photoresist thickness is known to have a radial variation and any radial pattern in failed ICs can be attributed to the variation in

58

photoresist thickness. The IC failures are also analyzed for periodic patterns in failed ICs, to diagnose other types of failures 3. Once other types of failure have been identified, the causes of parametric yield loss are analyzed by correlation analysis between parametric yield loss and ET measurements. Once the causes of parametric yield loss are identified in terms of ET parameters, the manufacturing process controls are tuned to bring the ET parameters within limits. S. W. Director [34-35] and M. Qu et. al. [36] have proposed techniques for identifying the causes of change in ET measurements in terms of process disturbances.

4.3 Limitations of Current Methods

The following limitations may be pointed out for the current yield management methods 1. Current yield management methodologies rely on ET measurements to diagnose the causes of yield loss. However, ET measurements alone are often inadequate to diagnose the cause of parametric yield loss 2. It takes a large number of wafers to collect sufficient ET data to compute correlations for diagnosis. This results in very slow diagnosis of yield problems leading to significant revenue loss. 3. Current methods are inefficient when trying to diagnose yield variations within a wafer. This is because the ET measurements are available on only a few test sites, and do not provide sufficient data for diagnosis.

59

4.4 Proposed Approach

The device parameter diagnosis problem is defined as follows: Given a set of analog ICs and a set of performance parameters, the tool should infer the cause(s) of any variation in the performance parameters of the ICs in terms of the device parameters. The diagnosis algorithms described in this chapter are based on the model for an IC manufacturing process shown in Figure 4.5 [34]. IC manufacturing processes are affected Circuit Performance Parameters
^
y

THD

Kii
i

J ( vt J . . .

Device

Parameters

^^r~^

<^T>^
Process Disturbances

^aopanf^ / t ) x i d e ^ v / M a s k ^ v difft isivityJ (growth rate! (misalign. \

Figure 4.5 Model for IC Manufacturing Process by a set of process disturbances, which cause the device parameters (threshold voltages, current gains, resistivity, etc.) of every circuit manufactured in the process to be random variables. The device parameters vary from lot-to-lot, from wafer-to-wafer within a lot, between ICs on the same wafer and in between different devices on the same IC (mismatches) [52-53]. These variations in device parameters, in turn, affect the performance parameters of the circuits. Excessive variance or shift in any of the performance parameters of the circuits will lead to parametric yield loss (Figure 4.2).

60

The process of mapping the effects of process disturbances on device parameters has been well studied [34-36, 47-48, 29-30]. However, the relationships between the performance parameters of an IC and the device parameters is different for every design. Therefore, the device parameters that need to be controlled for high yield are different for every design. The problem of diagnosing the variation in IC performance parameters in terns of the variation in device parameters remains largely unexplored. In this chapter, the diagnosis algorithms developed in Chapter II and Chapter III are applied to the problem of diagnosing parametric yield loss in analog ICs.

An overview of the proposed methodology is shown in Figure 4.6. The new steps introPre-test Analysis Circuit JNetllit Specifications Device Params Post-test Processing

'

Diagnosability Analysis Automatic TestGeneration

Measure Response to Optimized Test

Measure Specifications

f
ft

-_>-frCompute (6) Device Params DevicParameters Cause-effect Analysis (^\\

L ]

Function { 4 ) Decomposition

Regression Modelin

TT

Figure 4.6 Overview of Diagnosis Methodology

duced to customize the diagnosis algorithms to the specific problem of diagnosing yield

61

loss in analog ICs, are highlighted in grey. The methodology consists of pre-test and post test portions. The methodology consists of the following steps. 1. A new fault modeling technique is presented that models the effects of process variations in circuit simulations. The modeling technique takes into account the effect of local mismatches in device or process parameters, while ensuring that the process is modeled using only a minimum number of variables. 2. The diagnosability analysis, described in Chapter II, is performed to see if the device parameters can be accurately computed from the set of performance parameter measurements. If this is not possible, optimized test stimuli are generated which allow the unique identification of device parameters. The test generation is performed using methods described in Chapter III. 3. Non-linear regression models are built, which relate the perfomiance parameters and the optimized test response to the underlying device parameters. These regression models are used to solve for the values of device parameters of ICs from their response to the optimized test stimuli. 4. To diagnose yield problems, the contribution of each device parameter to variation in performance of ICs needs to be identified. Therefore, the regression models for the performance parameters (computed in step 3) are decomposed to the individual components pertaining to each device parameter and those due to interaction between parameters.

62

5. During the post-test phase, when there is some yield loss for an IC design, the optimized tests are applied to a set of ICs having yield problems and the response measured. 6. Device parameters for each individual IC is computed from the responses to the optimized test. 7. Using the decomposed regression models from step 4, the effect of each parameter variation on the performance parameters of each IC is analyzed. The remainder of this chapter is organized as follows. In Section 4.5, the process modeling technique used for capturing circuit variation under process disturbances, is described. In Section 4.6, the cause-effect analysis technique used for diagnosing the variation in an ICs performance parameters as a function of device parameters. Simulation results to validate the methodology are presented in Section 4.7.

4.5 Semiconductor Process Modeling

As noted in Section 4.4, the device parameters of an IC vary between different devices in an IC and between different ICs. Previous research [50-55] has concentrated on generating accurate distributions of device parameters for statistical simulations in the presence of mismatches. C. Michael and M. Ismail [54] have shown that the matching properties of devices depend on the sizes of the devices and the distance between then in the IC layout. L. Milor et. al [50-51] have used statistical simulations to remove redundant specification tests for ICs. The general philosophy followed in these techniques is to model a device

62

parameter as the sum of a global mean, an IC-to-IC variation and a local mismatch variation, i.e.

where p; is the global mean for the parameter, Api!C is the variation from IC-to-IC and kPim is the mismatch for the device.

The fact that the process modeling is being used for diagnosis, imposes additional constraints on the modeling process. The properties desirable for the modeling process are 1. Accuracy: The modeling process should represent the actual variation of device parameters. 2. Independent and Non-redundant Variables: Dependent or highly correlated variables will affect the numerical stability of the diagnosis algorithm. Also, the presence of redundant variables will result in additional ambiguity groups (non-uniquely computed parameters) in the diagnosis results. 3. Interpretable: The diagnosed parameters must be easily interpretable in terms of the variation in a model parameter or the mismatch in a parameter within a group of devices in the IC. This constraint helps the use of results obtained from the algorithm for process tuning. Examining the modeling techniques found in the literature w.r.t the constraints given above, it is found that it introduces redundant variables in the modeling process. For example, consider the modeling of mismatch between a matched pair of transistors, Ml and M2 using (4.1). The threshold voltages would be modeled using

64

^Mi = Vt^ + AVtIcm + AVtm

^M2

*VA^/C +

^M2

(4.2)

i.e. two device parameters are represented using three random variables (AVtIC,

AVtMl

and AVtM2). In general, np independent variations would be represented in this methodology using (np + 1 ) random variables. Therefore, the mismatch modeling methodologies presented in the literature have been modified to remove redundant variables as described in Section 4.5.1.

4.5.1 Modeling Mismatches Using Independent Variables The modeling methodology is represented in Figure 4.7. The inputs to the modeling

Designer Input

Find Matched Groups Eigen Value Extraction Simulation Model

Figure 4.7 Process Modeling Methodology process are (i) information on the layout of the IC, which gives data on the distances between devices, and any special matching characteristics, (ii) IC designer input on special structures that enhance or degrade matching and (iii) electrical test data, which gives statistics on the variation and matching of device parameters for the given manufacturing

65

process. Since it is important that the results of the diagnosis algorithm be easily interpretable, the devices in the IC are divided into different matched groups, each consisting of one or more devices (transistors, resistors capacitors, etc.). The model parameters of each matched group of devices forms a group of correlated random variables, with the amount of correlation depending on the average mismatch among the devices. The correlation coefficient between two parameters i andy, whose mismatch is a times the variation in the parameters can be shown to be

HJ

= l ~ auj

(4.3)

Forming the correlation matrix for the set of parameters

Pl,2 Plf
(4.4)

! P%n C = Pl,2 Pt.J l Hn

Pl,nP2.i-

A set of independent variables are formed by using a singular-value decomposition

T

[126] of C as C = U 2 U . The parameters for the matched devices are generated using Ap = D[ap] U JL n (4.5)

where Ap is the variation in parameters from their mean, D[a=] is a diagonal matrix of the standard deviations of the parameters, and n is a set of independent, random variables. Examining the properties of Ap, 1. The variables n are independent and non-redundant.

66

2. The variances and correlations of Ap match the actual distribution of parameters. 3. Since the correlation coefficients are greater than zero (due to (4.3)), the first random variable in n will represent the mean of the all the parameters, and the remaining variables will represent orthogonal mismatches in the parameters. Therefore, the variables n are easily interpretable. This process is illustrated for two simple sub-circuits shown in Figure 4.8, which shows

Ml

M2

0
Ql Q2 Q3
^ ^

0
(a)

(b)

Figure 4.8 Simple Sub-circuits to Illustrate the Modeling process two common sub-circuits that occur in analog circuits, namely differential pairs (Figure 4.8(a)) and current mirrors (Figure 4.8(b)). Only the modeling of one parameter for each sub-circuit is considered, Vt for Figure 4.8(a) and p for Figure 4.8(b). It is assumed that the differential pair mismatch is 2% and the current mirror mismatch is 1%. This results in the following equations for Vt and p.

AVt Ml AVt M2

= a Vt

0.9999 0.0141 0.9999 0.0141

(4.6)

67

AP Q 1 AP Q1
APQ,
Of

0.99997 0.99997 7.071 e

3

-SA64e 4.082e
3

(4.7)

0.99997 -7.07 le" 3 4.082<T3

It is seen that the first random variable (n{) represents the mean (global) variation while the remaining variables represent mismatches.

4.5.2 Finding Significant Device Parameters

The modeling technique described in Section 4.5.1 will result in an extremely large number of variables to represent any IC of non-trivial complexity. Most of the variables introduced have no effect on the performance of the IC, as was shown by L. Milor et. al [50-51]. An approach similar to the one proposed by L. Milor et. al, was used in the this research, for finding the significant variables, i.e. the ones that have significant affect on the performance of the IC. A level 3 experimental plan [129] is used to identify the variables that affect the performance parameters of the IC. The test generation and diagnosis algorithms are then focused on diagnosing these significant device parameters.

4.6 Cause-Effect Analysis

Once the device parameters for each IC has been computed using the algorithms described in Chapter II and Chapter III, a novel analysis methodology is applied to compute the effect of each device parameter on the performance parameters of the circuit. The regression model output of MARS can be decomposed to identity the contributions of different input parameters to the model. This analysis is described as ANOVA (ANalysis Of VAriance) decomposition by Friedman [128]. This analysis is the decomposition

68

applied to a. function, is different from the classical ANOVA analysis in statistics [131]. The ANOVA decomposition resolves fpm(p) into a set of functions in the form

fpm(P) = I / M > + Jfi,j(PiPj) + 1 fij, kiPiPjPk) +

j

(4-8)

ij

i,j, k

where the first sum give the contributions of individual variables, the second sum gives the contributions due to two-variable interaction, and so on. Given a set of diagnosed parameters for a set of ICs, the individual component functions in the ANOVA decomposition ifi,fij, ...)can be evaluated to compute the contribution of each parameter and that of parameter interactions on the variation in IC performance. To compute the effect of a parameter pb the mean and variance offjipf) are estimated using

P,

^I/^/.y)
7=1

<4-9> (4.io)

Kr w^i^P^-m,)2
7=1

respectively, where pi is the computed value ofpt for IC numbery. The mean and variance of effects due to interaction between parameters is estimated in a similar way using

Ar

4.7 Results
In this section, experimental results are presented to validate the effectiveness of the algorithms presented in this chapter. The experimental results are presented for three circuits: (i) the ITC mixed-signal test benchmark opamp described in Chapter III, (ii) the

69

power amplifier described in Chapter III and (iii) a low-power CMOS operational amplifier obtained from industry.

4.7.1 ITC Benchmark Opamp

To study the effectiveness of the cause effect analysis two case studies were performed. In the first case, a monte carlo simulation of the circuit was performed to generate a set of IC instances and performance parameters of these ICs were measured. This was considered the nominal statistical distribution of device performance. Now, in the second case, circuit instances were generated with shifts and increased variances were introduced into all the device parameters to simulate a process shift and poor control of process, respectively. (Note that this is a realistic scenario, as a fluctuation in a process parameter typically affects multiple device parameters). This is considered the new or faulted distribution of device performance. It was found that 4 of the opamp's performance parameters, namely, slew rate (SR), supply current (I sup ), power supply rejection ratio (PSRR) and large signal gain (Av)were affected by this change in device parameter statistics. The histograms of the nonnal and faulted IC performance parameters are shown in Figure 4.9. The cause-effect analysis was performed on the second set of ICs to diagnose the cause(s) of performance shift and increased in variance. The results of cause effect analysis on the normal and faulted ICs is shown in Figure 4.10, Figure 4.11, Figure 4.12 and Figure 4.13. The white bars show the AN OVA analysis performed using simulated (actual) device parameters, while the black bars show the ANOVA analysis performed using diagnosed parameters. The bar-graphs on the left side of Figure 4.10-Figure 4.13 show the relative contributions of various device parameters to the shift in performance

70

n ii ii.au
-1.9 -1.8 -1.7 Supply Current (mA) -1.6 1"6.5 17 17.5 18 18.5 19 Large Signal Gain (V/mV) 19.5

Figure 4.9 Effect of change in Device Parameters on Opamp Performance Parameters

Simula id Diagnosed ^^B Simulated I I Diagnosed

0.35 -

0.3 -

jn A

0.2 o

sT

CD

I iI ll In 1
:>
X

Figure 4.10 Cause Effect Analysis of Slew Rate for Opamp parameters. It can be seen that the shift in slew rate is mainly due to the shifts in the device parameters Vtn, yn and the interaction between toxn and yn. Similar inferences may be made about the shift in supply current. The bar-graphs on the right of Figure 4.107]

^m Simulated I I Diagnosed

Simulated Diagnosed

I I
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2

Figure 4.11 Cause Effect Analysis of PSRR for Opamp

Simulated Dingnosed Simulated Oiagnosod

* ID 4

0.1 - g o'

Figure 4.12 Cause Effect Analysis of Supply Current for Opamp Figure 4.13 show the relative contributions of each device parameter variation to the variance of each performance. For example, it can be seen that the major portion of the variance in slew rate is caused by the variation in the compensating capacitor Cc, the oxide thickness toxn, and the variation in width due to etching xwn. The portion of the bargraphs labelled 'Error' refers to the part of the variation that could not be explained by the variation in any of the parameters considered. It is seen that the technique is able to diagnose a major portion of the cause of shift and variance in circuit performance parameters.
72

u
4 5 6

MI n
7 8 9

10

0.2

"

0.15

Simulated Diagnosed

Simulated Diagnosed

0.1

0.05
2

0.05

-0.1

1 -1
" _

f".

" " _
1 2 3 4

0.15

-o^

-0.2

It f T
5 6 7 8 9

10

Figure 4.13 Cause Effect Analysis of Large Signal Gain for Opamp The technique is able to track variation in performance caused by the interaction between parameters as can be seen from Figure 4.11. The information provided by the cause-effect analysis can be used to provide feedback to process engineers to tune the manufacturing process to improve yield.

4.7.2 Power Amplifier

The diagnosis technique was applied to a simulation model of the LM386 power amplifier described in Chapter III. As described in Section 4.7.1, a Monte Carlo simulation representing the normal statistical behavior of the circuit was performed. Then, shifts and increased variances were introduced into the various device parameters of the circuit. The nominal and modified distributions of specifications for the LM386 are shown inFigure 4.14. The results of device parameter diagnosis for the power amplifier are shown in Figure 4.15-Figure 4.18. It is seen that accurate diagnosis results are obtained for all the performance parameters.

73

70

(0 d)

Nominal Modified

oo

Nominal I I Modified

o 60 c
2 s o
L.

<D so

o
C 80 I - 70 60

3
O 40

o O

JD

30 Q>

O
1.. 30

o
1 20

gio 3
19.3 19.4

19.5

19.6

19.7

19.8

19.9

20

20.1

20.2

I"
Z o
60

Ja

LJ
Nominal I 1 Modified

Low Frequency Gain (V/V)

60

High-Frequency Gain (V/V)

(0
<D 50

! Nominal I I Modified

W (1) O 50

O C
Q) l l 40 I-

c 2
3
L . 40

3 O
30

o
o
.Q 10

O30 "*0 2o
J2

E
3

L
Supply Current (rhA)

gin
3 Z o

In
4 TWb(V/V|

Figure 4.14 Normal and Modified Specifications for LM386

0.6

I M i l Simulated!.. I I I Diaanoseql

o.e

I M l SimulatedlI I I Diaqnoseqi

0.4
~Cu

0.5
E

0.2

<S>

_c

0.2

- r
2

,D

C.4

, ID & I-

g
0.3

0.2

o
UJ
3>

0.4

'
0.1

0.6

I\i
4

m1
6 7

Figure 4.15 Cause-Effect Analysis of Low-Frequency Gain for LM386

74

n H0.6

H Simulated 1 1 1 D i a a n o s e d l_

Simulated Diagnosed

"

0.4

0.2 o 0.2 0.4 0.6 -0.8

t1
"

Figure 4.16 Cause-Effect Analysis of High-Frequency Gain for LM386

I ^ H Simulated I I I D i a g n o s e d |"

r:
"

"fi

I
1

IIIulii
4 5 8 7 8 9

10

0.8

0.6

0.4

T"1
i

0.2 0 0.2
0.4

JL:
5 6 7 8

i i

0.6

0.8

Figure 4.17 Cause-Effect Analysis of Supply Current for LM386

4.7.3 Low-Power C M O S Opamp To study the scalability of the diagnosis methodology, it was applied to a low-power CMOS operational amplifier obtained from industry. The opamp contained 80 CMOS transistors belonging to 5 types and bipolar transistors (substrate pnp), as well as resistors and capacitors. The device parameter variations for this device was modeled using the

75

Simulated Diagnosed

^H 1

Simulated 1 Diagnosed

U S '

(5

il

Figure 4.18 Cause-Effect Analysis of THD for LM386 methodology described in Section 4,5. The process modeling required 269 independent variables. The significant parameters of this model were extracted using methods described in Section 4.5.2. This led to the extraction of 33 device parameters including 17 mismatch parameters, which had significant impact on the device performance. The specifications of the opamp considered included all measured specifications in the opamp data sheet. Optimized test were generated to aid diagnosis as described in Chapter III. The test configuration used for generating the alternate tests is shown in Figure 4.19. The output

lOkGF

-AA/V
UNP) 600Q. A/vV 10k!Q

Figure 4.19 Test Configuration for Opamp

76

voltage and the current through the power supply were the transient measurements made during the diagnostic test application. The opamp was simulated for the common mode response (INP and INM tied together), power supply response, and combination of differential-mode and common-mode response (INP and INM varying independently). The generated test stimuli and the response of the opamp to the test stimuli for the common-mode, power supply and combination of common-mode and differential-mode stimuli are shown in Figure 4.20, Figure 4.21 and Figure 4.22 respectively. To test the ability of the gener-

2 Time (msec)

Figure 4.20 Stimuli and Opamp Response for Common-Mode Stimuli

10

Figure 4.21 Stimuli and Opamp Response for Power Supply Stimuli ated tests to diagnose process parameter variations, process parameter computations, as described in Chapter II and Chapter III was attempted. The results of process parameter
77

kxAAXyA W

. AA^TA ^ A~

A ^ / V . / V \ / " Y \ / \ A A/W " ^ V ^Oc^\^ v^A\Y/v^A{W

INP INM

2 Time (msec)

Figure 4.22 Stimuli and Opamp Response for Combination of CommonMode and Differential-Mode Stimuli computation are shown in Figure 4.23. The figure shows the correlation coefficients

15 20 Parameter Index

35

Figure 4.23 Correlation Coefficients Between Simulated and Diagnosed Parameters between the simulated and diagnosed parameters, for the 33 parameters which had significant effect on the variation of specifications. In the case of perfect diagnosis, all correlation coefficients would be equal to one (diagnosed parameters equal to simulated parameters). It is seen that only 3 of the 33 parameters are diagnosed accurately. The remaining parameters form ambiguity groups, and cannot be computed uniquely. This

78

occurs due to the large number of process parameters for the CMOS opamp, which makes the unique identification of any single parameter difficult. Process disturbances were introduced in the device parameters as described in Section 4.7.1, and diagnosis was attempted. The normal and modified distribution of per-

79

formance parameters for the low-power CMOS opamp are shown in Figure 4.24. It is seen
i 60
CO

Nomina! I Modified

850 c
CD

340 o

n 30
CD

20 10

, n n
'00 -150 -100 -50 0 CMRR (uV/V)

50

1 n'
100 Nominal Modified

150 30

- 2 - 1

0 Offset (mV)

^M 70 860 o

80 c o 70
CD O

Nominal Modified

60 50 O o40 i> f30 ^20 10 n 0.69 120 100 Nominal | ' Modified ! 1

150
O

O40 "6 130

E 2 20

ft
0.7

0.71 0.72 0.73 Bias Current (mA)

1.

10
0.74 0.75 ?00 -150 -100 -50 0 50 +VE Supply PSRR (u.V/V) 100 150

80 e n 70

^M Nominal 1 i Modified

80

h *60
13

O 60
40

ibO

o
3

o40
<a

30 ^20

6.65 6.7 6.75 +VE SWING (V)

n.

12 14 16 Gain Sinking (u,V/V) 30 50

1.
1(

10 20

. ^JL

1,

;4o
O30

10

-1.4

-1.35

-1.3 -1.25 -ve Slew Rate (V/usec)

-1.2

-1.15

Figure 4.24 Specification Distributions for Operational Amplifier

80

that the process disturbances cause changes in the mean and the variance of the performance parameters. The results of process diagnosis for the low-power CMOS opamp are shown in Figure 4.25-Figure 4.31. It is seen that, due to the complexity of the IC and the

s
H
.22 E

s mulated
D agnosed

Simulated Diagnosed

_ Jb

-b Xi

Figure 4.25 Cause-Effect Analysis of CMRR for Low-Power Opamp

Simulated Diagnosed

Figure 4.26 Cause-Effect Analysis of V os for Low-Power CMOS Opamp process description, the diagnosis results are not as accurate as those for the first two examples. The effects of ambiguity groups can easily be seen in the diagnosis results. In Figure 4.25, it can be seen that the effects of mis-matches in substrate doping (nsub) and oxide thickness (tox) of input devices (denoted as inpDevs) form an ambiguity group. It is

81

'
0.4

' " _ 1 ^-

Simulated 1 Dia g n o s e d |

Simulated Diagnosed

0.3

~ _

0.2

0.1 O
0.1

. _ "
" "

in Jb "
" "
s

0.2

Jl

"5 cE

0.3

0.4

Figure 4.27 Cause Effect Analysis of PSRR for CMOS Opamp

Simulated Diagnosed ^ H Simulated 1 1 Diagnosed

JlM
"53

"
a E.
o

II
I o1

| | "1 I ^ H

i i
^n ~*h
e 0

=
s g

Tl

III lilt
1 2 3 4 5 6 7 8

Figure 4.28 Cause-Effect Analysis of Supply Current for CMOS Opamp seen that the effect of oxide thickness mismatch is under-estimated while the effect of substrate doping mismatch is over-estimated. Even though the effect of either parameter is not predicted accurately, the sum square of the parameter effects equals the variance in the performance parameters. Therefore, some conclusions can be drawn about the cause of variation in performance parameter variation. For example, it is seen that the increased variation in CMRR (Figure 4.25) is caused by mismatches in the either the substrate dop-

82

Figure 4.29 Cause-Effect Analysis for Gain for CMOS Opamp

Simulated Diagnosed

-o

fl

Figure 4.30 Cause-Effect Analysis of Voltage Swing for CMOS Opamp ing or the oxide thickness of the input transistors, though the exact parameter mismatch cannot be identified.

4.8 Summary
In this chapter, a methodology for computing the effects of device parameter variations on performance parameter variations of an analog IC, was presented. The methodology was shown to be highly effective in diagnosing the effects of process parameter variations

S 3

Simulated Diagno ^d

__D

ID

Figure 4.31 Cause-Effect Analysis of Slew Rate for CMOS Opamp in ICs of low-to-moderate complexity. The following conclusions may be drawn from the experiment on a highly complex CMOS opamp. 1. As device complexity increases, the contributions of individual components becomes difficult to distinguish, without the aid of access to internal nodes of the DUT. 2. Although die effects of individual parameters is difficult to track, the methodology will be able to track trends in the manufacturing process by observing the changes in parameter effects. 3. For devices of high complexity, such as ADCs, the use of custom circuitry designed to track process variations, can be investigated.

8-

CHAPTER V OPTIMAL LINEARITY TESTING OF ANALOG-TODIGITAL CONVERTERS

To maintain an acceptable level of quality in the production of ADCs the linearity metrics of every ADC has to be measured and checked against performance specification limits. As ADCs continue to improve in resolution, their testing has becoming increasingly demanding in terms of test time. In this chapter, a technique for reducing the test time for ADCs is presented. ADC test is formulated as a diagnosis problem and the accuracy of measurements is improved by explicitly considering the effects of measurement noise. The technique is shown to be significantly better than currently available techniques and can be easily integrated into current production test flows. Experimental results in simulation and on actual hardware are shown to demonstrate the technique

5.1 Introduction
Production testing of ADCs involves measurement of their functional specifications. The measurement of linearity metrics of ADCs takes up a major portion (35-50%) of this test time. The linearity metrics of an ADC, which include integral nonlinearity (INL) and differential nonlinearity (DNL) measure the amount of deviation of the code transition voltages, or CTs (the values of the input voltage at which the output code of the ADC changes) deviate from their ideal values. The measurement of these linearity metrics,

85

therefore, involves the measurement of all 2n-1 CTs of an ADC, where n is the number of bits of the ADC. For every additional bit in the ADC, the number of these measurements increases by a factor of two and the accuracy requirement of each measurement also increases by a factor of two [76-77]. Therefore, the linearity testing of high resolution ADCs can become highly time-consuming, and therefore, expensive. In response to the problem of increasing test times, techniques have been developed that estimate all of the CTs from a subset of CT measurements [82, 119]. These techniques are based on the following two assumptions. For most high resolution ADCs, the number of variables such as the values of resistors and capacitors and transconductances of transistors, which control linearity, is much less than the total number of CTs. Furthermore, the variations in these variables is typically small and the relationship between these variables and the CTs can be well approximated by a linear function, second order or higher order terms being negligible. Capofreddi and Wooley [76-77] have described techniques to use the linear model with three production test methods [83] to save test time. Based on the diagnosis methodologies developed in this thesis, a new analysis methodology for test time reduction for ADCs has been developed. Using this methodology, it was shown that CTs may be estimated with a greater degree of accuracy than that obtained by Capofreddi and Wooley [76-77], for a given test time. In this chapter, a methodology for test time reduction for ADCs, for both ramp and sine wave inputs, is presented. The rest of this chapter is organized as follows. In Section 5.2, the techniques used to measure linearity metrics and the use of linear models to improve the accuracy of linearity estimates [76-82] are reviewed. In Section 5.3, an overview of the proposed methodology

86

is presented. In Section 5.4, the proposed technique for obtaining accurate estimates of linearity metrics, is described. The improvement in accuracy is based on accurately estimating the expected variance of errors in linearity metrics estimated from histograms of ADC outputs, due to device noise and quantization effects. In Section 5.5, an analysis technique to accurately estimate the variances of errors in linearity estimates, obtained from histograms for both ramp and sine wave input waveforms, is presented. In Section 5.6, some of the practical considerations in the implementation of the technique are discussed. Experimental results to validate the performance of the algorithm are given in Section 5.7.

5.2 Review of Techniques for Estimation INL and DNL

In this section, the techniques used to compute CTs, INL and DNL for ADCs [83, 8587] are reviewed. In Section 5.2.1, the servo-loop technique for measuring linearity metrics is presented. In Section 5.2.2, the techniques to measure INL and DNL from a histogram obtained for a linear ramp or sine wave input signal are described. In Section 5.2.3, the techniques that have been proposed to reduce linearity test time using linear models are described. INL and DNL are measures of how much the CTs of an ADC differ from a ideal linear behavior. INL and DNL are defined as follows [125]. DNL is a measure of the deviation from the ideal 1 Least Significant Bit (LSB) of the input voltage span that is associated with each output code. INL is the deviation of an ADC transfer function from the line between the measured end-points (zero andfull scale) of the ADC. INL and DNL are usually expressed in LSBs. INL and DNL can be expressed in terms of the CTs as

87

DNL,- = P Ji-l)-l 1 \ ILSB J Y,-Yi-((V

7JVZ,,. = '
th

(5.1)
V )

] -Y 1 )/(2"-2))-(/-l)

ILSB

(5.2)

where yt is the z' CT, n is the number of bits in the ADC, and ILSB denotes the ideal voltage span of 1 LSB of the ADC. Since INL and DNL can be easily computed with a few algebraic operations once the CTs are known, only the estimation of CTs will be described throughout the rest of this chapter. INL and DNL measurement usually involves the measurement of all the CTs of the ADC. S.Max [85] has described the different techniques that can be used for the measurement of linearity metrics of ADCs. The three techniques that can be used for linearity testing are (i) servo-loop method, (ii) ramp histogram method (tally and weight method) and (iii) sine wave histogram method (code density method).

5.2.1 Servo-loop Technique for Measuring Linearity Metrics

The servo loop method involves the use of an analog integrator in a feedback loop to estimate CTs, one at a time. The feedback loop causes the input to the ADC to be equal to the CT for the target code and this voltage is measured using the digital voltmeter (DVM). Since the feed back loop automatically forces the input to the ADC to be equal to the CT for a target code, the accuracy of this technique does not depend on the accuracy of the tester's Digital-to-Analog Converter (DAC). However, this technique requires a long test time because of the settling time of the integrator and the long conversion time of the DVM. Therefore, the application of this technique is limited to those cases where a digital to analog converter of sufficient accuracy is not available. S. Max [85] has described a fast

variant of the servo-loop method replacing the analog integrator and DAC in the servoloop with a fast and accurate DAC. However, this requires a more complex tester interface board design and a non-standard test interface.

5.2.2 Linearity Estimates Using Histogram Techniques

The linearity testing of most high resolution ADCs is performed using the ramp histogram technique [87], because of its relatively short test time. The sine wave histogram technique has a worst case error in linearity estimates that is K times worse than that of the ramp histogram method. Therefore the sine wave histogram technique is used in cases where generation of an accurate ramp is difficult [86]. It should be noted that the histogram techniques estimate all the CTs in one pass while the servo-loop method measures CTs one at a time. Therefore, the servo-loop can be used to measure a subset of the CTs while the histogram technique cannot be used to do so.

To estimate linearity of ADCs using a histogram technique, a ramp or sine wave signal that spans the entire input range of the ADC is used as input to the ADC and a histogram of the output samples is computed. The deviation of the histogram values from the ideal values (expected values for a perfectly linear ADC) are used to compute the linearity metrics of the Device-Under-Test (DUT). Since the sampling rate of an ADC is fixed for these measurements, the test time required is proportional to the number of output samples of the ADC taken. However, due to the statistical nature of the histogram test, the accuracy of linearity estimates also improves with the number of samples in the histogram. In production test of ADCs, a maximum limit is usually specified for the allowable error in linearity measurements and a minimum test length is chosen that satisfies this criterion.

89

Typically, this maximum allowable error is of the order of 0.1 LSB, and this results in a test length of 100-200 samples for every output code of the ADC. The computations required to derive the linearity metrics from a histogram of ADC output samples for ramp and sine wave input signals have been given by S. Max [83] and J. Doernberg et. al. [86], respectively.

5.2.3 Use of Linear Models in A D C Testing As stated in Section 5.1, the number of variables that control the CTs in most high-resolution ADC architectures is much less than the number of CTs. The CTs can therefore be modelled by a linear model [76-82]

y - mY + A y - e

(5.3)

where y are the 2 n -l CTs of an ADC, nty are the mean (nominal values) of the CTs, 9 is the set of variables which control the variation in transition levels and Ay is the (2n -\)xp matrix which gives the linear model relating the CTs to the variables. The

model can be estimated from a set of training data i.e. a set of measured CTs for w ADCs. The training data can be denoted by a matrix X = [*], where 1 < i < 2 - 1 represents the index for the CTs and 1 <j < w represents the indices of the ADCs. The mean CTs are estimated using

H%X^
j=
i

(5 4)

and the matrix Ay is determined using a principal component analysis of X. An efficient way to do this would be to subtract the mean transition levels m^ from the measured tran90

sitions xtj as x = x - m , and then perform a singular value decomposition of the resulting matrix, X. Singular value decomposition resolves the matrix X into a product of
T

three matrices X = U X V , as described in Chapter II [126]. The matrix Ay is obtained by extracting the first/? columns of U [81]. The resulting Ay matrix has orthonormal colT

umns, i.e. A A = I. In the remainder of this chapter, it is assumed that the matrix Ay has been derived in this way and satisfies the property of having orthonormal columns. The variables 0 of an empirical model derived in this manner, have no physical significance, i.e. they cannot be associated with the value of a single capacitor or resistor within the ADC. An estimate of the variances of the variables 6,- is given by

a flII , = r =T

SI-

(5.5)

Vw- 1 where X, is the i diagonal element of the matrix X (i singular value)

Stenbakken and Souders [81, 119] and Lyons [82] have shown that it is possible estimate die variables 0 from a subset of all the CTs and to use (5.3) to compute all the CTs. However, to measure a subset of the CTs the servo-loop technique has to be used, and this technique is seldom used because of its long test time. Capofreddi and Wooley [76-77] have shown a technique to improve the accuracy of INL and DNL estimates obtained from a histogram.The technique involves the following steps: A coarse estimate of the CTs is obtained using a ramp with reduced number of samples (ramp with reduced test time). The variables that control the ADC transitions are estimated using

9i

9 = (AyAy) AJy (y-my) = A!J (y-my)

(5.6)

where y are the (coarse estimates) CTs computed from a histogram, and Ay is the linear model matrix given in (5.3). The CTs are computed using (5.3) substituting 0 for 0. This method reduces 2n - 1 measurements into p independent parameters and this has the effect of averaging the noise on all the measurements [76-77]. Therefore, this method gives an improvement in the standard deviation of the error in linearity estimates by a factor of approximately

Jp/2n.

5.3 Overview
The linear modeling techniques for improving ADC test time depend on the computation of a few independent parameters that control the linearity metrics of an ADC. This can be seen as a diagnosis problem, where the parameters are diagnosed from measurements made on the IC. It is proposed that, if more accurate estimates of the independent parameters can be made, the accuracy of the computed linearity metrics will be improved. Therefore, ADC test is formulated as a diagnosis problem of computing the parameters that control linearity, accurately. It is shown that, if estimates of the variance of measurement noise are available, the computation of device parameters can be made more accurate. Methods to accurately estimate the variance of measurement noise, as a function of test length, are also proposed. The conditions to be satisfied by an ADC for the application of the proposed methodology are the two conditions stated in Section 5.1 for the construction of a linear model. First, a linear model for the ADC is constructed from a training set using the methods
92

described in Section 5.2.3. The average device noise variance for the ADC is also measured from the training set. The proposed methodology works with the histogram method for measuring INL and DNL because of the reduced test time in comparison to the servoloop method. As noted in Section 5.2, the histogram techniques estimate all the CTs in one pass. Gapofreddi and Wooley [76-77] have shown that the accuracy of CT estimates can be improved by using a linear model (5.6). It is shown that, if the variance in the errors in y are known, more accurate estimates of the 0 can be made than is suggested by (5.6). From these optimal estimates for 9, an improved estimate of yean be made. An overview of the proposed approach is given in Figure 5.1. The steps within the dashed box have been demonstrated in literature [76-82] while the remaining parts are the contributions of this work. The proposed technique consists of an off-line model building phase and a production test strategy. During the off-line model building phase, a minimal test length is selected that will give the required accuracy in the CT estimates. Also the parameters required to calculate the optimal estimates for y from the histogram estimates of y (Ay, GQ and a^) are computed. During production test, a sine wave or ramp of the computed test length is applied to the DUT and the CTs are estimated from the resulting histogram. Then, using the parameters computed during the model building phase an optimal estimate for the CTs is made. The ADC linearity metrics are computed from these optimal CT estimates and the device is classified and good or faulty by comparing the metrics against specified limits.

93

Model Building ADCs Training Set Production Test Strategy

Measure All CTs Accuarately Estimate Device Noise

Linear Model Construction AToe

L _ _ _ 4 _ _ _ _ _ 4 J 'en

Ay, <fy a 0
Optimal y Estimates

Estimate Variance of Error in y, Test Length Selection: N

i ^
Pass/Fail ?

Figure 5.1 P r o p o s e d A D C Test Strategy

5.4 Improved estimation Linearity

In this section, it is shown that the estimate of CTs can be improved with the knowledge of the variance of the errors in y. The histogram estimates of CTs can be modelled as

y = y+e

= my + A d + e,

(5.7)

where ey is the error in the estimate of y. It is assumed that ey is a random variable with
2 2

zero mean and variance a

. Tecliniques of predicting a

are described in Section 5.5. It

is further assumed that the error in estimates of different CTs are independent. This assumption is true as long as the device noise is less than the width of an LSB of the DUT [85, 89-90]. Under this assumption, the estimates of the variables are given by

9 = A ; - ( Y - m Y ) = 0 + <?(

(5.8)

94

where e is characterized by variance oeQ. It can be shown that cey = G e9 and that the elements of eQ are uncorrected, since the columns of A y are orthonormal. Since the variance of the variables 0 are known, (from (5.5)) a least squares linear estimate for 0 can be computed as follows. For two random variables x and y with zero means, standard deviations ox and Oy and correlation coefficient r, it can be shown [127] that the least squares linear estimate for x given y is given by

x = E(x\y) = r- -y y
Substituting x=Qh the z"th element of 0 and y=Qj+eQi, r = / 2 2 VC6i + GeQ

(5.9)

and

= Gv

p2~t

- - are obtained. Therefore, an optimal estimate for 0, which is denoted by 2~

0, is given by

3d-' ^ 7 / ( ? - *fy)

V/,1 < i </>

(5.10)

where <j0l- is the standard deviation of 6/ and Ay is the / column of Ay and % is a scaling factor. Let us examine the structure of (5.10). It can be seen that the estimates for 0, using the proposed method are the estimates proposed by Capofreddi and Wooley [76-77] multiplied by the scaling factor % , which is always less than one. For the dominant vari-

95

ables in the model, i.e for the variables for which a 0 / oey, (5.10) becomes equivalent to
2

(5.6). For the non dominant variables, i.e the variables with small a e / , the estimate for 0/ from (5.6) is scaled by the factor %,, which is less than unity. This scaling minimizes the error in estimation of 0,. The CTs are estimated from 0,- using (5.3). For a sine wave signal, the variance in errors in CTs estimates vary with the voltage level of y. To accommodate this fact, each equation in (5.7) is scaled by Gy/, the standard deviation of the error in y/? to obtain a set of scaled equations, y1 = y + e'where

li ~

it =

% G vi eyi

and A'' -----LG, D ;J

eyv

Ay

(5.11)

The D[.] operator creates a diagonal matrix from a vector. The new variables ^i all have variance in error equal to one. The matrix A' no longer has orthonormal columns due to the scaling of its rows. Therefore, a singular value decomposition of A' is performed to obtain A'y = U'y S'y V'y . Now, a new set of variables 0' - S'y V*y 0 is formed. With this set of new variables the set of equations

y = vy-fjr + e'y

(5.12)

can be formed, where the variances of all the elements of e} are equal (to 1.0), and the columns of U' are orthonormal. By these mathematical operations, (5.12) has been converted to the form of (5.7) and the steps of (5.8)-(5.10) can be performed on it to obtain an optimal estimate of y1, which is denoted by Y . y can be estimated from y1 using

96

Y = D[c2eJ-y 5.4.1 Test Length Selection

+ my

(5.13)

In the testing of ADCs, the maximum error allowable in the estimates of INL/DNL is usually specified. The objective of the test length selection procedure is to select a minimum test length that would give the required accuracy in measurement. To do this, the expected variance of errors in linearity metrics is estimated using the procedure described in Section 5.3. For a linear ramp input, since the optimal linearity estimates are computed using (5.3), y can be shown to be [126]

a"~ = diag[Ay-D[o2e~Q]-Ay]
2 -

(5.14)

where a ~ is the variance in the error in 0 and the diag[.] operator extracts the diagonal
of a matrix. Since 0/are computed using (5.10) and 0. are given by (5.6), (7 - . are given by
eyji

<4 = < ' X ) 4 + X < = -T^Y

2

2 Ga,-

<

(5-15)

where a

is the variance of errors in the CTs obtained from a histogram. Techniques

2

for estimating <5 as a function of test length are described in Section 5.5. For a sine wave input, using similar calculations, the errors in CTs estimated using the proposed technique can be shown to be

c2e~ = diag[D[a2ey) Uy D [ a ^ t ] - Uy]

(5.16)

91

where Uy, y , are as defined in Section 5.3 and a - is the variance of the variables 6'
2

defined in Section 5.3. Using calculations similar to (5.15), a ~r can be shown to be

i
2

2=

4^Ge, + 1

(5i7>

Once G ~ has been determined, a limit on the errors in linearity measurements can be computed such that P\\e~\<h\ = 1-8 (5.18)

where P[.] denotes the probability operator. For a specified accuracy in measurement i~|,
2 -n

the test length should be chosen such that max{o~) = - . In the experimental results pre' k sented in this chapter, e = 10"5 has been used, which gives k = 4.4172 for an e^ that has a Gaussian probability distribution.

5.5 Methodology for Predicting Variance of Measurement Error in CT Estimates

The optimal CT estimates in (5.15) need the value for the variance in the errors in CT estimates obtained from the histogram. In this section, it is shown how the value of o ^ may be derived as a function of the test length, given the variance of the input-referred noise of the ADC. S. Max [85] has used behavioral simulations to estimate <5ey. Doernberg et. al. [86] have analyzed source of errors in linearity metrics obtained using a sine wave histogram. However, the authors assume that the sine wave is randomly sampled, which is not the case in most test situations, where the sampling technique used is synchronous

sampling. In synchronous sampling, the frequency of the input signal is related to the sampling frequency of the ADC by the ratio of two, relatively prime, integers. J. Blair [89] has analyzed the effects of device noise and quantization effects on the accuracy of linearity metrics obtained using a histogram for a sine wave input signal and he has given asymptotic expressions for the variation of worst case a ^ as a function of test length. A more rigorous analysis is provided in this section, to obtain accurate expressions for aey, that are valid for all values of test length. The computation of the variance in the estimate of CTs is based on the model given in Figure 5.2. The noise sources inside the ADC are modelled as an equivalent noise source

(^)V(t)

"Noise-Free" ADC SS clock

Figure 5.2 Model for Computing a ^ in series with the analog input of the ADC. For an input signal V(t) the samples captured by the ADC would be S{ = V(ix) + en{ix) - Vt +e, where 1 is the period of the sampling clock of the ADC. It is assumed that the random process en(i%) is an independent and identically distributed (i.i.d) Gaussian process with zero mean and standard deviation Gn. The value of (5n is usually not known a-priori and has to be estimated experimentally from a set ofADCs.
99

The measured output of an 8-bit ADC with a linear ramp input with an average of 128 samples/code is shown in Figure 5.3 .It can be seen that when the input to the ADC is near

Sample Index

*io"

Figure 5.3 Output of ADC in Response to Linear Ramp Input the code transitions the output of the ADC switches randomly between adjacent codes due to noise in the ADC. It can be seen that CTs estimated from a histogram of this output will have two sources of errors 1. If there are n samples (on the average) per code of the ADC, the minimum step change possible in the measured DNL is \in. Therefore, the resolution of the measurement is restricted 1/n LSBs. 2. As shown in Figure 5.3, the noise in the ADC will cause it to switch randomly between adjacent codes, when an input signal near a CT. This adds additional error in CT estimates. The effects of these two sources of errors is illustrated in Figure 5.4 . The figure shows voltage samples near a code transition from j to j+1. The horizontal axis represents voltage input to the ADC with the dots representing the sample voltages that would have been obtained for an ideal (noise-free) ADC
(K(JTC)).

For voltage samples near the CT, voltage

samples which should ideally have given code/ at the output have a non-zero probability
100

Code

Transition

Figure 5.4 Errors in Histogram of giving a output code greater than7 due to ADC noise and vice-versa. Since the voltage samples are spaces A Volts apart, the resolution of the CT measurement is A Volts, as can be seen from Figure 5.4. To analyze the effect of noise and finite resolution of measurement on the estimation of the CT, following quantities are defined. Vb = max(Vi\P[C(Vi + en)>j]~0 (5.19)

i.e. Vb is the largest sample value of the input signal that has (approximately) zero probability of giving an output code greater than/ is a small constant (equal to 10"6 in the calculations in this chapter), that is required because a Gaussian distribution has a finite probability of being arbitrarily large. C(x) is the code at the output of the ADC when x is the input value. A set S is defined as

S = {Si\P[C(st) <j] > t P[C(Si) >j] > Q

(5.20)

i.e. a set of samples that have non-zero probabilities of giving an output code greater than or less than or equal toy depending on the value of noise on the samples. Let the true value for the CT y is given by y- = Vb+mA+a, A and a are as indicated in Figure 5.4. It is

[01

assumed that the CT can occur at any point between the two voltage samples with equal probability, i.e. a can vary uniformly from 0 to A. Under these definitions, the measured value of the CT y. is given by

7,. = Vb + kA + ^

(5.21)

where the A/2 term has been added to make the estimate of y- unbiased. The symbol k represents the number of elements the set S', defined as S' = {*,!*, C ( * , ) / } (5.22)

i.e. S' is the subset of S that give output less than or equal t o / The error in estimation of y, e . = y. - y. is given by (m - k) A + a - . The mean square value of e^ is given by

E(ey) = A f E((m-kf\a
^=0

= x)dx + 2- j E((m- k)\a = x)(a^=0

-)dx + ^- (5.23)

where

(JC|J/)

is the conditional expectation of x given the value of > > . (5.23) requires
2I

the estimation of E((m-k)

\a) and E((m~ k)\a).

Since w is a constant it is only

required to estimate the mean and variance of k. For a given value of a, the random variable k can be modelled as * = 5>i
ie S

(5-24)

where ^ = 1 iff C(st) <j, and J U L / = 0 otherwise. The probabilities of |ir- being equal to one is given by

102

l-v,

P[C(Si)<j]

= P[V, + en<y]= P[en<y~

V,] = J J2K-0

e2'"dx

fi
x
1
2

y- Vi

(5.25)

where g(oc) =

J2n x J= a

[ e dx

Substituting y-Vj equal to z'A+a,

nji,= i] = ^ef^f^H 3/
P [ ^ . = 0] = 1 - p .

< 5 - 26 >
(5.27)

The mean of jii/ is equal to p,- and the variance of u^ is equal to (3^(1-(3^) [127]. Therefore the mean and variance of k are given by

E(k) = p,
ieS

0^ = X P,.- p?
is S ie S

(5.28)

is estimated by substituting the results of (5.28) into (5.23). (5.23) now involves the

integral of Q(.) functions. Therefore, the integration in performed numerically.

5.5.1 Computation of o^ for Ramp Signal

For a linear ramp or triangular wave, the resolution in measurement A is independent of the CT. For a test signal having T V samples of ADC output, A is given by

2n A = Volts = LSBs iV A'

VFS

(5.29)

103

where VFS is the full-scale voltage of the ADC and n is the number of bits.

5.5.2 Computation of G^ for Sine Wave Input Signal

For a sine wave signal, the resolution of the measurement A depends on the CT. It is assumed that the sine wave and the clock input to the ADC are synchronized, so that

^iztik

+ 81, 0<n<N.

The relative frequency k is chosen to be relatively

prime to N. Under these test conditions, the samples of s(nx) can be rearranged to form a + 5 in effect. The variable 5 represents the variability in initial phase of the sine wave and 0 < 5 < 2n .Therefore the resolution in measurement A is found to be [891 N

A = hs(nx)) dn

=A-^N

s i n f ^ + d] - A ^ jA2-s\nx) \ N J N

(5.30)

If the curvature of the sine wave is ignored t\i = A ,JA - yt is obtained. It is

VFo

noted that A ~

and that for half of the sine wave the samples of the sine wave are

repeated (a sine wave covers its full span of voltages in half a cycle).

5.6 Practical Considerations

The derivation of the optimal estimates for CTs in Section 5.3 (5.10) used the variances of process variables 9;- (CF 9/ ) and the variance of errors on the CT estimates (ag ). o

104

depends on the variance of device noise and o e / depends on the amount of variability in the manufacturing process of the ADC (i.e. amount of mismatches in capacitor and resistor ratios, offsets etc.). Therefore these variables can vary over time in any given manufacturing process. In this section, the effects of such long-term variations on the optimal CT estimates is studied, and procedures to alleviate the effects of process variability are proposed. The optimal estimates for CTs depend on the variance in device noise and the variance of the process variables 0/. () can be rewritten as

9,- = - Ayr (y~ my) 2

<*e/
2

(5.31)

where the ratio ^ will depend on the device noise variance. To compensate for the

e/
effects of variation in device noise a ^ m a y be estimated from measurements as follows. Consider

e = Ay- A ^ - y - y Substituting y = I y,

(5.32)

? - (Ay-A^ - - I M Computing the expected sum of squares of e,

(5.33)

E(eT e) = E{e] (A y ATy - I ) ey) = a2eJ (2n - 1 -p)

(5.34)

105

Since e can be computed from the measured CTs (y), cey may be estimated from the measured CTs. To check for variations in process statistics the variance of the computed variables 0; may be monitored. If a significant change in the process statistics is observed, a new linear model must be built using a training set derived form the ICs with the new process statistics.

5.7 Results
The experimental results are given in three sections. First, it is verified the expressions derived in Section 5.5 are verified using simulation in Section 5.7.1. In Section 5.7.2, the effect of device noise and test length on the estimates of CTs is analyzed and a minimum test length for a give accuracy requirement in CT estimates is chosen. In Section 5.7.3, the experimental set-up used for making measurements is described. In Section 5.7.4, experimental results from a commercial ADC [146] for a ramp input are presented. In Section 5.7.5, simulation results for a sine wave input are presented.

5.7.1 Verification of o ^ Estimates via Simulation

In this section, the formulae derived in Section 5.5 are validated using simulation. The simulation model used for behavioral simulations is shown in Figure 5.5, which models the DC (low-frequency) behavior of ADCs.The model consists of (i) an input noise source, (ii) an ideal sample-and-hold and (iii) a set of CTs which represent the DC transfer function of the ADC. The behavioral simulation tool was implemented in C. In this simulation model, the CTs for the ADC were varied with a standard deviation of 0.1 LSB and

106

Output

(^)V(t)

Code

CTs Figure 5.5 Simulation Model for ADCs the CT are estimated using a ramp and sine wave signals. The difference between actual and estimated CTs was computed to estimate G^. The results for estimation of oey for the ramp signal are given in Figure 5.6. The x-axis of the plot is average the number of sam-

CQ
CO J, 0.2

JiQ.15

Samples per Code (N/2n)

Figure 5.6 Comparison of Theoretical and Simulated o^yfor a Ramp Signal pies of the test signal per output code of the ADC. This is equal to l/A as given in (5.29). The different curves are for different values of device noise variance from O.l LSB to 0.5 LSB. It is seen that the theoretical results show excellent matching with simulations. To compare the results obtained to those obtained in previous approaches [89], the error in the estimated noise standard deviation, compared to simulated results, is shown in Figure 5.7.

107

Test Length (Samples/Code)

(b) Figure 5.7 Comparison of Error in a^ for Proposed Approach vs. Earlier Approaches [89] The error in estimated <Jey using the approach proposed by J. Blair is shown in Figure 5.7(a), while the error using the proposed approach is shown in Figure 5.7(b). It is seen that the error in estimated a ^ i s extremely small for the proposed approach., compared to the one proposed by J. Blair.

The results for estimation of for a sine wave signal are given in Figure 5.8. The results

100

150

200

250

100

150

200

250

Code Index
(a)

50

100

150

200

250

Code Index (b)

Code Index (c)

Figure 5.8 Comparison of Theoretical and Simulated o^ for a Sine Wave Signal

are given for an 8-bit ADC. Since the Ge varies with the voltage of yi9 the x-axis in Figure 5.8 is the code index for the converter. The different curves represent the different values of device noise Gn from 0.1 LSB to 0.5 LSB. The curves have been generated for

108

test lengths of 4096, 16384 and 65536 in Figure 5.8(a), Figure 5.8(b) and Figure 5.8(c) respectively. It is seen that the theoretical results agree well with simulations. The simulation results show some degree of variability due to lack of enough averaging. The simulation results for the ramp in Figure 5.6 were averaged over the all the codes and therefore show almost exact matching with theoretical results. However, since the error in CT estimation for the sine wave signal varies with signal level, this averaging cannot be performed for the sine wave signal. The generation of simulation results took more than 6 hours of CPU time while the theoretical results were computed in a about 5 minutes of CPU time. But the theoretical results are a closer approximation to the true values of standard deviation in error. This illustrates the importance of having closed form expressions like (5.23) to easily evaluate the effect of noise for different values of test length and device noise. The comparison of worst case (over all codes) r.m.s error in CT estimates for a sine wave is shown in Figure 5.9 . The five curves are for values of aen from 0.1 LSB to
0.25

a=0.5 ae=0.4
0.2

"Theoritioal C a l c u l a t i o n s Results

ae=0.3 oe=0.2 aew=0.1

i2 0.15

P Q ft
W

o.l

D cos
O 10l 10' lO" icr

Test L e n g t h

(Samples/Code)

Figure 5.9 Comparison of Theoretical and Simulated w.c a^for Sine Wave Signal 0.5 LSB. It is seen that the theoretical results match simulations very well.

109

5.7.2 Selection of Test Length

In this section, the computation of test length for a given required accuracy and variance of device noise is presented. Test length is directly proportional to test time is the sampling frequency of the ADC is specified. For experimentation, linearity metrics of 75 ADC0831 ADCs were measured at 512 samples/code . A linear model was built for the CTs of the 75 ICs using techniques described in Section 5.2.3 [81]. The r.m.s device noise was found to be 0.1 LSBs. The variation in r.m.s error in the CTs for the proposed technique is shown in Figure 5.10. The
O R M S Error ( P r o p o s e d T e c h n i q u e ) * R M S Error (Capofreddi and W o o l e y ) R M S Error ( N o Linear M o d e l U s e d )

w 5

m
en
HJ
0 0 4

i-^b.oa

10

10

lO

lO

Samples/Code (N/2 f

Figure 5.10 Variation in o^ vs. Test Length for a Ramp Signal values of a^y without the use of the linear model and for the use of a previous technique [76-77] are also shown for reference. It is seen that the performance of the proposed technique is similar to the one proposed by Capofreddi and Wooley for large values of test

1. It should be noted that to produce a true ramp signal at 512 samples/code a DAC of 17 bits (ADC 8 bits +9)resolution is required. Since the Data Acquisition DAC has only 16 bits, a ramp at 512 samples/code will have adjacent output samples to be the same value. However, since the quantization level of the DAC is much less than the input noise of the ADC, this ramp behaves as an ideal ramp with the 17 bit resolution required.

no

lengths (-128 samples/code). However the performance of the proposed technique becomes significantly better as the test length reduces. For a sine wave signal, the errors in CTs is a function of the voltage level of the CTs. Therefore, the worst case (over all codes) r.m.s error in CT estimates with and without the use of the proposed technique are compared. This is s own in Figure 5.11. A direct com0.12
0.1
/v C/l

Computed from Histogram -e- - Using Proposed Technique

on

DQ

0.08

^- 0 . 0 6

D*
0.04 0.02

io

101

JO2

103

Samples/Code (N/2 f

Figure 5.11 Variation in a ^ vs. Test Length for a Sine Wave Signal

parison with the technique used by Capofreddi and Wooley [76-77] is not provided since they assumed random sampling of the sine wave in their results. It can be seen that the proposed technique gives significant improvement in test a ^ for a given test length for a sine wave input signal. To select a test length that will give a prescribed accuracy of measurement, plots of the form of Figure 5.6 and Figure 5.7 can be used. A test length of 16 samples/code was selected for the sine wave and ramp to give a worst case error of 0.1 LSB, after giving sufficient safety margins.

111

5.7.3 Test Set-up

The experimental set-up used to make measurements on the ADCs is shown in Figure 5.12. A PCI-6110E [151] Data Acquisition (DaQ) plug-in card from National

PCI-6110E CNTR1 Out DACO Out AOGnd A I 1 (+) CNTRO Out Gnd Vcc(8Vb DC Power Supply Computer

T3F A/V^Q.lyu

" ADC0831 -. CS Vcc Vin(+) Vref Vini(-) DO Gnd Clk

J 10 H o.ig

LM2SM OTra

10 n

-A/W

ID

^H

Figure 5.12 Experimental Set-up for ADC Measurements

Instruments was used to generate the linear ramp and transfer the outputs of the ADC to the computer. The plug in card has 2 16-bit Digital-to-Analog Converters (DACs) which can be used to generate precision waveforms. A low-pass filter consisting of the two 1.5k resistors and the
O.IJLLF

capacitor was used to filter out high frequency noise and glitches

from the output of the DAC. The DaQ card has two general-purpose counters which were used to generate the timing signals (clock and chip select) for the ADC. The serial output of the ADC (DO) was unable to drive the input channel of the DaQ card directly. Therefore, 74HC04 inverter was used to buffer the ADC output. An LM7805 3-terminal regulator [147] was used to provide a stable power supply and reference to the ADC. LabVIEW [150] software was used to control the DaQ card for data acquisition. The

112

test programs for the ADC were written to generate triangle waves. Therefore, the results on hardware measurements are for the ramp input signal. To demonstrate the technique for a sine wave input signal, simulation results are given in Section 5.7.5.

5.7.4 Hardware Measurements for a Linear ramp input signal

For validation of the proposed test technique, linearity metrics for 25 new ADC0831 ICs were measured at 512 samples/code. These measurements were considered the "true" INL/DNL and used as reference to compute the error in INL/DNL estimates obtained using the proposed technique. Ramps of length 4096 samples (16 samples/code) was applied to the ADCs and the INL/DNL were obtained from the histogram produced by this signal, using the proposed technique. The computed INL and DNL using the proposed technique for IC no. 4 is shown in Figure 5.13 and Figure 5.14, respectively. The (inaccu-

0.2

0.1

PQ
OO
^, h-J -0.1

-0.2

-OS

10

20

Reference Inl Inl C o m p u l e d using p r o p o s e d T e c h i n q u e Raw INL from l i s t o g r a n 30 40 50

60

70

Code Index

Figure 5.13 Comparison of Predicted and TRUE INL for a Ramp Input

rate) INL and DNL obtained directly from the histogram at 16 samples/code, without the use of the proposed technique, is also shown in figure (denoted as raw INL/DNL). The INL/DNL measured at 512 samples/code is denoted as the reference INL/DNL. It is seen that the computed INL/DNL obtained matches the accurate measurements quite closely.

113

Reference. Oril Dnl Computed using proposed Techinque R *w DfsIL fioin I ilstog rtirn

10

20

L1CJ

40

SO

GO

70

SO

Code

Index

Figure 5.14 Comparison of Predicted and TRUE DNL for a Ramp Input

The r.m.s of the errors (averaged over all codes of an IC) in the measurement of INL/ DNL, for the 25 ICs, computed using the proposed technique is shown in Figure 5.15. The

IC Index

IC Index

Figure 5.15 R.M.S Error in INL and DNL r.m.s error in INL/DNL using the technique proposed by Capofreddi and Wooiey [76-77] and the r.m.s error using an input ramp having 128 samples/code (8 times test time, the original test length for ADC0831) without the use of the linear modelling technique are also shown for reference. It is seen that the proposed technique performs significantly better than the one proposed by Capofreddi and Wooiey [76-77] in terms of r.m.s error in INL/DNL estimates.

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ADCs are usually specified in term of peak INL/DNL (i.e the devices are classified as good or faulty on the basis of whether or not the peak INL/DNL is less than or greater than a specified threshold). Therefore, it is important that any proposed technique for measurement measures the peak INL/DNL accurately. The error in the peak INL and DNL estimated using the proposed technique is shown in Figure 5.16.It is seen that the proposed

CQ C/D -J

PQ 05 J, ^J

a
<u P-,

fc IC Index

I
-^J

IC

Index

Figure 5.16 Error in Peak INL and DNL

technique meets the proposed technique meets the requirement in measurement accuracy (error < 0.1 LSB) for all 25 ICs. The proposed technique shows a significant improvement in the prediction of peak INL over the technique proposed by Capofreddi and Wooley [7677] (maximum error of 38.8 mLSBs vs. 49.2 mLSBs over the set of 25 ICs). However, only a small improvement is seen for the error in peak DNL estimate (maximum error of 72.2 mLSB vs. 84.5 mLSB over the set of 25 ICs). An explanation for this is as follows: The ADC0831 has a successive approximation architecture, therefore the peak DNL occurs usually for the MSB transition. The variable (0,-) that controls this transition has a large variance. For this variable, the technique proposed in this research becomes equivalent to that proposed by Capofreddi and Wooley, and therefore, the errors in peak DNL estimates are about same for both techniques.

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5.7.5 Simulation Results for a Sine Wave Input Signal

To demonstrate the effectiveness of the technique for sine wave inputs, the measured transfer functions of the 25 ADCs used for experimentation in the previous section were simulated using a sine wave input signal. The test length chosen was 4096 samples, which gives an average of 16 samples/code for the 8 bit ADC. The measured INL and DNL are compared to the true INL and DNL in Figure 5.17 and Figure 5.18, respectively. The r.m.s

T R U E INL Using Proposed Technique R a w Inl f r o m h i s t o g r a m 100 1SO

Code Index Figure 5.17 Comparison of Measured and TRUE INL for a Sine Wave Input

100

150

Code Index Figure 5.18 Comparison of Measured and TRUE DNL for a Sine Wave Input error and error in the maximum computed INL and DNL for the 25 ICs is shown in Figure 5.19(a) and Figure 5.19(b) respectively. It is seen that the technique is able to com-

116

area

3 <

fc w

IC Index

IC Index

Figure 5.19 R.M.S and Error in Peak of Estimated INL and DNL pute the INL and DNL accurately for a sine wave input signal also, at low values of samples/code.

5.8 Summary
In this chapter, the diagnosis algorithms developed in this thesis were applied to the problem of reducing production test time for ADCs. The formulation of ADC test as a diagnosis problem resulted in a methodology showed significant reduction in test time. Experimental results, to demonstrate the effectiveness of the technique, were presented.

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CHAPTER VI HIERARCHICAL FAULT ISOLATION FOR ANALOG AND MIXED-SIGNAL BOARDS

In this chapter, the methods for fault diagnosis developed in this thesis are extended to larger systems. A technique for hierarchical fault isolation in analog and mixed-signal PWBs is proposed. The technique is based on verifying the fault-free behavior of partitions of the circuit, and can be applied hierarchically to large systems. The technique is shown to be independent of the availability or completeness of fault models for the CUT. The technique has minimal computational requirements and can be easily programmed on automatic testers. Experimental results to show the effectiveness of the technique are presented. The technique depends on access to internal nodes of the CUT, and therefore is tailored toward fault isolation in PWBs, rather than ICs where access to internal signals can be difficult.

6.1 Overview
One of the major obstacle to automated fault isolation in mixed-signal circuits is the lack of precise models for failure modes of mixed-signal circuits. PWBs often contain ICs obtained from outside sources, whose failure modes may not be well characterized. Another problem in fault isolation is that, in the presence of tightly coupled feedback loops, which are present in a large number a of analog and mixed-signal circuits, the

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waveforms at all nodes of the CUT are altered by a fault in any one module of the CUT. However, the following are facts may be used for fault isolation. Although detailed fault models are difficult to obtain, behavioral models that approximate the fault-free behavior of modules in the circuit, are usually available, or can easily be built from the performance specifications of the modules. Within a faulty circuit, the relationship between the inputs and outputs of a fault-free module are not altered. For example, the amplitudes of signals at the input and output of an embedded amplifier in the CUT will be related by the gain of the amplifier, even though the inputs and outputs of the amplifier may change under fault in some other Off-line Training C U T Netlist ^Jodes to Access Hyper graph modeling and Partitioning | Partitions Regression Model Construction | Lowest Leve_ 9 ^00^ N o r Faulty Partiton Fault Isolation Strategy CUT

Make Measurements Find Faultypartition

Regression Models

Figure 6.1 Overview of fault isolation technique portion of the circuit. FV techniques take advantage of this fact to isolate faulty parts of a mixed-signal system. However, FV techniques perform expensive circuit simulations after making measurements on the CUT, and therefore cannot be applied to large mixed signal circuits. In

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this dissertation, techniques to approximate the fault-free behavior of circuit partitions using nonlinear regression models are proposed. These regression model for the & * partition of the CUT is denoted by

Ok=fi0(t)

(6.1)

where O are the outputs of the partition and I are the inputs to the partition. The regression models are constructed using off-line circuit simulations. In the proposed methodology, the inputs and outputs of a partition are properties of voltage waveforms at the external nodes of the partitions. During testing, the waveforms at all the inputs and outputs of each partition are measured. A partition is denoted as faulty if its output waveform properties differ from those predicted by the regression model. An overview of the proposed methodology is given in Figure 6.1. As the first step, the CUT is partitioned recursively, while minimizing the number of nodes that have to be accessed for partitioning. This results in a hierarchical tree of circuit partitions as shown in Figure 6.2, which is used for fault isolation. Then, nonlinear regression models are con-

CUT
r -i

-o o
c d
r
"i
*

^J_J_J
L _ _ _ _ _ J

faulty partition
i
r

| |
J

kfeJ
partition 2

. _

partition 1

Figure 6.2 Hierarchical Circuit Partitions

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structed to approximate the fault-free behavior of each partition. Since only the fault-free behavior of partitions of the CUT are modeled, the methodology is independent of the accuracy or completeness of fault models available for the CUT. During testing, waveforms at all the external nodes of each partition are measured and the faulty partition is identified by comparing the measured outputs of the partition with those predicted by the regression models. Then, internal nodes of the identified faulty partition are accessed to isolate the fault to one of its sub-partitions. The computations required after obtaining measurements from the CUT are minimal and can be easily programmed on to an automated tester. The proposed technique makes only voltage measurements on the CUT and can be used for fault isolation of embedded modules.

6.2 Automated hierarchical circuit partitioning

In the proposed fault isolation technique, the fault-free operation of partitions of the CUT is verified by measuring waveforms at all the outputs of the partition. Therefore, the automated partitioning algorithm should 1. Minimize the number of nodes accessed while partitioning and 2. Ensure that the partitions are approximately equal in size in order to form a balanced fault isolation tree. The first condition ensures that only a minimum number of nodes are accessed for fault isolation and the second condition minimizes the average depth of the fault isolation tree, which minimizes the number of steps required for isolating the fault down to the smallest partition of the CUT. To automatically partition a circuit, it is modeled as a hypergraph. The multilevel hypergraph coarsening algorithm proposed by Karypis et. al. [132] has

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been used to obtain near-optimal partitions of the CUT. The effects of loading in analog circuits is not taken into account by the original hypergraph partitioning algorithm. Techniques that account for loading by analog networks are described in Section 6.2.2.

6.2.1 Hypergraph modeling of CUT and hierarchical partitioning

A hypergraph is a generalization of a graph where the set of edges are replaced by a set of hyper-edges. A hyper-edge extends the notion of an edge by allowing more than two vertices to be connected by a hyper-edge. Formally, a hypergraph H = (V, E ) , is defined

R2

.
in

RI rMAn
out f op J; ; m

* f^r
(a)
\(R2

ItlY m'

(b)

Figure 6.3 A simple Circuit and its hypergraph representation as a set of vertices Fand a set of hyper-edges Er, where each hyper-edge is a subset of the subset V. To model a circuit netlist as a hypergraph, each module in the circuit is repre-

Vs *.. (Rl) Am

(a)

(b) Figure 6.4 Hypergraph partitioning

sented as a vertex, and the nodes of the circuit which connect the modules are represented

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as hyper-edges. The hypergraph representation of a simple circuit is shown in Figure 6.3. The circuit, which consists of the modules Vs, Rl, R2, and op and the nodes in, out, and m, is shown in Figure 6.3(a). The hypergraph representation of the circuit is shown in Figure 6.3(b). The vertices of the hyper graph are represented as circles and the hyper edges are marked by dashed lines. Figure 6.4 shows how the hypergraph partitioning relates to the number of nodes accessed in the CUT. In Figure 6.4(a) a partition of the graph is shown with the hyper-edge 'nf being cut by the partition. This corresponds to the partition of the CUT shown in Figure 6.4(b) with 'm' being the node accessed for partitioning. Optimal hypergraph partitioning is known to be at least N-P hard. Several heuristic algorithms exist for obtaining near optimal partitions. Karypis et. al [132] have described an efficient algorithm for partitioning hypergraph which minimizes the number of hyper edges cut by the partition and constraining the partitions to be of approximately equal weight. The algorithm is based on hypergraph coarsening, i.e. collapsing vertices of the hypergraph to get successively smaller hypergraphs. The hypergraph is partitioned at the coarsest level and the partition is projected to successively finer hypergraphs, and the partition is refined after each projection. The algorithm has given very good results on several benchmark problems.

6.2.2 Effects of Loading

In general, the outputs of a partition of the CUT will depend on the inputs to the CUT and the load offered by the rest of the CUT, i.e. (6.1) must be modified to

Ok = ftoif, load)

(6.2)

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However, in many cases, the variation of voltage due to loading can be neglected when compared to the variation in the outputs due to manufacturing tolerances of analog components within the partition. To illustrate how loading in analog networks affects the fault isolation algorithms, consider the two simple example circuits given in Figure 6.5. In partition 1 p partition 2 out

in^A/VV

out

partition 2

partition 1

(a) (b) Figure 6.5 Example circuits to illustrate the effects of loading Figure 6.5(a), a fault in partition 2 will not affect the I-O relationship of partition 1 because of the high input impedance of an opamp in closed loop. However, for the circuit in Figure 6.5(b), a fault in partition 2 will change the load on partition 1 and hence affect its I-O relationship. Since the methodology is based on verifying the fault-free behavior of each partition of the CUT, this can lead to partitions being falsely labeled as faulty. In order to overcome this problem, the hypergraph partitioning algorithm is modified as follows. After partitioning, it is attempted to identify external nodes to every partition that are not affected by the loading of the rest of the CUT. The waveforms at these nodes become the outputs of the regression models given in Equation 1 and the waveforms at all the remaining external nodes of the partition become inputs to the regression model. If all external nodes of a partition are affected by loading, the fault-free behavior of the partition cannot be verified by measurements on the external nodes alone. In this case, an additional

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internal node of the partition is selected to be accessed during fault isolation and the properties of the waveform on this internal node become outputs to the regression model. This is because the waveforms at internal nodes to a partition are affected only by the waveforms at the external nodes of the partition. Tn this way, the problem of loading is alleviated, but an additional node has to be accessed during fault isolation. Applying the above algorithm to the partitions in Figure 6.5(b), it is found that for partition 2 the node 'out' is not affected by loading and therefore, properties of waveforms of that node become the outputs of the regression model. However for partition 1, both the external nodes ('in' and '1') are affected by loading. Therefore the waveform on the internal node '2' will have to be measured to verify the fault-free operation of partition 1.

6.3 Regression Model Construction

In a general analog circuit, the outputs of any partition are a function of the inputs to the partition and the internal states of the partition (voltages across capacitors, current through inductors, etc.). Since the internal states cannot be measured at the outputs of a partition to the CUT, it is not possible to predict transient waveforms at the outputs of the CUT from measurements on its interfaces alone. Therefore, it is assumed that only steady-state measurements are made on the CUT. Under this assumption the waveforms at outputs of any partition to the CUT are a function of the waveforms at the inputs to the partition alone. The regression functions are built relating parameters of the input waveforms to a partition (such as frequency, phase, amplitude duty-cycle etc.) to parameters of the output waveforms. In a general analog or mixed-signal circuit, the information content in a waveform may be in the amplitude phase frequency or some other property of the signal. Therefore,

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while building the regression model it is important to capture those properties of the waveforms that contain information. The type of measurement made on the circuit is decided based on the type of circuit. An overview of the techniques used to construct the regression models is given in Figure 6.6. The fault isolation technique is based on approximating the 1-0 relationship of

Circuit TsTetlist, Hierarchical Partitions, Input S t i m u l u s

Regression Models
Figure 6.6 Methodology for building regression functions a fault-free module using nonlinear regression functions.The regression functions are generated using off-line circuit simulations. In order to train the regression models, a sample of waveforms that occur at the inputs and outputs of a partition under fault, is required. To obtain these waveforms random faults are injected into all partitions of the CUT and waveforms at the external nodes of the fault-free partitions are recorded. Using this sample of waveforms as a training set, regression models are trained to approximate the behavior of the fault-free partitions of the CUT. Now, new faults are injected into the CUT and the waveforms at the outputs of the fault-free partitions of the CUT are predicted

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using the regression models and the results compared with the simulation results. If the error in prediction is less than a pre-set limit the models are said to have converged. Otherwise, the regression models are refined by adding the newly generated waveforms to the training set. This process is repeated till the models of all the partitions of the CUT become accurate.

6.4 Hierarchical fault Isolation

Hierarchical fault isolation is achieved by descending down the fault isolation tree created by the partitioning algorithm. The external nodes of the candidate faulty partitions are measured and the 1-0 relationship of each partition is checked against the response predicted by the regression model of the partitions. The tfh partition of the CUT is considered fault-free if

\okmi-ACti

< Ou a

Vz, \<i<n0

(6.3)

where Tm are the properties of the input waveforms to the partition, Omi is the ix output of the partition, (property of voltage waveforms at an output node of the partition), and n0 is the number of outputs to the partition. cki is the expected standard deviation on the /th output measurement made on the partition due to measurement errors and the manufacturing tolerances of analog components. The techniques used to determine o^ are described in Section 6.4.1. The constant a gives the confidence interval for fault detection. A large value of a decreases the probability that a fault-free partition is incorrectly found to be faulty, but it also makes some of the soft parametric failures in the circuit undetectable. An a of 3.0 has been used in the experiments which gives a confidence level of 99.9% for an

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error distribution that is Gaussisan.Once a faulty partition is identified, the process is repeated by accessing the internal nodes of the faulty partition for further fault isolation.

6.4.1 Tolerance Effects The output of an analog circuit, both in the faulty as well as fault-free conditions, cannot be represented by a precise value, but can vary under the effect of manufacturing tolerances of analog components. Therefore, a partition of the CUT must be declared as faultfree only if its response differs from the nominal response by a "tolerance band" [122]. To estimate this tolerance band, Monte Carlo simulations on the fault-free circuit is used. The following steps are performed. 1. The parameters of the CUT are varied randomly within their prescribed manufacturing tolerances and the CUT is simulated. 2. The outputs of all the partitions of the CUT are predicted using the regression models constructed as described in Section 6.3. 3. The average (r.m.s) error in prediction is computed for each output of every partition. This error is used as o^z- in (6.3).

6.5 Results
In this section, experimental results to validate the fault isolation technique on three circuits are presented (l)a state variable filter, (2) a leapfrog filter and (3)a PLL based FM demodulator. The circuits were partitioned according to the hypergraph partitioning algorithm described in Section 6.2. Then regression models were built for each of the partitions as described in Section 6.3. Monte -Carlo simulation were run on the two circuits to

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determine the tolerance bands at the outputs of each partition as described in Section 6.4.1. Faults were injected into the different partitions of the circuits (the faults injected were all different from the faults used to train the regression models). The faults injected included both soft parametric deviations and catastrophic faults in the active and passive components in the circuits. The fault-free parameters of the circuits were varied randomly within their prescribed tolerances. Fault isolation was attempted using the algorithms described in Section 6.4.

6.5.1 State variable Filter

The state variable filter is one of the benchmark circuits for mixed-signal test [138]. The schematic for the filter is given in Figure 2.3. The low-pass output of the circuit (output of opamp x3) was labeled the primary output of the circuit. The circuit was tested in the frequency domain using a sine-wave of frequency 800Hz (the filter has a cutoff frequency of about 800Hz). The hierarchical partitions obtained for the circuit is given in Figure 6.7. xl, x2, x3, Rl, R2, R3, R4, R6, R7, R8, CI, C2

xl, x2, Rl, R4, R6, R8, R7, R2 CI xl,Rl,R4,R6, R7,R8 xl,Rl R4,R6 3
xl

x3, R3, C2

x2, R2, CI
1

x3

R3C2

1
->

R7,R8 R1,R4, R6

x2 1

R2C1

Figure 6.7 Hierarchical Partitions for State Variable filter Since voltage excitation and voltage measurements are being used, fault isolation to single components is not possible. The partitions at the lowest level of the fault isolation tree (the

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leaf-cells of the fault isolation tree) represent the finest level of isolation possible using only voltage measurements. The modules contained in each partition are placed inside the boxes and the nodes accessed at each level in the hierarchy is marked on the connections between different levels of the tree. The regression models were built for the filter using circuit simulations. 200 simulations were required to obtain accurate models for all the partitions of the CUT.

6.5.2 L e a p f r o g Filter The leapfrog filter, which is a mixed-signal test benchmark circuit [138], has several interlocking feedback loops which makes fault isolation difficult. The schematic of the fil-

x l , x2, x3, x4, x5, x6, R l , R2, R3, R4, R5, R6, R7, R8, R9, RIO, R l l R12, R13, C1,C2, C3, C4 113.10 xl,x2,x3,Rl,R2,R3,R4,R5,R6, C I , C2 R13 x3, R6, C2 I S x3 R6,C2 x4,x5,x6,R7,R8,R9,R10,Rll,R12,C3, C4

x5,x6,R8,R9,R10 xl,x2,Rl,R2,R3, x4,R7, R12,C3 R11,R12,C3,C4 R4,R5,R13,C1 *1 t& xl,Rl,R2, x2,R4,R5 R7,R12 x4 x5,R8,R9 x6,R10, R3,C1 R13 R11,C4 r-^5, m=L RI,R: x2 R4,R5 R8 x6 RIO, J xl x5 R13 R3,C R9 RIUPJ

if

Figure 6.8 Hierarchical Partitions for leapfrog filter

ter is shown in Figure 2.6. The circuit was tested in the frequency domain using a single test frequency of 1.5kHz. The hierarchical partitions for the circuit is given in Figure 6.8. Accurate regression models for all the partitions of the CUT were constructed using 230 circuit simulations.

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6.5.3 PLL based F M demodulator The PLL based FM demodulator is a slightly modified version of a circuit taken from National Semiconductor's Application Notes [135]. The circuit uses an LM565C PLL IC and the schematic of the circuit is shown in Figure 6.9.The IC was modeled behaviorally
6V

out

=6V

Figure 6.9 PLL based FM demodulator using in SpectreHDL [137], an analog behavioral modeling language available in the Cadence design environment. The circuit consists of the PLL IC configured as an FM demodulator and an output filter for demodulated FM. The circuit was tested in ihz freerunning mode with the input being connected to a constant DC voltage. The node voltages of the circuit were characterized by measuring three parameters of the waveforms (1) the average values, (2) the frequency and (3) the peak to peak ripple voltage. The hierarchical partitions for the CUT is given in 6.10 . The hierarchical regression models were built for the CUT using 200 circuit simulations,

6.5.4 Results for fault isolation The results for fault isolation is given in Table 6.1. It is seen that the technique is able to isolate faults efficiently for all the example (less than 2% mis-classification). The cases

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565c, xl, x2, Rt, Ct, RI, R2, R3, R4, R5, R6, R7, R8, R9, Ct, C2, C3, C4

Rl, R2, R3, R4, xl, Rt, Ct, R9, C4, 565c

R5,R6,C2,C3,R7,R8,X2

-5xl,Rl,R2,R3,R4 Rt, Ct, R9, C4, 565c R5, R6, C2, C3 x2, R7, R8

T
xl,R3,R4 R1,R2 R3,R4 R9,C4 Rt, Ct, 565c R5,C2 R6,C3
x2

R7,R8

5
xl

Figure 6.10 Hierarchical Partitions for PLL based FM demodulator

where faults were not detected were soft parametric failures where the deviation of voltages due to faults was less than the variation in voltage due to tolerance of analog components. Currently, test signals chosen on an ad-hoc basis are being used for fault isolation. To correctly detect and isolate these soft parametric failures, test signals that are optimized for this purpose would be required. Table 6.1: Results for fault isolation
Circuit State variable filter Leapfrog filter FM demodulator Correctly Diagnosed 115 220 342 4 6 51 Not Detected Misdiagnosed 1 4 7

6.6 Summary
In this chapter, a fault isolation technique for PWBs was presented. The technique models the fault-free behavior of partitions of the CUT, to isolate faults. Simulation results to verify the technique were presented.

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CHAPTER VII FAULT SIMULATION AND FAULT ISOLATION FOR MIXED-SIGNAL ICS USING ERROR WAVEFORMS

In this chapter, a novel approach for fast fault simulation of faults in mixed-signal systems is presented, that does not resort to expensive full circuit simulation for every fault. The approach is based on partitioning the mixed-signal circuit and representing fault effects using error waveforms. Methods compress a large number of fault effects into a few fault syndromes are presented. This results in significant savings in fault simulation effort. The ability to distinguish between analog and digital fault syndromes using simple heuristics is demonstrated.

7.1 Introduction
With advancing semiconductor process technology and packaging techniques, it has now become possible to integrate analog and digital portions of electronic systems into a single chip/package giving rise to mixed-signal Integrated Circuits (ICs) and Multi-Chip Modules (MCMs). The test cost of these mixed-signal ICs and MCMs can be as much as 45% of the total manufacturing cost. The testing of these mixed-signal ICs and MCMs is more difficult than the testing of a purely digital or analog systems. This is because testing of digital and analog circuits have evolved along different paths and the test requirements are different. Digital circuits are tested based on a fault model (stuck at 1/0, bridging faults

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etc.) while analog circuits are tested for their performance specifications such as gain, slew-rate and rise-time (specification testing). Another significant problem in the testing of mixed signal devices is the large amount of simulation time required for fault simulation of these systems. Analog circuits have long simulation times due to the lack of an efficient analog fault simulator. Also, the number of failure modes for an analog circuit is far greater that for a digital circuit of similar size. Another significant problem is that current testing practice gives no way of diagnosing the failures in mixed-signal circuits. The test problem is further complicated by factors like limited accessibility to internal nodes, restricted pin counts of the associated modules, and the need for complex and expensive mixed-signal testers. G. W. Roberts [58] has given a review of the techniques for testing of mixed-signal devices. Some of the early techniques for mixed-signal testing was aimed at testing of specific devices like CODECs, [59] AID converters [60] and ISDN devices [61]. Another approach to testing mixed-signal devices has been the evolution of Design-For-Testability (DFT) rules [62-64] which allow for structured testing of different parts of the system via access to internal nodes of the system through multiplexers and switches. This allows the mixed signal systems to be partitioned into its analog and digital parts and the partitions are tested separately. These techniques have been formalized recently into a mixed signal test bus standard 1149.4 [65-68]. The standard uses testability infrastructure for digital modules defined in the IEEE 1149.1 test bus standard [71] and two additional analog test buses for accessing the internal modules of the system. The standard applies mainly to DC and low-frequency parametric measurements for printed circuit boards rather than highspeed performance measurements, due to the parasitics of the long test buses. Attempts

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have been made to overcome this limitation by the use of iterative deconvolution [69] and undersampling [70]. However, measuring high-speed signals using an analog test bus remains an extremely difficult task. Also, the additional overhead required by these (DFT) techniques cannot be justified for many mixed-signal designs [67]. Another approach to mixed signal testing has been to consider the mixed-signal system as a whole and to generate tests for the whole system. A. F. Alani et. al. [72] have used a digital test generator and the ideal inverse function of an A/D converter, to generate analog stimuli to test for digital faults in a mixed-signal circuits. B. Ayari et. al. [74] have presented an approach to test generation using an existing digital test generator along constraints on the digital test generator to generate only test vectors that can be back-traced to the analog inputs. A. Balivada et. al. [73] have investigated the effects of manufacturing tolerances of analog components on detectability of digital faults. Unlike digital circuits, the outputs (performance) of analog circuits cannot be specified exactly, but vary within a prescribed range due to the manufacturing tolerances of analog components. This uncertainty can make some of the faults in digital partitions of the circuit driven by analog partitions, undetectable. Under these conditions, the notion of hamming distance (the count of the number of bits that are different, between two digital words) usually used for detection of digital faults is no longer sufficient. (A change of 1 Least Significant Bit (LSB) can cause all the bits of a digital word to change 011... 1 100... 0). To overcome this deficiency Balivada et. al. [73] introduced the concept of arithmetic distance (i.e. the arithmetic difference between the measured digital word and the expected nominal digital word) for fault detection. The same concept of arithmetic distance has been used in the proposed methodology.

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For fault simulation of these mixed signal systems, N. Nagi et. al. [75] have presented a behavioral simulation methodology for linear mixed-signal systems which uses z-domain representation of the analog and digital parts of the circuit to aid fast fault simulation. J. Hou et. al. [141-142] have presented a novel fault simulation technique for mixed-signal circuits that extends the ideas of concurrent fault simulation of digital circuits, to the analog and mixed-signal domain. This technique uses redundancies in circuit equations for analog circuits, while simulating a large number of faulty circuits that have a similar structure. These fault simulation techniques try to reduce the time required for fault simulation of mixed-signal systems by reducing the time for a single full circuit simulation. In this research, a methodology for evaluating the fault effects in a mixed-signal system without simulating the entire circuit for every fault is presented. The approaches to testing of mixed signal testing described above do not address the problem of mixed-signal fault simulation and fault isolation. Although there has been a lot of research into the fault isolation and diagnosis for purely analog circuits, there has been little work on diagnosis or fault isolation for mixed-signal systems. In the proposed methodology, the aim is to distinguish between faults in the analog and digital parts of the system, while using a minimum of simulation effort. This would be useful for repair as analog and digital parts of the system are often on different ICs. Another potential use of this information would be for process monitoring. Once the fault has been isolated to the analog or digital part of the circuit, any of the well-known techniques specialized for fault diagnosis for analog or digital circuits can be used for further fault isolation, if so desired.

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The rest of the chapter is organized as follows. In Section 7.2, an overview of the proposed approach is presented. In Section 7.3, some of the fault models used analog and digital circuits are described. In Section 7.4, the fault modeling methodology is described in detail. In Section 7.5, a test circuit for the proposed methodology and give some results for this test circuit are presented. In Section 7.6, the algorithms for fault isolation are presented. The results for applying the proposed methodology to a charge-pump PLL are given in Section 7.7. A summary of the chapter is presented in Section 7.8.

7.2 Overview
The large number of faults in mixed-signal circuits and the lack of efficient mixed-signal fault simulators has made the task of fault simulation of large mixed signal circuits an extremely difficult task. In this chapter, a novel methodology for fast fault simulation in mixed-signal systems without resorting to expensive serial mixed-signal simulation of every fault, is presented. The technique is based on partitioning the circuit and representing the fault effects on a partition of the Circuit-Under-Test (CUT) using a voltage source added to the output of the partition. This is illustrated in Figure 7.1. Fault simulations of

^v

Partition of Circuit (faulty)

^ ^

Good waveform Observed waveforms u n d e r fault

U
^"\
Partition of Circuit (fa u It-free) Observed waveforms u n d e r fault

-ii

E rror Waveforms

Figure 7.1 Representation of fault effects using error waveforms

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the partitions of the circuit are performed using the fault-free input waveforms and the difference between the faulty and fault-free waveforms (error waveforms) at the output of each partition are recorded. The following aspects of the above fault modeling problem are investigated: 1. To find the smallest set of error waveforms for each partition that adequately characterizes all fault effects at the partition outputs and simulate the mixed-signal system for only a few representative fault effects. 2. To determine how the error waveforms are different for different analog and digital faults in the CUT, so that during fault isolation can be performed during specification testing.
Fault Dictionary construction Circuit Netlist, Specifications' Outputs Partition Circuit, Record Fault-free Waveforms Fault Simulate Partitions, Compute Error Waveforns Compute Fault Syndromes Find Rep. Faults | Rep. Faults Isolate Fault to Analog/Digital part of CUT Fault Dictionary CUT Fault Isolation Strategy

Measure Output and Compute Fault Syndromes

Compute Fault Dictionary for Rep. Faults

Figure 7.2 Fault Simulation methodology

The overall flow of the fault simulation methodology is shown in Figure 7.2. As the first step, the circuit is partitioned and the waveforms at inputs and outputs of every partition are recorded. The partitioning is performed such that the digital and analog portions of the CUT are in different partitions, as far as possible, to avoid the use of slow, mixed-

138

signal simulators. Next, fault simulation of the partitions of the CUT are performed and the error waveforms at the outputs of every partition of the CUT is recorded. Then, a. fault syndrome is extracted from each error waveforms using a statistical signal processing technique, namely, Linear Predictive Coding (LPC). These fault syndromes are then clustered into a few representative fault effects and the mixed signal system is simulated for one representative fault from each fault cluster. It is shown that large number of faults can be represented by a few fault syndromes. Finally, error waveforms at the primary (observable) output of the CUT are computed and fault syndromes are extracted from the output error waveforms. These fault syndromes represent a fault dictionary for the CUT and fault isolation to different partitions of the CUT is performed using this fault dictionary. Fault isolation capability using a simple fault isolation strategy, i.e. the nearest neighbor approach, is demonstrated

7.3 Fault Models

Faults in analog circuits can be classified into parametric and catastrophic faults. Parametric faults are caused by process variations like mask mis-alignments, line width variation, variation in doping levels etc. in an IC manufacturing process. They cause degradation in performance of the circuit without total failure of circuit functionality. The parametric faults for an analog circuit are difficult to enumerate because of the continuous nature of these faults. They often cause variation in multiple parameters of the CUT. Catastrophic faults are caused by local process defects like oxide pin-holes, extra metal etc. They may cause the circuit functionality to fail completely. An analog circuit usually has

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only a few catastrophic faults. These can be deduced using techniques such as Inductive Fault Analysis [59]. Faults in digital circuits, on the other hand, are usually caused by process defects. There are well-accepted fault models for failure modes in digital circuits, (stuck-at, bridging, etc.) which helps to create a fault list for any given digital circuit. It is assumed that a list of all the failure modes for the digital parts of any mixed-signal system can be constructed.

7.4 Fault Effect Characterization and Fault Clustering

In the fault simulation approach developed, the fault effects in a module are modeled by an error waveform added at the output of the module. In general, no two faults will have the same exact error waveforms. However, a large number of error waveforms very similar in terms of properties like wave shape. Therefore, the fault effect characterization technique should be able to represent commonly used waveforms such as single or multiple sine-waves, pulses, decaying exponentials, etc. with only a few coefficients. The idea is to represent a large number of faults with a few fault syndromes while retaining enough of the features of the error waveforms to be able to isolate faults. Linear Predictive Coding (LPC) is a statistical signal processing technique which has the above property. Therefore, LPC was used to characterize error waveforms at outputs of partitions.

7.4.1 Fault Syndrome Extraction Using LPC As discussed in Section 7.2, the main difficulty in fault simulation of mixed-signal systems is the large number of faults to be simulated. It is shown that the large number of faults can be compressed to a few fault syndromes using LPC.

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LPC has been a well known technique in data compression [134] with wide range of applications in speech and image processing. LPC models the data as the output of a digital all-pole filter driven by a random input. LPC takes advantage of the correlations that exist between samples of the input data to predict the next value of the input. The estimate of the n input would be

yn

= a

\yn-\

+a

iyn-\

v-/>

C7-1)

where p is the order of prediction. The prediction error is calculated as = (yn-yn) -The coefficients a,- are chosen to minimize the average squared prediction

error. The coefficients af- of the filter now form a model for the input data. More details of this technique can be found in [134]. The coefficients at can vary over a wide range, which is not a desirable property for a fault syndrome. Therefore, the coefficients a, are transformed into reflection coefficients or partial correlation coefficients Tj. The reflection coefficients are always scaled to be between -1 and 1. The transformation [a,-] => [ryi [134] is reversible and both sets of coefficients represent the same information. The transformation is done only to make the fault syndromes properly scaled. The coefficients r , form the fault syndrome for any fault.

7.4.2 Fault Syndrome Clustering

As discussed in Section 7.4.1, for each fault, a fault syndrome is computed using LPC. These fault syndromes consist of k LPC coefficients. Each fault now represents a point in k dimensional space of fault syndromes. If two faults have fault syndromes which are close to each other, they can be collapsed into a single faulty behavior. A similarity mea-

141

sure between the fault syndromes was used to collapse or cluster two faults together. In this work, the first six LPC coefficients have been used as the basis for clustering. It is found to give good amount of compression, reducing the simulation effort while retaining enough features for fault isolation. The procedure for fault clustering is given below. This Procedure for fault clustering Begin 1.Start two clusters with the two furthest points in the dictionary. 2.Classify all points to the nearest of the existing clusters. 3.Compute distances of each point from the cluster centroid. 4.1f (Distance of points from cluster centroids >=threshold) start new cluster with furthest point. Go to 2 end if end.

is similar to the algorithm proposed by Chakrabarti et. al. [27].

7.5 Case Study

AntiAnalog Input Aliasing Filter ADC Filter Digital

Digital Output

Figure 7.3 Example circuit The fault simulation methodology is demonstrated for the mixed-signal circuit shown in Figure 7.3. The circuit consists of an analog biquadratic filter, an A/D converter, and a digital filter. The circuit is divided into three partitions the analog filter, the A/D converter and the digital filter. The analog filter performs the function of anti-aliasing. The A/

142

D converter is an algorithmic A/D converter [124] shown in Figure 7.4(a). The A/D con-

Figure 7.4 (a)Anti-Aliasing Filter (b) A/D converter and (c) Digital Filter verter was implemented at the behavioral level using SpectreHDL, [137] the behavioral modeling language available in the Cadence design environment. The digital filter as shown in Figure 7.4(b) was implemented using gates and registers with fixed-point, two's compliment arithmetic. The analog circuit is assumed to be tested for specifications. Only a single specification, the a.c. gain at a test frequency of 3.7695 kHz, is considered for demonstrating the capabilities of the proposed algorithm. 512 samples of the output were taken for measuring the specification and therefore, the test frequency was chosen to be 193/512 of the sampling frequency (10 kHz). The input frequency is chosen such that a whole number of periods of the input waveform is captured and the output samples are not repeated. The fault-free response of the system at the output of the digital filter is shown in Figure 7.5. For the analog filter, the fault included catastrophic faults (opens/shorts) to the

Time (sec)

Frequency

(a)

(b)

Figure 7.5 (a)Fault-free response of system, (b) FFT of Fault-free passive components and in the op-amp, and multiple parametric variations in the different

143

analog components in the analog filter. For the A/D converter faults in the Comparator, the gain stages and stuck-at faults in the output bits, were simulated. For the digital filter stuck-at faults in the various gates of the circuit were simulated.

7.5.1 Results
M w - r V, .J >V A A. JW*WHH
V.

. , .

vy

lime(sec) (a)Fault in Analog Filter

Yime(sec) (b) Fault in A/D Converter

time (sec.) (c) Fault in Digital Filter

Figure 7.6 Error waveforms for (a) Biq Filter (b) A/D converter and (c) Digital filter

For the biquadratic filter and the A/D converter, two cases are considered: (i) when the faults are caused by the variation of process parameters of the CUT (parametric faults) and (ii) when the faults are caused by local process defects (catastrophic faults). In the case of parametric faults, it is not possible to simulate all possible faults. Therefore a fault sampling algorithm was used. The process parameters are varied according to process statistics and N random faults were generated. The error waveforms for the faults were computed and the fault syndromes were clustered using the algorithm described in Section 7.4.2. Now, a new set of random faults were injected into the CUT and the fault syndromes were computed for the new faults. If the new fault syndromes fall into the precomputed fault clusters, all types of faulty behavior is assumed to have been found. If the new set of faults fall into new fault clusters, the process is repeated till all types of faulty behavior is found. The catastrophic faults considered for the analog filter and A/D con-

144

verter consisted of shorts and opens in the components of the filter and A/D converter. All catastrophic faults for the analog filter and A/D converter were simulated. Parametric faults considered were single and multiple parametric variations that caused the specifications of the circuit to be violated. Example error waveforms for the Biquadratic filter and A/D converter and Digital filter are shown in Figure 7.6. The first 3 LPC coefficients for the analog filter and A/D converter are shown in Figure 7.7. The fault syndromes are shown with a '+' and the centroids of each fault cluster is marked with an 'o'. The fault clusters for the digital filter are shown

Figure 7.7 Fault Syndromes for (a) Biquad filter and (b) A/D Converter

Figure 7.8 Fault syndromes for digital filter in Figure 7.8. Only a few representative fault clusters are shown for the case of the digital filter because of the large number of faults. The results for fault clustering is shown in Table 7.1. The last column gives the ratio of total number of faults to the number of fault

145

syndromes. The full circuit is simulated for only one representative fault from each fault cluster for the ADC and analog filter (i.e.41 faults). It is seen that significant reduction in simulation time is obtained for the circuit.
Table 7.1: Results for fault clustering partition Biq. filter ~ ADC Digital filter No of faults injected 215 30 1830 No of clusters 30 11 572 Compression 7.17 2.73 3.20

7.6 Fault Isolation

The fault isolation problem is formulated as follows: Given the fault syndromes at the output of the CUT, the fault should be isolated to either the analog or the digital part of the system. This would give a quick fault isolation during specification testing. First, the effect of manufacturing tolerances of analog components on the detectability of faults in the digital filter was studied. Then fault isolation for all detectable faults was attempted. To demonstrate the effectiveness of the fault isolation technique, fault syndromes were computed at the primary output of the example circuit and a fault dictionary was constructed. Then, all the faults in the fault list were injected into the circuit along with random manufacturing tolerances on the analog components of the CUT and fault isolation was attempted using the fault dictionary. The nearest neighbor rule has been used for fault classification.

7.6.1 Effects of Tolerances As explained in Section 7.1, the manufacturing tolerances in the analog filter will render some of the faults in the digital portion of the DUT to be undetectable. It is assumed that

!46

the functional specifications of the analog parts of the CUT is available, which give the limits on the variation of the analog outputs due to tolerance. If the error introduced at the output by any fault is less than this limit, the fault would be undetectable.

In the example circuit, it was assumed that the gain of the filter can vary by 1 %. This, along with the tolerances of the A/D converter, introduces an uncertainty of 1 LSBs for the output of the A/D converter. This makes 237 of the 1830 simulated faults in the digital filter undetectable, for a fault coverage of 87.0%.

7.6.2 Nearest Neighbor Approach

The nearest neighbor rule is one of the simplest of fault isolation algorithms. In this method, the distance of each of the observQd fault syndrome to each of the fault clusters in the fault dictionary is computed. The distances are rank-ordered. The fault is assumed to lie in the module whose fault syndrome it is closest to. If the distances to two clusters was found to be almost equal the fault isolation result is considered ambiguous. To demonstrate the effectiveness of the fault isolation approach, a fault dictionary was built for the example circuit in Figure 7.3. The entire circuit was simulated using only 41 error waveforms for the biquadratic filter and ADC. Now, to verify the effectiveness of the fault isolation algorithm, all the faults in the fault-list of the digital filter were injected into the circuit and fault isolation was attempted. For the analog filter, 415 faults, including faults not simulated during the fault dictionary construction, were simulated. The components in the analog filter and A/D converter were varied randomly within their prescribed tolerance of 1 %. The results for fault isolation

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are given in Table 7. 2. Overall, the algorithm gives correct results 94.5% of the time for
Table 7. 2: Fault diagnosis using nearest neighbor for example circuit module Biquadratic filter Digital filter No of faults 415 1593 Correctly diag 392 1588 Ambiguous 21 5 Misdiagnosed 2 0

the analog filter and 99.7% of the time for the digital filter.

7.6.3 Failures in A D C The ADC in the CUT is a partition that contains closely coupled analog and digital parts. Therefore, it exhibits some failure modes that are similar (in output response) to failures in the analog filter, while some other failure modes exhibit similarity to faults in the digital filter. For failures in ADC, fault isolation was attempted using the fault dictionary constructed for the analog filter and digital filter. The faults in the reference section of the digital filter were diagnosed as analog faults while the faults in the comparator, gain stage and stuck-at faults in the output bits of the A/D converter were diagnosed as digital faults. This gives an analog/digital partitioning of the A/D converter as shown inFigure 7.9. This may be explained as follows. The gain stages and comparator of the A/
Analog Part Digital Part

Comp^Digtal Output

Figure 7.9 Analog/digital partitioning for the A/D converter D converter are part of a tightly coupled feedback loop with digital components in the loop because of the feedback of the output bits to the control of the switch at the input to

148

the gain stages. Therefore, their fault syndromes appear to be similar to that of digital faults.

7.7 Case Study 2: Charge-Pump PLL

The proposed methodology was applied to a charge-pump phase-lock loop (PLL), one of the proposed mixed-signal test benchmarks [138]. The top-level schematic of the PLL is shown in Figure 7.10. The details of each of the sub-circuits of the PLL is shown in
Up

Input

Ref _ Phase

p=S

Charge Pump &

Filter

Out

Fbk Detector Down > >

vco

Figure 7.10 Charge-pump PLL Figure 7.11. The phase detector of the PLL is a digital circuit while the other sub-circuits
VDD

VDD
PREF U

Fbk

Current Ref.
Down

NREF-i Cont

T HL

Y
1

=jy^^

(a)

(b) W

(c)

Figure 7.11 Sub-circuits of PLL (a) VCO (b) Charge Pump and (c) Phase of the PLL are analog in nature. The locking behavior of the PLL for an input frequency of 25MHz was used as the test condition.The fault-free output of the PLL at the node 'out' is shown in Figure 7.12.
149

time (sec)

Figure 7.12 Fault-free output of PLL The VCO converts an input voltage to an output frequency. Therefore, instantaneous frequency of the waveform at the VCO output, computed at every rising edge of the VCO output waveform, was used to compute error waveforms for the VCO. At the output of the phase detector, the information is contained in the widths of the pulses at the output nodes up and down. Therefore, at the phase detector output, the output waveform was computed using the equation

nt) = X A '.. P -I A 'd-

02)

where Atup are the widths of pulses at the node up and Atdown are the widths of pulses at the node down. The fault simulation and fault isolation algorithms proposed in this chapter were applied to the PLL. The results for fault simulation are shown in Table 7. 3. The faults simulated
Table 7. 3: Fault Clustering results for PLL Sub-circuit VCO Charge pump Phase detector No of faults Injected 131 108 21 No. of Clusters 19 15 4 Compression 6.89 7.2 5.25

included opens, shorts and parametric faults in the analog parts of the PLL and stuck-at faults in the digital gates of the phase detector. Fault isolation results for the PLL are

150

shown in Table 7. 4. It is seen that only one of the stuck at faults in the phase detector is
Table 7. 4: Fault isolation using nearest neighbor for PLL module No of faults 131 108 21 Correctly diag 83 81 1 47 26 20 Ambiguous Misdiagnosed 1 1 0

vco
Charge pump Phase detector

identified correctly while all others give ambiguous results. Also, a large number of faults in the VCO and charge pump also give results that are ambiguous. This is because the PLL is a tightly coupled feedback system and any catastrophic fault in the analog section (open or short) or a stuck-at fault in the digital section of the PLL causes complete loss of functionality of the system, i.e. results in the node out being stuck at one of the rail voltages. Therefore, it is difficult to identify the part of the system that has failed from measurements on the output alone. However, it is seen that there is very little mis-classification of failures (less than 1%), which shows that the error waveform methodology is able to capture all the failure modes of the PLL while requiring only a fraction of the simulation effort required for full circuit simulation.

7.8 Summary
In this chapter, a fast fault simulation methodology for mixed-signal systems was presented. The approach is found to give significant speed-up in the fault simulation of mixed-signal systems. Methods for distinguish fault syndromes of analog and digital partitions of the circuit have been introduced. The technique gives robust performance in the presence of analog component tolerances.

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CHAPTER VIII CONCLUSIONS AND FUTURE WORK

In this dissertation, a comprehensive methodology for fault diagnosis on analog and mixed-signal circuits has been presented. The fault diagnosis algorithms presented in Chapter II give a theoretical framework for the dissertation. The effect of measurement noise on the accuracy of diagnosed parameters, was quantified and a novel algorithm for the identification of ambiguity groups was presented. Algorithms to minimize the number of test points that need to be accessed for diagnosing the parameters of an analog circuit and techniques to minimize test time, were presented. In Chapter III, a novel algorithm to automatically generate optimized test stimuli to aid the diagnosis of parametric failures in analog circuits, was presented. The automatic test optimization algorithm, based on genetic optimization, was shown to generate efficient, effective test stimuli for the diagnosis of parametric faults in analog circuits. In Chapter IV, the algorithms developed in Chapter II and Chapter III were applied to the problem of diagnosing yield problems in analog ICs. A comprehensive fault modeling methodology, including the effects of intra-IC mismatches in analog parameters was presented. A novel algorithm to analyze the contribution of variation in individual parameters to the variation in the performance parameters was presented. The algorithm, which uses a general non-linear model, is able to diagnose the effects of interactions between different

152

parameters. The algorithm was applied to the problem of diagnosis of yield problems in an operational amplifier obtained from industry. In Chapter V, the diagnosis algorithms were applied to the problem of test time reduction for ADCs. The methodology was shown to give an order of magnitude reduction in test time for ADCs compared to methodologies practiced in industry. The algorithms were verified using both simulations and hardware measurements on a commercially available 8-bit ADC. In Chapter VI and Chapter VII, algorithms to extend the diagnosis algorithms to larger systems were described. In Chapter VI, a fault isolation technique for mixed-signal boards was presented. The technique, that depends on modeling the fault-free behavior of the CUT, was shown to be robust under the presence of un-modeled failures and manufacturing tolerances of analog components. In Chapter VII, a novel technique for separating analog and digital faults in mixed-signal systems, was presented. The technique, based on error waveforms, was shown to be effective in separating analog and digital failure modes.

8.1 Future Work

The diagnosis methods described in this dissertation depend on the availability of accurate simulation models for the circuits being tested. These simulation models may not be available, or may be too inaccurate for the purpose of accurately computing the parameters of the circuit being tested. Therefore, a simulation normalization technique, for normalizing a set of circuit simulations using measured data from a set of circuits will be needed. P. Variyam and A. Chatterjee [102] have used a similar technique for fast, tran-

153

sient testing of analog circuits. It may be possible to extend this methodology for diagnosis in analog circuits. The test optimization strategy, presented in Chapter III, takes a few hours of computer simulation for generating tests for amplifiers and filters. The simulation complexity for larger circuit blocks such as ADCs and PLLs would be prohibitive. Therefore, more efficient algorithms for fault simulation will be needed to automatically generate tests for complex mixed-signal circuits. J. Hou and A. Chatterjee [141-142] have presented concurrent fault simulation algorithms for mixed-signal circuits that give significant improvements in simulation times, compared to conventional circuit simulators such as SPICE. The use of concurrent fault simulation in test generation for analog circuits needs to be investigated.

The fault isolation algorithm, described in Chapter VII, assumed that either the digital or the analog portion of the mixed signal circuit being tested was faulty. In complex mixed-signal circuits, a large number of failures occur due to the interaction between analog and digital circuits. Failures in analog circuits caused by digital switching noise is an example of such a failure. More investigation into the classification of such failure modes is needed for a comprehensive solution.

154

References
Diagnosis for Analog Circuits

[1] J. W Bandler and A. E. Salama, "Fault Diagnosis of Analog Circuits," Proceedings, IEEE, Volume. 73, August 1985, pp. 1279-1326. [2] J. W Bandler and A. E. Salama, "Recent Advances in Fault Location of Analog Networks," Proceedings, IEEE International Symposium on circuits and systems, 1984, pp. 660-663.

[3] R. W. Liu, "Selected Papers on Analog Fault Diagnosis," IEEE press,

1987.

[4] R. W. Liu, "Testing and Diagnosis of Analog Circuits and Systems," Van Nostrand Reinold, 1991. [5] M. Slamani and B. Kaminska, "Analog Circuit Fault Diagnosis based on Sensitivity Computation and Functional Testing", IEEE Design &Test of Computers, Volume. 9, No. 1, March 1992, pp. 30-39. [6] N. B. Hamida, K. Saab, D. Marche, B. Kaminska and G. Quesnel, "LIMSoft: Automated Tool for Design and Test Integration of Analog Circuits," Proceedings, International Test Conference, 1996, pp. 571-580. [7] A. Walker, W. E. Alexander and P. K. Lala, "Fault Diagnosis in Analog Circuits Using Element Modulation," IEEE design & test of computers, Volume. 9, No. 1, March 1992, pp. 19-29.

[8] A. Walker, W. E. Alexander and P. K. Lala, "A Technique for Analogue Fault Diagnosis Using Element Modulation," Proceedings, Asilomar Conference on Conference on Signals, Systems and Computers, pp. 1255-1259. [9] S. L. Farchy, E. D. Gadzeva, L. H. Raykovska and T. G. Kouyoumdijev, "NullatorNorator Approach to Analog Circuit Fault Diagnosis Using General-Purpose Analysis Programs," International Journal of Circuit Theory and Applications, Volume 23, 1995, pp.571-585. [10] H. Dai and M. Sounders, "Time Domain Testing Strategies and Fault Diagnosis for Analog Systems," IEEE transactions on Instrumentation and Measurement, Volume. 39, No. 1, February 1990, pp. 157-162. [11] N. Sen and R. Saeks, "Fault Diagnosis for Linear Systems via Multi-Frequency Measurements," IEEE transactions on circuits and systems, Volume. CAS-26, July 1979, pp. 440-457. [12] W. G. Lou, S. W. Zhang, "Multi-fault Diagnosis of DC-Nonlinear Analog Circuits," Proceedings, IEEE International Symposium on Circuits and Systems, 1988, pp. 1171-1174. [13] L. Rapisarda and R. A. Decarlo, "Analog Multi-Frequency Fault Diagnosis," IEEE transactions on Circuits and Systems, Volume CAS--30, April 1983, pp. 223-234. [14] S. Cherubal and A. Chatterjee, "Parametric Fault Diagnosis for Analog Systems Using Functional Mapping," Proceedings, Design Automation and Test in Europe Conference, 1999, pp. 195-200.
ii

[15] R. M. Biermacki and J. M. Bandler, "Multiple Fault Location of Analog Circuits", IEEE transactions on Circuits and Systems, Volume CAS-28, No. 5, 1981, pp. 361367. [16] D. Reisig, R. DeCarlo, "Multiple Fault Diagnosis for Analog Digital Circuits," Proceedings, IEEE International Symposium on Circuits and Systems, 1986, pp. 12571260. [17] Chwan-Chia Wu, K. Nakajima, C. L Wey and R. Saeks, "Analog Fault Diagnosis with Failure Bounds," IEEE transactions on Circuits and Systems, Volume C AS-29, No. 5, May 1982, pp. 277-284. [18] C. L. Wey and S. Krishnan, "Built-in Self-Test (BIST) Structures for Analog Circuit Fault Diagnosis with Current Test Data," IEEE Transactions on Instrumentation and Measurement, Volume 41, No. 4, August 1992, pp. 535-539. [19] C. L. Wey, "Built-in self-test (BIST) Structure for Analog Circuit Fault Diagnosis," IEEE Transactions on Instrumentation and Measurement, Volume 39, No 3, June 1990, pp. 517-521. [20] A. E. Salama, J. A. Starzyk and J. W Bandler, "A Unified Approach for Fault Location in Large Analog Circuits," IEEE transactions on Circuits and Systems, Volume CAS-31, No. 7, July 1984, pp. 609-622. [21] R. Spina and S. Upadhyaya, "Linear Circuit Fault Diagnosis using Neuromorphic Analyzers," IEEE transactions on Circuits and Systems-II: analog and digital signal processing, Volume. 44, No. 3, March 1997, pp. 190-196.
iii

[22]

S. Somayajulam, E. Sanchez-Sinencio and J. P. de Gyvez, "A Neural Network Approach to Hierarchical Analog Fault Diagnosis" Proceedings, A UTOTESTCON, 1993,pp. 699-703

[23] S. S. Somayajulam, E. Sanchez-Sinencio and J. P. de Gyvez, "Power Supply Ramping and Current Measurement Based Technique for Analog Fault Diagnosis," Proceedings, IEEE VLSI test symposium, 1994, pp. 234-239. [24] Z. You, E. Sanchez-Sinencio and J. P. de Gyvez, "Analog System-level Fault Diagnosis Based on a Symbolic Method in the Frequency Domain," IEEE transactions on Instrumentation and Measurement, Volume 44, No. 1, February 1995, pp. 28-35. [25] B. H. Lin, S. H. Shieh, C. W. Wu, "Efficient Multi-Frequency Analysis of Fault Diagnosis in Analog Circuits Based on Large Change Sensitivity Computation," Proceedings, Asian Test Symposium, 1996, pp. 232-237. [26] R.Voorakaranam, S. Chakrabarti, J. Hou, A. Gomes, S. Cherubal and A. Chatterjee, "Hierarchical Specification-Driven Analog Fault Modeling for Efficient Fault Simulation and Diagnosis" Proceedings, International Test Conference 1997, pp. 903912. [27] S. Chakrabarti and A. Chatterjee, "Compact Fault Dictionary Construction for Efficient Isolation of Faults in Analog and Mixed-signal Circuits," Proceeding of Advanced Research in VLSI conference, 1999, pp. 327-341.

[28] B. R. Epstien, M. Czigler, "Fault Detection and Classification in Linear Integrated Circuits: An Application of Discrimination Analysis and Hypothesis Testing," IEEE transactions on Circuits and Systems, Volume 12, No. 1, 1993, pp. 102-113. Process Diagnosis and Yield Management

[29]

D. A. Hanson, R. J. G. Doossens, M. Redford, J. McGinty, J. K. Kibarian, K. W. Michaels, "Analysis of Mixed-Signal Manufacturability with Technology CAD (TCAD)," IEEE Transactions on Semiconductor Manufacturing, Volume. 9. No. 4, November 1996, pp. 478-488.

[30] D. A. Henson, H. S. Cheng, D-B Kao, J. K. Kibarian, K. W. Michaels, "Analysis of the Controllability of a Sub-Micron CMOS Process Using TCAD," Proceedings, International Symposium on Semiconductor Manufacturing, 1994, pp. 85-89. [31] M. Miyamo, S. Kamohara, K. Okuyama and Y Oji, "Parametric Yield Enhancement System via Circuit Level Device Optimization Using Statistical Simulation," Proceedings, IEEE Symposium on VLSI Circuits, 2001, pp. 163-166. [32] J. Cheng, "E-T Based Statistical Modeling and Compact statistical Circuit Simulation Methodologies," Proceedings, IEEE Electron Devices Meeting, 1996, pp. 635638. [33] S. H. Lee, D. Y Lee, T. J. Kwon, J. H. Lee and Y K. Park, "An Efficient Statistical Model Using electrical Tests for GHz CMOS Devices,"

[34] C. J. B. Spanos and S. W. Director, "Parameter Extraction for Statistical IC Process Characterization", IEEE transactions on Computer-aided Design, Volume. CAD-5, No. 1, January 1986, pp. 66-78. [35] K. K. Low and S. W. Director, "An Efficient Methodology for Building Macromodels of IC Fabrication Processes," IEEE transactions on Computer-Aided Design, Volume. 8, No. 12, December, 1989, pp. 1299-1313. [36] M. Qu and M. A. Styblinski, "Parameter Extraction for Statistical IC Modeling Based on Recursive Inverse Approximation," IEEE transactions on Computer-aided Design, Volume. 16, No. 11, November 1997, pp. 1250-1259. [37] A. C. Carlson, S. L. Sundaram, "Statistical Approach for Improving Manufacturing Yield in Advanced IC fabrication," Proceedings, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 1991, pp. 25-29. [38] J. K. Kibarian and A. J. Strojwas, "Diagnostic System for IC Manufacturing," IEEE/ SEMI Advanced Semiconductor Manufacturing Conference, 1991, pp. 98-103. [39] C. N. Berglund, "A Unified Yield Model Incorporating Both Defect and Parametric Effects," IEEE Transactions on Semiconductor Manufacturing, Volume. 9, No. 3, August 1996, pp. 447-454. [40] E. A. Rietman, S. A. Whitlock, M. Beachy, A. Roy and L. Willingham, "A System Model for Feedback Control and Analysis of Yield: A Multistep Process Model of Effective Gate Length, Poly Line Width, and IV Parameters," IEEE Transactions on Semiconductor Manufacturing, Volume. 14, No. 1, February 2001, pp. 32-45.
vi

[41] A.Y. Wong, "A Statistical Approach to Identify Semiconductor Process Equipment Related Yield Problems," Proceedings, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1997 pp. 69 -73. [42] A. Y. Wong, "A Statistical Parametric Probe Yield Analysis Methodology," Proceedings, International Symposium on Defect and Fault Tolerance in VLSI Systems, 1996, pp. 131-139. [43] A. Y. Wong, "A Systematic Approach to Identify Critical Yield Sensitive Parametric Parameters," Proceedings, 2nd International Workshop on Statistical Metrology, 1997,pp.56-61. [44] F. Recio et. al, "The 100% Yield Explanation Methodology at Lucent Technologies Madrid," IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 2000, pp. 26-32. [45] D. Malinaric, R. R. Hoffmeister, C. Sum, "Case Study for Root Cause Analysis of Yield Problems," Proceedings, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 2000, pp. 8-13. [46] J. Park, R. Kittler, B. Hopper, P. Wen, "Advanced Methods for Analysis of Waferto-Wafer Yield Problems," Proceedings, IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 1997, pp. 62-65. [47] J. K. Kibarian and A. J. Strojwas, "Using Spatial Information to Analyze Correlations Between Test Structure Data," Proceedings, IEEE International Conference on Microelectronic Test Structures, 1990, Volume 3, pp. 187-191.
vii

[48] J. K. Kibarian and A. J. Strojwas, "Using Spatial Information to Analyze Correlations Between Test Structure Data," IEEE Transactions on Semiconductor Manufacturing, Volume. 4 No. 3, August 1991, pp. 219-225 Circuit Simulation/Modeling

[49] S.W Director and P. Feldmann, "Statistical Integrated Circuit Design," IEEE Journal of Solid-State Circuits, Volume. 28, No. 3, March 1993, pp. 193-202. [50] C-Y Chao and L. S. Milor, "Performance Modeling Using Additive Regression Splines," IEEE Transactions on Semiconductor Manufacturing, Volume. 8, No. 3, August 1995. [51] L. S. Milor and S. Vincentelli, "Minimizing the Production Test Time to Detect Faults in Analog Circuits," IEEE Transactions on Computer-Aided Design, Volume. 13, No. 6, June 1994, pp. 796-813. [52] D. S. Gibson, R. Poddar, G. S. May and M. A. Brooke, "Using Multivariate Nested Distributions to Model Semiconductor Manufacturing Processes," IEEE Transactions on Semiconductor Manufacturing, Volume. 12, No. 1, January 1999, 54-65. [53] D. S. Gibson, R. Poddar, G. S. May and M. A. Brooke, "Statistically Based Parametric Yield Prediction for Integrated Circuits," IEEE Transactions on Semiconductor Manufacturing, Volume. 10, No. 4, November 1997, 445-458.

Vlll

[54]

C. Michael and M. Ismail, "Statistical Modeling of Device Mismatch for Analog MOS Integrated Circuits," IEEE Journal of Solid-State Circuits, Volume. 27, No. 2, February 1992, pp. 154-165.

[55] K. S. Eshbaugh, "Generation of Correlated Parameters for Statistical Circuit Simulation," IEEE Transactions on Computer-Aided Design, Volume. 11, No. 10, October 1992, pp. 1198-1206. Diagnosability/Testability [56] V. Visvanathan and A. Sangiovanni-Vincentelli, "Diagnosability of Nonlinear Circuits and Systems," IEEE transactions on Circuits and systems, Volume CAS-28, pp. 1093-1102, 1981. [57] V. Visvanathan and A. Sangiovanni-Vincentelli, "A Computational Approach for the Diagnosability of Dynamical circuits," IEEE transactions on Computer-Aided Design, 1984, Volume. 3, pp. 165-171. Mixed-signal Test [58] G. W. Roberts, "Metrics, Techniques and Recent Developments in Mixed-signal Testing," Proceedings, IEEE/ACM International conference on Computer aided Design, 1996 pp. 514-521. [59] D.K. Shirachi, "Codec Testing Using Synchronized Analog and Digital Signals," IEEE Design and Test of Computers, June 1985 pp. 56-63. [60] R. Kramer, "Testing of Mixed-signal Devices," IEEE Design and Test of Computers, April 1987, pp. 12-16.

ix

[61]

K. Lanier, "ATE-based Functional Testing of ISDN," Proceedings, International Test Conference, 1990, pp. 86-94.

[62]

K. D. Wagner and T. W. Williams, "Design for Testability of Mixed-signal Integrated Circuits," Proceedings, International test conference, 1988, pp. 823-828

[63]

E. J. Perelias, A. Rueda, J. L. Huertas, "A DFT Technique for Analog-to-Digital Converters With Digital Error Correction," Proceedings, IEEE VLSI Test Symposium, 1997,pp302-307.

[64] M. Jarwala and S. J. Tsai, "A Framework for Design for Testability of Mixed-signal Integrated Circuits," Proceedings, custom integrated circuits conference, 1991, pp. 13.5.1-13.5.4 [65] A. Cron, "PI 149.4 Mixed-signal Test Bus," IEEE design and test of computers, fall 1996, pp. 98-101. [66] K. Lofstrom, "A Demonstration IC for the PI 149.4 Mixed-signal Test Standard," Proceedings, International Test Conference, 1996, pp. 92-98. [67] S. Sunter, "Cost/Benefit Analysis of the P1149.4 Mixed-signal Test Bus," IEE Proceedings- Circuits, Devices and Systems, Volume. 143, No. 6, December 1996, pp393-398. [68] A. Cron, "PI 149.4 Mixed-signal Test Bus," IEEE Design and Test of Computers, Fall 1996, pp. 98-101.

[69] C. Su, T. Chen and S. J. Jou, "Parasitic Effect Removal for Analog Measurement in PI 149.4 Environment," Proceedings, International Test Conference, 1997, pp499508. [70] R. Mason, S. Ma, "Analog DFT Using an Undersampling Technique," IEEE Design and Test of Computers, Fall 1999, pp. 84-88. [71 ] "IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE standard 1149.1-1990, IEEE Inc., New York, October 1993. [72] A. F. Alani, G. Musgrave and A. P. Ambler, "A Steady State Response Test Generation for Mixed-signal Circuits," Proceedings, international test conference, 1992, pp415-421 [73] A. Balivada, A. Chatterjee, N. Nagi and J. A. Abraham, "Unified Approach for Fault Simulation of Linear Mixed-signal Circuits" Journal of Electronic Testing, Theory and Applications, Aug.-Oct. 1996, pp. 29-41. [74] B Ayari, N. B. Hamida and B. Kaminska, "Automatic Test Vector Generation for Mixed signal Circuits," Proceedings, European Design and Test Conference, 1995, pp. 458-463 [75] N. Nagi, A. Chatterjee and J. Abraham, "MIXER: Mixed-signal Fault Simulator," Proceedings, International Test Conference, 1993, pp. 568-571. Analog-to-Digital Converter Test

XI

[76] P. D. Capofreddi and B. A. Wooley, "The Use of Linear Models in A/D Converter Testing," IEEE transactions on Circuits and Systems- I: Fundamental Theory and Applications, Volume. 44, No. 12, December 1997, pp. 1105-1113. [77] P. D. Capofreddi and B. A. Wooley, "The Use of Linear Models for the Efficient and Accurate Testing of A/D Converters," Proceedings, IEEE International Test Conference, 1995, pp. 54-60. [78] G. N. Stenbakken and T. M. Souders, "Test-Point Selection and Testability Measures via QR Factorization of Linear Models," IEEE Transactions on Instrumentation and Measurement, Volume. IM-36, No. 2. June 1987, pp. 406-410. [79] T. M. Souders and G. N Stenbakken, "A Comprehensive Approach to Modeling and Testing of Mixed-signal Devices," Proceedings, IEEE International Test Conference, 1990, pp. 169-176. [80] G. N. Stenbakken and T. M. Souders, "Linear Error Modeling of Analog and MixedSignal Devices," Proceedings, IEEE International Test Conference, 1991, pp. 573581. [81] G. N. Stenbakken and T. M. Souders, "Developing Linear Error Models for Analog Devices," IEEE Transactions on Instrumentation and Measurements, Volume. 43, No. 2, April 1994, pp. 157-163. [82] T. D. Lyons, The Production Implementation of a Linear Error Modeling Technique," Proceedings, IEEE International Test Conference, 1992, pp. 399-404.

[83] S. Max, "Fast Accurate and Complete ADC Testing," Proceedings, IEEE International Test Conference, 1989, pp. 111-117 [84] S. Cherubal and A. Chatterjee, "Optimal INL/DNL Testing of A/D Converters Using a Linear Model," Proceedings, International Test Conference, 2000, pp. 358366. [85] S. Max, "Testing of High Speed High Accuracy Analog to Digital Converters Embedded in Systems on a Chip," Proceedings, IEEE International Test Conference, 1999,pp.763-771 [86] J. Doernberg, Hae-Seung Lee and D. A. Hodges, "Full-Speed Testing of A/D Converters," IEEE Journal of Solid-State Circuits, Volume. SC-19, NO. 6, December 1984, pp. 820-827. [87] T. Kuyel, "Linearity Testing Issues of Analog to Digital Converters," Proceedings, IEEE International Test Conference, 1999, pp. 747-756. [88] "Definition of Terms A/D Converters," National Semiconductor Data Acquisition Handbook, National Semiconductor, 1995, pp. 2.4-2.5. [89] J. Blair, "Histogram Measurement of ADC Non-linearities Using Sine Waves," IEEE Transactions on Instrumentation and Measurement, Volume. 43, No. 3, June 1994, pp. 373-383. [90] P. Carbone and D. Petri, "Noise Sensitivity of ADC Histogram Test," IEEE Instrumentation and Measurement Technology Conference, 1998, pp. 88-91.

Automatic Test Generation and Measurement Selection [91] N. B. Hamida and B. Kaminska, "Analog Circuit Testing based on Sensitivity Computation and New Circuit Modeling," Proceedings, International Test Conference, 1993, pp.331-343. [92] M. Slamani, B. Kaminska and G. Quesnel, "An Integrated Approach for Analog Circuit Testing with Minimum Number of Detected Parameters," Proceedings, International Test Conference, 1994, pp. 631-640. [93] S. Chakrabarti and A. Chatterjee, "Diagnostic Test Pattern Generation for Analog
Circuits Using Hierarchical M o d e l s , " Proceedings, International Conference on

VLSI Design, 1999, pp. 518-523. [94] S. Chakrabarti and A. Chatterjee, "Partial Simulation-driven Test Generation for Fault Detection and Diagnosis in Analog Circuits," Submitted to International Conference on Computer-Aided Design, 2000. [95] M. J. Marlett and J. A. Abraham, "DC-IATP: An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern Tests," Proceedings, International Test Conference, 1988, pp. 839-845. [96] L. Milor and V. Visvanathan, "Detection of Catastrophic Faults in Analog Integrated Circuits," IEEE Transactions on Computer-aided Design, Volume. 8, 1989, pp. 114-130.

[97] S. Tsai, "Test Vector Generation for Linear Analog Devices," Proceedings, International Test Conference, 1991, pp. 592-597. [98] G. Devarayanadurg and M.Soma, "Analytical Fault Modeling and Static Test Generation for Analog ICs," Proceedings, IEEE/ACM International Conference on Computer-aided Design, 1994, pp. 44-47. [99] G. Devarayanadurg and M. Soma, "Dynamic Test Signal Design for Analog ICs," Proceedings, International Conference for Computer-aided Design, 1995, pp. 627629. [100] H. H. Zheng, A. Balivada and J. A. Abraham, "A Novel Test Generation Approach for Parametric Faults in Linear Analog Circuits," Proceedings, VLSI Test Symposium, 1996, pp. 470-475. [101] N. Nagi, A. Chatterjee, A. Balivada and J.A. Abraham, "Fault-based Automatic Test Generator for Linear Analog Devices," Proceeding of IEEE/ACM International Conference on Computer-Aided Design, pp.88-91, 1993. [102] P. N. Variyam, J. Hou and A. Chatterjee, "Test Generation for Analog Circuits Using Partial Numerical Simulation," Proceedings, International Conference on VLSI Design, 1999, pp. 597-602. [103] P. N. Variyam, J. Hou and A. Chatterjee, "Efficient test generation for transient testing of analog circuits using partial numerical simulation," Proceedings, IEEE VLSI Test Symposium, 1999, pp. 214-219.

[104] R. Voorakaranam and A. Chatterjee, "Hierarchical Test Generation for Analog Circuits Using Incremental Test Development," Proceedings, IEEE VLSI Test Symposium, 1999,pp296-301. [105] R. Voorakaranam and A. Chatterjee, "Feedback driven backtrace of analog signals and its application to circuit verification and test," Proceedings, Conference on Advanced Research in VLSI, 1999, pp. 342-355. [106] P. N. Variyam and A. Chatterjee, "Specification-driven Test Design for Analog Circuits," Proceedings, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 1998. pp. 335-340. [107] P. N. Variyam and A. Chatterjee, "Test Generation for Comprehensive Testing of Linear Analog Circuits Using Transient Response Sampling," Proceedings, IEEE/ ACM International Conference on Computer-Aided Design, 1997, pp. 382-385. [108] P. N. Variyam and A. Chatterjee, "Specification-Driven Test Generation for Analog Circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume. 19, No. 10, October 2000, pp. 1189-1201. [109] R. Voorakaranam and A. Chatterjee, "Test Generation for Accurate Prediction of Analog Specifications," Proceedings, IEEE VLSI Test Symposium, 2000, pp. 137142. [110] W. M. Lindermeir, H. E. Graeb, and K. J. Antreich, "Analog Testing by Characteristic Observation Inference," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume. 18, No. 9, September 1999, pp. 1353-1368.

[Ill] W. M. Lindermeir, "Design of Robust Test Criteria for analog Circuits," Proceedings, IEEE/ACM Conference on Computer-Aided Design, 1996, pp. 604-611. [112] W. M. Lindermeir, "Design Based Analog Testing by Characteristic Observation Inference, Proceedings, IEEE/ACM Conference on Computer-Aided Design, 1995, pp. 620-626. [113] C. Y. Pan and K. T Cheng, "Test Generation for Linear Time-invariant Circuits," IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Volume. 46, No. 5, May 1999, pp. 554-564. [114] A. Y. Gomes and A. Chatterjee, "Minimal Length Diagnostic Tests for Analog Circuits using Test History," Proceedings, Design Automation and Test in Europe, 1999, pp.189-194. [115] S. Cherubal and A. Chatterjee, "Test Generation Based Diagnosis of Device Parameters in Analog Circuits," Proceedings, Design, Automation and Test in Europe, 2001, pp. 596-602, [116] G. N. Stenbakken, M. T. Sounders and G. W. Stewart, "Ambiguity Groups and Testability," IEEE transaction on Instrumentation and Measurement, Volume 38, No 5, October 1989, pp. 941-945. [117] G. N. Stenbakken, M. T. Sounders, "Test Point Selection and Testability Measures via QR factorization of Linear Models," IEEE transaction on Instrumentation and Measurement, Volume 36, No 3, Junel987, pp. 406-410.

xvii

[118] E. Liu, W. Kao, E. Fslt and A. Sangiovanni-Vincentelli, "Analog Testability Analysis and Fault Diagnosis Using Behavioral Modeling," Proceedings, IEEE Custom Integrated Circuits Conference, 1994, pp. 413-416. [119] G. N. Stenbakken and T. M. Souders, "Test-Point Selection arid Testability Measures via QR Factorization of Linear Models," IEEE Transactions on Instrumentation and Measurement, Volume. IM-36, No. 2. June 1987, pp. 406-410. [120] J. van Spaandonk and T. A. M. Kevenaar, "Iterative Test Point Selection for Analog Circuits," Proceeding of the VLSI test symposium, 1996, pp. 66-71 Other References [121] M. Sachdev and B. Atzema, "Industrial Relevance of Analog IFA: A Fact or Fiction," Proceedings, International Test Conference 1995, pp. 61-70. [122] A. Pahwa and R. A Rohrer, "Band Faults: Efficient Approximations to Fault Bands for Simulation Before Fault Diagnosis of Linear Circuits", IEEE transactions on Circuits and systems, Volume. CAS-29, No. 2 pp. 81-88. [123] G. W. Roberts, "DFT Techniques for Mixed-signal Integrated Circuits," Circuits and Systems for the Information AgQ, Short Courses at the 1997 IEEE International Symposium of Circuits and Systems, Chapter 6.2, pp. 251-270. [124] B. Razavi, "Principles of Data Converter System Design," IEEE press, New York, 1995.

xviii

[125] "Definition of Terms A/D Converters," National Semiconductor Data Acquisition Handbook, National Semiconductor, 1995, pp. 2.4-2.5. [126] D. S. Watkins, "Fundamentals of Matrix Computations," John Wiley and Sons, 1991. [127] A. W. Drake, "Fundamentals of Applied Probability Theory," McGraw-Hill, 1967 [128] J. H. Friedman, "Multivariate Adaptive Regression Splines," The Annals of Statistics, Vol 19, No. l,pp. 1-141. [129] G. E. Box, W. G. Hunter, J. S. Hunter, "Statistics for Experimenters: An Introduction to Design, Data Analysis and Model Building," Wiley, New York, 1978. [130] J. M. Ortega and W C. Rheinbolldt, Iterative Solution of Nonlinear Equations in Several Variables, New York, Academic, 1970. [131] S. Dowdy and S. Wearden, "Statistics for Research," John Wiley and Sons, New York, 1991. [132] G. Karypis, V. Kumar and Shashi Shekhar, "Multilevel Hypergraph Partitioning: Applications in the VLSI Domain," Proceedings, Design Automation Conference, 1997, pp. 526-529 [133] D. E. Goldberg, Genetic Algorithms in Search, Optimization and Machine Learning, Addison-Wesley, Massachusetts, 1989.

[134]

S. Saito and K. Nakata, "Fundamentals of Speech Signal Processing," Academic press, 1995

[135] AN-146: The Phase Locked Loop IC as a Communication System Building Block, National Semiconductor Application Notes, at http://www.national.com/apnotes/ an_Linear.html [136] LM386: Low Voltage Power Amplifier, National Semiconductor Corporation, at http://www. national, com [137] "Spectre HDL reference manual," Cadence Design systems. 1995. [138] B. Kaminska, K. Arabi, I. Bell, P. Goeteti, J. L. Huertas, B. Kim, A.Rueda and M. Soma, "Analog and Mixed-signal Benchmark Circuits - First Release," Proceeding of International Test Conference, 1997, pp. 183-190 [139] P. Variyam and A. Chatterjee, "Enhancing Test Effectiveness for Analog Circuits Using Synthesized Measurements," Proceedings, VLSI. Test Symposium, 1998, pp. 132-137. [140] G. Devarayanadurg, P. Goeteti and M. Soma, "Hierarchy Based Fault Simulation of Mixed-signal ICs," Proceedings, International Test Conference, 1996, pp521527. [141] J. Hou and A. Chatterjee, "Concert: A Concurrent Fault Simulator for Analog Circuits," Proceedings, IEEE-ACM Conference on Computer-Aided-Design, 1998, pp. 384-391.

XX

[142] J. Hou, W. H. Kao and A. Chatterjee, "Novel Concurrent Fault Simulation Method for Mixed-signal Circuits," Proceedings, International Symposium on Circuits and Systems,. 1999.pp. II-448-II-451. [143] "LM146/LM246/LM346 Programmable Quad Operational Amplifiers," National Semiconductor Corporation, November 1994, also at http://www.national.com [144] V. K. Navin, T. Ray, M. M. Hassoun, W. C. Black, E. K. R Lee, E. G. Soenen, R. L. Geiger, "A Simulation Environment for Pipelined Analog-to-Digital Converters," IEEE International Symposium on Circuits and Systems, 1997, pp. 1620-1623. [145] E. Liu, G. Gielen, H. Chang, A. L. Sangiovanni-Vincentelli, P. R. Gray, "Behavioral Modeling and Simulation of Data Converters," IEEE International Symposium on Circuits and Systems, 1992, Volume. 5, pp. 2144-2147. [146] "ADC0831 8-bit Serial I/O CMOS A/D Converters with Multiplexer Option," at http://www.national.com, National Semiconductor Corporation, August 1999. [147] "LM7805C Series 3-Terminal Positive Voltage Regulators," at http://www/ national.com, National Semiconductor Corporation, July 1999. [148] "LM386 Low-Voltage Audio Power Amplifier," at http://www/national.com, National Semiconductor Corporation, August 2000. [149] R. Pease, "Troubleshooting Analog Circuits," Butterworth-Hienmann, 1990, pp. 90-96. [150] -"LabVIEW User Manual" National Instruments, January 1998.

xx i

[151] "PCI-61XE Families - E-Series Multifunction I/O - 5MS/s, 12-bit, Simultaneous Sampling, 2 or 4 analog Inputs," National Instruments Measurement and Automation Catalogue, pp. 236, also at http://www.mxom. [152] M. Abramovici, M. A. Breuer, A. D. Friedman, "Digital Systems Testing and Testable Design," IEEE press, 1990, Chapter 12, pp. 541-568.

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VITAE
Sasikumar Cherubal was born in November 19 , 1974 in Palakkad, India. He completed his Bachelor of Technology degree from Indian Institute of Technology, Chennai in 1996. He received his M.S. and Ph.D. degrees in Electrical and Computer Engineering from Georgia Institute of Technology, Atlanta, in 1998 and 2002, respectively. His research interests are in the test, diagnosis and modeling of analog and mixed-signal circuits.