PIPELINED LFSR COUNTERS

Jaromr Kolouch Brno University of Technology, Institute of Radio Electronics, Purkyova 118, 612 00 Brno phone: (05)41149144, fax: (05)41149244, e-mail: kolouch@ feec.vutbr.cz Abstract: Fast LFSR counter modifications with the cycle length different than the basic one suitable for implementation in FPGA devices are suggested. Example of VHDL code for 15-bit full cycle counter is given. LFSR counters are often used in FPGA based designs. Their simplicity allows them to count at maximum device speed for practically unlimited bit width of the counter. The cycle length for the basic LFSR modification with n bits is 2n 1, see e.g. [4]. Sometimes, other cycle length may be desired. The counter connection can be easily modified to achieve different cycle length, as described e.g. in [2], but at the price that, for large counters, wide products occur in the counter structure, which are usually implemented by LUT cascading. This means that the register-to-register delay is increased and the counter speed goes down with the counter bit width. Nevertheless, these wide products occur in expression for only one counter bit and the remaining counter structure simplicity is not changed. General connection of the LFSR counter in consideration is drawn in Fig. 1. This connection includes possibility of the basic n-bit counter modification with 2n 1 states as well as other modifications with different cycle length. The current counter cycle length is determined by the combinational logic function, CLF. In the basic modification, the CLF function is reduced to the XNOR function of some output signals with indices i1, i2, ..., im. The LFSR counter theory shows, see e.g. [1], [4], that for any given counter bit width n, the input signals in this function can be chosen so that the counter proper operation with corresponding cycle length (2n 1 states) is provided. For the most practically useful counters, the number of the CLF input signals is not greater than 4. This means, when the counter is implemented in a FPGA device, that the function can use one LUT. Exception represents the counter with 37 bits where 6 input signals are necessary. In modifications with different cycle length, products of some other counter output signals are added, see [2]. Then, LUT cascading is used for the CLF implementation and the counter speed is reduced.
q i1 q
i2

CLF

D
im

RG<

Q1 Q2

q 1 q
2

Clk

Qn

Fig. 1. General connection of LFSR counter suitable for FPGA designs If the counter speed is important, pipelining technique can be used to reduce the registerto-register delay in the counter with other than the basic cycle length. Similar technique called flip-flop retiming is described in [3]. This technique consists in moving registers across combinational logic. In case of LFSR counter, all counter output signals are created by the shift register. If such output signal is used as feedback signal, it is equivalent to use of the output signal with the index by one lower and with register added into its path. Moving the registers in the forward direction can then be used to split the combinational logic function block into smaller blocks, each of them implementable in one LUT, to reduce the delay.

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An example of a 15-bit LFSR counter is drawn in Fig. 2. Fig. 2a represents the basic LFSR counter modification with 215 1 states, Fig. 2b is modification with full cycle, i.e. with 215 states, with CLF block having 15 inputs. In the Fig. 3a, the CLF block is split into two parts. One of them, enclosed by the dash-dotted frame, has only four inputs and, therefore, is implementable in one LUT. Fig 3b shows result of the register moving forward across the AND gate, which represents combinational block with only 13 inputs. The part in the frame is now separated from other logic by registers. The same process can be applied to the AND gate and continued in so many steps till the combinational blocks do not have more than four inputs. Final result is drawn in Fig. 4.
q 15 q
14

=1

RG<

Q1 Q2

q 1 q
2

q 15 q
14

=1

=1

RG<

CLF
Clk
(a)

q 1 q
2 14

Q1 Q2

q 1 q
2

&

Qn

Clk
CLF
(b)

Qn

Fig. 2. Example of 15-bit LFSR counter basic modification (a) and full cycle counter (b)
q 15 q
14
1 q 2_14

=1

=1

RG<

Q1 Q2

q 1 q
2

q 15 q
14
1 q 2_14

=1

=1

RG<

&

Q1 Q2

q 1 q
2

&

q 2 q
3

Qn
& (a)

Clk
q

q 1 q
2 13

Qn
&
Clk

Clk

14

(b)

Fig. 3. Register moving separates four-input combinational part in full cycle counter
q 7 q 8 q &

9 q 10

Clk

q 15 q
14

=1

=1

RG<

q 1 2_14
q 5 q 6 q
7

Q1 Q2

q 1 q
2

&

&

Clk

q 3 q 4 q
5

&

Clk

q 1 q 2 q
3

&
Clk

Qn
Clk

8_11

6_12

4_13

Fig. 4. Final result pipelined LFSR counter The schematic can be used to write the HDL description of pipelined LFSR counter. For the 15-bit counter, the VHDL code corresponding to the Fig. 4 is as follows:
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY LFS15pi1 IS PORT (Clk : IN std_logic; QOut: OUT std_logic_vector(1 TO 15)); END LFS15pi1;

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ARCHITECTURE Behavioral OF LFS15pi1 IS SIGNAL q: std_logic_vector(1 TO 15); SIGNAL ShRgIn: std_logic; SIGNAL q2_14,q4_13,q6_12,q8_11: std_logic; BEGIN ShRgIn <= (q(14) XNOR q(15)) XOR (q(1) AND q2_14); ShReg: PROCESS (Clk) BEGIN IF Clk'event AND Clk = '1' THEN q(2 TO q'high) <= q(1 TO q'high-1); q(1) <= ShRgIn; END IF; END PROCESS; PROCESS (Clk) BEGIN IF (Clk'event AND Clk = '1') THEN q2_14 <= q(1) AND q(2) AND q(3) AND q4_13; q4_13 <= q(3) AND q(4) AND q(5) AND q6_12; q6_12 <= q(5) AND q(6) AND q(7) AND q8_11; q8_11 <= q(7) AND q(8) AND q(9) AND q(10); END IF; END PROCESS; QOut <= q; END Behavioral;

To compare the results of synthesis and timing parameters, the LFSR counter described above and similar designs with 33 and 60 bit width were synthesized using Xilinx ISE 6 system and implemented into XC2S15CS144-5 device. The number of slices from the synthesis report and minimum period from static timing analysis are given in the following table.

15-bit counter

33-bit counter

60-bit counter pip bSRL bFF full pip 18 3 35 39 34

bSRL bFF full pip bSRL bFF full No of Slices 1 9 9 11 2 19 21

Min. period 4.60 4.11 6.41 4.30 4.57 4.30 8.68 4.39 4.38 4.66 8.91 4.59 [ns] Abbreviations in the table: bSRL basic counter modification with SRL primitive implemented (only last counter bit available outside the primitive) bFF basic counter modification with all bits available full full cycle counter without pipelining pip full cycle counter with pipelining The 33-bit counter design used bits indexed 20 and 33 as the XNOR feedback, the 60-bit one used bits 59 and 60. The bSRL and bFF modifications were described by the same architecture, difference was only in port declaration: for bFF, all counter outputs were declared as ports, and for bSRL, only the last counter bit was declared as port, others only as internal signals. The default ISE setting was used in all cases. Based on the table, it is apparent that minimum period of the full cycle counter is significantly larger than that for the basic counter modification, and the pipelining reduced it back, near to the value for the basic modification.

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It is easy to write VHDL code for pipelined LFSR counter in similar way with any other bit width. For counters with lower number of states in their cycle, as described e.g. in [2], the same approach can be used to accelerate them. This technique can be used as well to speed up the LFSR counters that require more than 4 bits for feedback in the basic modification. Conclusion If a LFSR counter with full cycle or other cycle length than 2n 1 states is designed, the important advantage of the basic LFSR counter, i.e. high maximum frequency that is practically independent on the counter bit width can be preserved using the pipelining technique described in the paper. The HDL code for this counter modification is easy to write, and the FPGA resource requirements are not higher than those for the modification without pipelining. As drawback of this technique, occurrence of new states that are not included in the counter cycle can be considered. Acknowledgement This work has been supported by research programme Research of electronic communication and system technologies CEZ J22/98:262200011 and by research programme MSM 262200022 Mikrosyt. References [1] KOVALSK, J., VLEK, K., MITRYCH, J.: VHDL Models with Usage of the LFSR_PCKG Package. Radioengineering, Vol. 11, No. 1, April 2002, p. 18 [2] KOLOUCH, J.: LFSR Counters with Arbitrary Cycle Length. In: Radioelektronika 03, Conference Proceedings, Brno 2003, p. 110 [3] XST User Guide. Documentation to the Xilinx ISE-6 software, xst.pdf [4] WAKERLY, J. F.: Digital Design Principles and Practices. Prentice Hall, 2001

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