From Matlab/Simulink to ISE

Version number 1.0 Date 2008

Author: Sandro Noto Revised by: Helena Sarmento

Technical Report

Project: UWB Receiver: baseband processing using reconfigurable hardware (UWBR) PTDC/EEA-ELC/67993/2006

Funded by:

Abstract
System Generator can be useful when implementing the design flow as described by [1]. With Simulink, with its blocksets, and Matlab code we can explore an algorithm in a functional domain. Using System Generator blocks (Xilinx blockset) we can also design in the functional domain, but towards an FPGA implementation (physical domain). System Generator provides interfaces to CAD tools (ISE, ModelSim). System Generator automatically compiles designs into low-level representations. Experiments using hardware generation can suggest the hardware speeds that are possible and, through the resource estimation, give a rough idea of the cost of the design in hardware. If a promising approach is identified, system generator can create the bit stream (physical level) to the FPGA. System Generator allows refinements (lower levels) to be done in steps. Some portions of the design can be made ready for implementation in hardware, while others remain described by Simulink blocks, System generator blocks or were designed outside and are inside a wrapper to be wired in the System Generator tool. The mixed descriptions can be simulated in a multiple environment. Hardware descriptions can be emulated in the FPGA (Co-Simulation). This report describes the design of a small example. This example permitted to understand the interfaces between Simulink, ISE [2] and the FPGA, as well as the capabilities to design the complete Ultra Wide Band receiver. The example demonstrates the use of System Generator, using a ML402 evaluation platform with a Virtex-4 xc4vsx35-10ff668. The necessary steps to configure the board through an Ethernet interface are also part of this report.

Funded by:

Funded by:

Table of Contents
Introduction.............................................................................................................................7 ML402 Configuration .........................................................................................................8 Board setup .........................................................................................................................9 Network setup ...................................................................................................................10 CompactFlash setup ..........................................................................................................13 Verifying the board ...........................................................................................................13 Simulink, ISE and FPGA design ..........................................................................................14 Simulink with Xilinx Blockset..........................................................................................14 FPGA co-simulation .........................................................................................................15 Results and conclusions ........................................................................................................19 References.............................................................................................................................20

Funded by:

Funded by:

Introduction
System Generator is a system-level modeling tool that extends Simulink to provide FPGA hardware design. It offers high-level abstractions, the System Generator blocks (Xilinx blockset), that can be automatically compiled into an FPGA. System Generator can generate equivalent representations of the design, at the same or lower level. For example, from the functional domain it can generate a structural representation, an HDL or NGC netlist, or a physical representation such as an FPGA configuration bitstream. It can also to generate an equivalent high-level module that performs a specific function in applications external to System Generator (ModelSim hardware co-simulation) [3]. System Generator does not substitute hardware design, but permits to design less critical portions with System Generator blocks and then combined them with the other critical ones. Therefore: Parts of the design are implemented using System Generator blocks. System Generator employs libraries of intellectual property (IP) to automatically map abstractions onto device primitives. Other parts are designed directly in the FPGA using basic functions (adders, registers, memories) and a HDL language. The developed code (VHDL, Verilog) can be imported using wrappers to create Black Boxes. Black boxes are wired into the design, participate in simulations, and are compiled into hardware. The complete design is a combination of all the parts (System Generator blocks and imported blocks) into a working whole. System Generator offers mechanisms to: To import HDL code into a design. A configuration wizard can be used to associate the HDL module to a Black Box block. The wizard creates an M-function that defines the interface, the implementation and the simulation behavior of the black box block it is associated with. To automatically generate an HDL testbench, including test vectors. Upon requested, System Generator generates a testbench that produces files to allow comparisons of simulation results between Simulink and ModelSim (HDL simulator). The testbench is a wrapper that feeds the stimuli to the HDL for the design and compares HDL results against expected ones. To perform hardware co-simulations, hardware run under the control of Simulink, bringing the power of MATLAB and Simulink to bear for data analysis and visualization. For hardware Co-Simulation, a bitstream is created and associated to a block. When the design is simulated in Simulink, results for the compiled portion are calculated in hardware The example (named cosimul) used in this report was described with basic blocks of Simulink and with blocks from Xilinx blockset. The Xilinx Blockset contains some lowlevel blocks, providing access to device-specific hardware, and high level blocks, implementing signal processing and advanced communications algorithms. The description base on the Xilinx blockset was compiled to create the bitstream. Finally, a co-simulation was performed where the bitstream is downloaded to the FPGA board and the hardware outputs are analyzed by Simulink. Funded by:

ML402 Configuration
For the hardware co-simulation, the communication between the System Generator and the ML402 board was established through Ethernet. JTAG can also be used. Using Ethernet, the board connects to the PC either remotely across a network or directly using a standard Ethernet cable. System Generator automatically wraps the design with the logic necessary to communicate with the FPGA over an Ethernet connection during the simulation. A CompactFlash card installed on the ML402 board contains a special boot-loader image that allows the FPGA to receive, over the Ethernet cable, the bitstreams to be simulated on the FPGA. The ML402 configuration process is performed over the same Ethernet connection used for co-simulation. To use the ML402 board with System Generator for DSP we need a 15W (5V @ 3A) AC adapter, a Compact Flash (CF) card and CF reader. The PC requires two NICs (Network Interface Card) for Ethernet connection, one to access the Matlab license server and another to connect to the ML402 board. Windows XP Professional, MATLAB 7.6.0 (R2008a) and Xilinx System Generator 10.1 were used to install and configure the ML402 board. We connected the ML402 board and the NIC board in the PC through an RJ45 Ethernet cable and we followed the instructions in [3]. To set-up the board, the Network and the CompactFlash we followed [3].

Funded by:

Board setup

Power switch

LEDs Address and mode DIP switches

SYS ACE switch

Figure 1 ML402 evaluation platform (front) [5] For the board setup we performed the following steps: 1. Inserted the CompactFlash card with the power switch OFF (see Figure 3). 2. Plugged the power supply adapter cable into the ML402 board and to AC power. 3. Configured the address and mode DIP switch (Figure 1). Dip switches number 1, 4 and 6 up and dip switches 2, 3 and 5 down (Figure 2). 4. Configure the source selector switch to SYS ACE (Figure 1).

Figure 2 Address and mode DIP switches [3]

Funded by:

10 Power switch 5V power jack

Figure 3 ML402 evaluation platform wit CompactFlash inserted (back) [5]

Network setup

Figure 4 Network connections on Control Panel

Funded by:

11 To configure the Ethernet connection, we performed the following steps: 1. Found the reference of the NIC connected to the ML402 evaluation platform board. In this example is a SMC9452TX-2 Gigabit Ethernet PCI board. 2. Configured the board identified in the previous step on network connections of the control panel: Click Start Control Panel Network Connections, and next select Properties (Figure 4). 3. Selected TCP-IP (Figure 5) and then Properties. Set the IP. The IP must be in the same sub-network of the ML402 IP. Initial IP values were in the 192.168.8.0/24 range [3]. After the CompactFlash configuration we detected some problems (Figure 6) that were solved changing the IP range. The IP value of the ML board was changed from 192.168.8.1 to 1.2.3.1, editing the IP.dat file in the CompactFlash 4. Set the NIC board to 1.2.3.2 with a network mask to 255.255.255.0 (Figure 5). 5. Configured the communication, selecting the Configure button (Figure 7) and then the Advanced tab (Figure 8), to enable flow control and automatic negotiation in the communication speed and duplex mode.

Figure 5 TCP-IP properties

Figure 6 IP assignment problems Funded by:

12

Figure 7 Configuration

Figure 8 Communication speed and flow control

Funded by:

13

CompactFlash setup
To configure the memory card, we performed the following steps: 1. Used a CompactFlash reader to mount a CompactFlash as a disk drive. 2. Formatted the CompactFlash as FAT16, using the mkdofs command (mkdosfs v F 16) [4]. 3. Ran the unzip command in a Matlab window: unzip(fullfile(xlFindSysgenRoot,'plugins/bin/ML506_sysace_cf.zip'), '<CF Drive Letter>:\') to transfer to the CompactFlash the files: IP.dat (IP configuration), MAC.dat (MAC configuration), xilinx.sys and the folder ml402 (with boot files) (Figure 9).

Figure 9 CompactFlash configuration files [3] 4. Edited IP.dat to change the ML402 IP to 1.2.3.1. 5. Eject the CompactFlash from the PC

Verifying the board

After power on, we verified the network configuration looking at the green LEDs identified on Figure 1 (TX, RX, DUP, 1000, 100, 10) and the LCD. LCD displayed MAC and IP addresses. The LEDs indicating 1000 Mbps, Rx and TX were illuminated. To verify the network connection, a ICMP (Internet Control Message Protocol) ping command was issued in the PC (Figure 10) with a successful message.

Funded by:

14

Figure 10 ICMP ping command

Simulink, ISE and FPGA design

We analyzed the design environment, involving the Matlab/Simulink, ISE and the ML402 board. For that we design a very small example that uses a XOR function to invert the bits of a random bit stream.

Simulink with Xilinx Blockset

Figure 11 Simulink and Xilinx blocksets descriptions (example) On Figure 11 the XOR is described by the XOR logical operator of Simulink or by the XOR block of Xilinx blockset. The input bit stream, for simulation purposes, is generated by a Bernoulli binary generator (Communications blockset). The Scope block (Simulink basic block) permitted the analysis and comparison of simulations results. Both blocks are Simulink blocks. To use Xilinx blocksets, we need Gateway In and Gateway Out blocks that become the input and output ports when translated into hardware. Simulation results obtained by the Scope block are represented on Figure 12.

Funded by:

15

Figure 12 Simulation results with Simulink and Xilinx blockset

FPGA co-simulation
In this example, everything needed for a design is available inside System Generator. We do not use exterior blocks. Simulink basic blocks used only generate the bitstream and permit data visualization. Pressing the Generate button in System Generator generates files for the ISE package: HDL code describing the design itself; a clock wrapper that produces the clock and clock enable signals that the design needs; HDL code for the testbench that encloses the clock wrapper to allow results from Simulink simulations to be compared against ones produced by a logic simulator; project files and scripts to allow XST synthesis tools to operate on generated HDL; Files to allow the HDL code to be used as a project in Project Navigator. To generate the system block, representing our example, we performed the following steps: 1. Opened the System Generator block and choose for Compilation Hardware CoSimulation, ML402 board, Ethernet and Network based (Figure 13). We also tried the option Point-to-Point without success when running the simulation.

Funded by:

16 2. Choose the Generate button. A system block was created including the description of the bitstream inverter, corresponding to the description between Gateway In and Gateway Out (Figure 14). The locations of the GateWay In and Gateway Out ports and the speeds at which they must operate can be entered in the Gateway In and Out parameter dialog boxes [3]. 3. Copied the generated block (cosimul) (Figure 14) in the Simulink window to obtain a description for hardware co-simulation. The Bernoulli generator and the Scope block (Figure 15) were simulated in Simulink, the cosimul block will run in the FPGA (co-simulation). 4. Verified the IP address in the Network tab, clicking on the block (Figure 16). Set it to 1.2.3.1 (see CompactFlash setup). 5. Executed the hardware co-simulation. We connected the Ethernet cable between the board and the PC NIC card and the power cord to the AC power supply. We powered the ML402 board (power switch ON). In the Simulink window we initiated the simulation. Different messages indicating the generation of ACE files, the FPGA configuration and the network connection appeared before simulation is finished. Opening the scope blocks, simulation results appeared (Figure 17). Simulated the complete system in Simulink. To 6. We also tried the option Point-to-Point (step 1), but an error occurred when we executed the co-simulation.

Funded by:

17

Figure 13 System block generation

Figure 14 System block

Funded by:

18

Figure 15 Hardware co-simulation description

Figure 16 Set IP address

Funded by:

19

Figure 17 Hardware co-simulation results

Results and conclusions

We analyzed this example, using a PC with an Intel Pentium 3.2 GHz and 512 Mbytes of RAM. Simulation times are presented on Table 1. Even in a small example the bit stream takes time to be generated. Table 1 Simulation time
Simulation Simulink and System Generator blocks Hardware co-simulation: generation of black box Hardware co-simulation Time 3.19 s 13m 42.94 s 14.38 s

Funded by:

20

References
[1] [2] [3] [4] [5] Gajski, D.D. and Kuhn, R.H., New VLSI Tools, Computer Volume 16, Issue 12, pp: 11 14, December 1983 Release 10.1 March, 2008 Xilinx, ISE In-Depth Tutorial, 2007 Xilinx, System Generator for DSP User Guide, Release 10.1, March 2008 http://www.xilinx.com/products/boards/ml310/current/utilities/mkdosfs.zip Xilinx, ML401/ML402/ML403 Evaluation Platform User Guide, May 2006

Funded by: