University of California, San Diego Department of Electrical and Computer Engineering

ECE 108 2013, Homework Assignment 1

Reading: Digital Integrated Circuits by J. M. Rabaey et al. Chapter 4. Problem 1: Signal distribution and fanout An important question in designing digital circuits is: how many gates in parallel can a single output drive, in order to meet timing constraints? Here, we will examine a simple distribution network. A V_s=5 V source, with Thevenin resistance R_s=1 k, drives a certain number h (fanout) gates, each of which is modeled as a C_g=100 fF load. The gates are driven simultaneously (i.e., in parallel). You are given : V_OL = 1 V, V_OH = 4 V. Ignore the wire resistance. What is the allowed fanout (h, as a numerical value) such that signals upto 333 MHz can propagate satisfactorily? Problem 2: Elmore Delay Using the Elmore delay model, find the RC time constant for the high-to-low transition (i.e., to GND) in the circuit shown to the left. (It is part of a NAND gate, and h is called fanout, or electrical effort). Hint: The output of the gate is at the node marked Y. State your answer in terms of h, R and C. Problem 3: (ignore the crossed out parts, this is just revision control) In a particular CMOS generation node, you are given that a minimum sized inverter has R = 5 k and C = 0.2 fF and the size ration oN f tsegments he PMOS to NMOS transistors (i.e., width ratio) = 2. Using R calculate R/N R/N R/N of a R/N Elmores model, the RC time constant 5x inverter (i.e., 5 times the size of each of the PMOS and NMOS driving a 2x inverter the end of a 1 mm wire. Assume that the wire C transistors) C/N C/N C/N at C/N has capacitance of 0.2 fF/m m and resistance of 0.01 0.1 /square, and is 0.125 m m long wide.
R C R C/2 C/2 R/2 R/2 C

L-model T-model Represent the wire RC as -model instead of a single R and single C. Hint: Driving a CMOS invertor means the signal has to drive both the PMOS gate capacitance and the NMOS gate capacitance in parallel.

ECE108