A Novel Structure of Wide-Swing CMOS

Voltage Buffer
Chutham Sawigun and Jirayuth Mahattanakul
Department of Electronic Engineering, Faculty of Engineering
Mahanakorn University of Technology, Bangkok, THAILAND
Email: chotharn@mut.ac.th, jirayut@mut.ac.th
Abstract This paper presents a novel structure of wide-
swing CMOS voltage buffer, which is based on the flipped
voltage follower. When compared with the previously
established buffer based on the same principle, the proposed
circuit is less complex and consumes less power while attaining
wide bandwidth and high slew-rate. Simulated results of the
proposed buffer using a 0.35m CMOS process are provided.
I. INTRODUCTION
Analog voltage buffers or voltage followers can be
found in various analog applications such as current
conveyors [1], current feedback amplifiers [2], output stages
of power amplifiers and line drivers [3], and analog filter
realizations [4]. In order to drive large capacitive loads with
high speed and attain high signal-to-noise ratios, analog
buffers must provide an output current and voltage swing
range which is as high as possible. To meet these
requirements, a fast, unity-gain class-AB amplifier circuit
with rail-to-rail signal capability is required. Combining the
class-AB operation and rail-to-rail signal swing usually
requires a complicated biasing circuit to extend the
common-mode input range of the buffer [5]. Unfortunately,
this increases the buffer complexity and power
consumption.
In this paper, we describe a compact, class-AB CMOS
analog buffer with rail-to-rail signal capability, which
dispenses with the requirement for a complicated biasing
circuit. The circuit employs the complementary class-AB
differential transconductor proposed in [6] and its common-
mode input range limitation is solved by inserting level
shifters into the local feedback path of the transconductor.
Although, this technique is similar to the voltage buffer
proposed in [7], our approach avoids the complicated
biasing circuit required in [7] to stabilize the circuit DC
operating points when the input signal goes either
excessively high or low. As a result, the overall buffer
complexity and quiescent power consumption are reduced,
while still attaining rail-to-rail signal swing and high driving
ability.
Figure1. (a) Flipped voltage follower. (b) Buffer without level shifting.
The remaining sections of the paper are organized as
follows. Section II provides an overview of previous works
in analog rail-to-rail buffer design and Section III presents
the proposed circuit. Simulated results using parameters for
a 0.35Pm CMOS process are presented in Section IV and
conclusions suitably drawn in Section V.
II. PREVIOUS BUFFERS
A. Flipped Voltage Follower
Fig. 1a shows the high accuracy buffer which is called
flipped voltage follower by the fact that a bias current I
B
is
injected to drain instead of source terminals of MA.
Compared with the traditional source follower circuit,
following behavior of the circuit in Fig.1a is far better
because the drain current of MA is regulated by constant
current source resulting in constant gate-source voltage as
well. Moreover a very large loop gain provided by common
source circuit MB, which is embedded in a local negative
feedback loop of the circuit, forcing a small signal output
resistance of this circuit to be very low [9] and the feedback
mechanism can be simplify by a feedback block diagram
shown in Fig 2, where g
mi
is a small signal transconductance
gain of each transistor and r
ds
is a drain-source resistance and
r
B
is an output resistance of the
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Figure 2. Feedback block diagram of the flipped voltage follower.
Figure 3. Class-AB buffer in [6].
current source I
B
. To compensate for a DC level shifting
between input and output voltages of the circuit in Fig.1a, the
circuit in Fig.1b is employed. This circuit operates as a single
stage amplifier connected in unity gain feedback scheme
which also maintains equality between input and output
voltages by a large loop gain of a global feedback path.
When large signal characteristics are considered, it can be
seen that both circuits in Figs. 1a and 1b can maximally push
current to load by I
B
, whereas pull currents can be much
higher.
To fulfill the asymmetrical output currents of both
circuits, a buffer circuit providing fully class-AB
characteristic is proposed in [6] and shown in Fig.3. It is
simply realized by stacking the circuit in Fig. 1b in a
complementary fashion. The circuit is compact and has very
low quiescent power consumption given by
3
B DD SS
P I V V . (1)
Moreover, it provides a class-AB output current suitable
for large capacitive loads but its signal swing is limited by
the circuit topology itself. An attempt to extend signal swing
of the buffer has been done in [7]. Although, however, the
signal swing is successfully enhanced, the overall circuit is
bulky and required almost quadrupling of power
consumption of the buffer in Fig.3.
,
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M1 M2
M5
M4
9
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M3
9
66
,
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M6 M7
,
%
M8 M9
M12
M11
9
66
M10
9
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,
%
M13 M14
9
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1
2
Figure 4. Proposed rail-to-rail buffer.
III. PROPOSED CIRCUIT
Fig. 4 shows the proposed rail-to-rail CMOS analog
buffer. The circuit can be divided into two parts; the upper
circuit consisting of devices M1-M7 and the lower circuit of
devices M8-M14. Each of these sub-circuits resembles a
single-stage class-AB amplifier. The purpose of level
shifters, M4-M5 and M11-M12 are to provide negative
feedback loops (1 and 2), thereby extending the input
common-mode range [7].
By virtue of the negative feedback around loops 1 and
2, the impedances at the source terminals of M2 and M9 are
forced to be very low. As a result, the gate-source voltages
of M2 (V
GS2
) and M9 (V
SG9
) are kept nearly constant,
causing the current at the circuit output node to feature
class-AB behavior [9]. Considering the circuit in Fig. 3
without M3 and M10 we can see that it may properly
operate as a unity-gain amplifier or voltage buffer.
However, when the input voltage (V
in
) goes low or high and
exceeds the following range:
5 2 12 9
d d
SS eff eff Tn in DD eff eff Tp
V V V V V V V V V (2)
where V
eff
is the effective or saturation voltage, V
Tn
and V
Tp
are the threshold voltages of n and p channel devices
respectively, either the upper or the lower sub-circuit will be
forced out of the active region. As a result, there will be no
DC current to support the output branch of the rest of the
circuit, leading to inevitable shut down of the entire buffer
circuit.
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Here, the main objective of inserting M3 and M10 into
the circuit in Fig. 4 is to widen its input range, i.e., to be
higher than (2). Since the gate-source voltages of M3 and
M10 are respectively copied from M2 and M9, their current
conducting behavior will be similar and controlled by V
in
.
Devices M3 and M10 function as controlled constant
current sources and stabilize the DC current of the output
branch devices M7 and M14. The DC stabilizing
mechanism will be considered next.
First consider the case when V
in
= 0. By virtue of the
negative feedback from the output node (V
out
) to the
inverting input terminals (gate terminals of M2, M3, M9
and M10), the input and output voltages are forced to be
identical, i.e., V
in
= V
out
= 0. At this point, both the upper
(M1-M5) and lower (M8-M12) input pairs are biased in the
active region, and the drain currents of M1 and M8 (both
equal to I
B
) are copied to the output branches via the current
mirrors M6-M7 and M13-M14. Also, M3 and M10 are
active with drain currents of I
D3
= I
D10
= I
B
. In this situation,
we can see that no DC operating problem occurs because
the drain current of M7 (I
D7
) is fully absorbed by a drain
current of M14 (I
D14
) and the total current consumption is
8I
B
then static power consumption of this circuit can be
calculated as
8
B DD SS
P I V V , (3)
showing that this circuit consumes less power than the
buffer in [7]. Interestingly, M3 and M10 may appear to be
redundant. Although true when V
in
= 0, for V
in
= 0, M3 and
M10 play a significant role as discussed next.
When a positive V
in
is applied and reaches the upper
limit of (2), M12 will be forced to enter the triode region. If
V
in
goes higher than this limit, I
D12
will be reduced and M8-
M10 will be pushed out of the active region, eventually
resulting in zero drain current in M8-M10 and M13-M14.
However, the upper sub-circuit will still continue to work
properly because I
D7
can be fully absorbed by I
D3
(even if
M14 is already turned-off). In the reverse situation, i.e.,
when V
in
goes more negative than the lower limit of (2), the
lower sub-circuit will be fully functional, whereas the upper
sub-circuit will be turned off. Thus, we can find that the
input range of the buffer is extended from (2) to be

11 12 in 4 5
3
DD eff eff Tp SS eff eff Tn
V V V V V V V V V d d . (2)
(4)
Hence, by appropriate choice of the voltage supply rails and
effective voltages in (4), we can achieve rail-to-rail
capability. To show the compactness of the proposed circuit
a component of the proposed buffer, excluding bias circuits,
is summarized in Table 1.
Table1: List of Components and Current Consumption of
the proposed circuit.
Parameter Fig.3
Transistor count 14
Current sources 4
Current consumption 8IB
Table2: Transistor Dimensions.
(channel length L = 1Pm for all transistors)
Transistor W [Pm]
M1-M3 20
M4 0.6
M5 10
M6-M10 60
M11 1.8
M12 30
M13-M14 20
Table3: Performance Summary.
Circuit performance Value
Bandwidth 6.8MHz
Slew rate:
positive, negative
61.3V/Ps,
68.2V/Ps
THD@1.4Vp, 100KHz -42dB
Static power consumption 282 PW
IV. SIMULTION RESULTS
The circuit in Fig.4 was simulated using SPICE with
parameters for a 0.35 Pm CMOS process (V
Tn
# 0.55V and
V
Tp
# 0.71V). The transistor dimensions are listed in Table
2. Capacitive load of 10pF were used, and the supply
voltage (V
DD
= V
SS
) and bias current I
B
were set to 1.5V
and 10PA, respectively.
The DC characteristic of the buffer circuits is shown in
Fig.5. The tracking behavior, between the input and output
voltages is shown in Fig.5a, and the offset error is shown in
Fig.5b. It can thus be seen that the output voltages of the
proposed buffer follow the input voltage for almost the
entire range of the voltage supply and the offset of the
proposed buffer is very low.
The operating speed of the proposed buffer was
evaluated by applying a 1.4V, 2 MHz square signal at the
input. The transient response is depicted in Fig. 6 showing
that the step response of the proposed buffer is faster than
60V/s.
The circuit linearity was evaluated by simulated total
harmonic distortion (THD) with a 100 kHz sinusoidal input
voltage with varying amplitude. The result is shown in Fig.
7 where it can be seen that less than -40
dB
THD of the
proposed buffer is achieved for amplitudes in excess of
1.4V. Finally, for a 10pF load, the buffer exhibited a
bandwidth of 6.8 MHz and details of other simulated
parameters are summarized in Table 3.
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Figure 5. DC characteristic of the proposed buffer
(a) input-output tracking behavior (b) voltage error.
Figure 6. Transient response of the proposed buffer.
-100
-90
-80
-70
-60
-50
-40
-30
0.2 0.4 0.6 0.8 1 1.2 1.4
Amplitude oI9LQ
THD|dB|
Figure 7. Simulated total harmonic distortion.
V. CONCLUSION
A novel compact structure of the high-performance
class-AB CMOS analog voltage buffer has been presented.
The proposed buffer combines high driving capability and
rail-to-rail signal swing. The circuit complexity and
quiescent power consumption of the proposed circuit are
lower compared with a previously reported buffer based on
the same principle. Simulated results have been provided to
show the performance of the circuit.
ACKNOWLEDGMENT
The authors would like to thank A. Demosthenous, for
invaluable suggestions and discussions. His kind help
creating this paper is highly appreciated.
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