IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 57, NO.

11, NOVEMBER 2010

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A Family of Low-Voltage Bulk-Driven CMOS Continuous-Time CMFB Circuits

Juan M. Carrillo, Guido Torelli, Senior Member, IEEE, Miguel A. Domnguez, Raquel Prez-Aloe, Jos M. Valverde, and J. Francisco Duque-Carrillo

AbstractThis brief introduces four different structures for implementing a continuous-time common-mode feedback (CMFB) network for fully differential (FD) ampliers. The proposed circuits use bulk-driven MOS transistors, thus representing a lowvoltage realization of their gate-driven counterparts. The CMFB circuits were included in a 1.5-V FD buffer implemented in standard 0.35-m CMOS technology. Experimental results illustrate the performance of the proposed schemes, demonstrating their suitability to operate with a low supply voltage. Index TermsBulk-driven MOS transistors, CMOS analog integrated circuits, common-mode feedback (CMFB), fully differential ampliers, low-voltage.

Fig. 1. FD amplier with feedback control of the output CM voltage.

I. I NTRODUCTION HE OVERALL performance of analog and mixed-mode systems may be improved by adopting a fully differential (FD) implementation. The use of this approach entails several well-known advantages, such as the extension of the dynamic range, the ideal cancellation of even-order harmonics, and the reduction of the effects of undesired noises coming from the supplies, which may be considered as common-mode (CM) signals [1]. Nevertheless, there are also disadvantages associated to the use of FD circuits. The duplication of most parts of the circuit leads to area and power consumption increase. Moreover, an additional network, referred to as CM feedback (CMFB) circuit, must be used to control the CM component of the output signal [1][4]. Some approaches have been reported in order to avoid the need for a CMFB loop in FD circuits [5][7]. However, all the proposed techniques have their own benets and drawbacks. The conventional block diagram of a FD amplier including a CMFB loop is shown in Fig. 1. The amplier output voltages, + and Vout , are fed to a CM detector. This block provides a Vout signal, Vs , which monotonously tracks the amplier output CM + + Vout )/2. This signal is compared to voltage Vout,CM = (Vout a reference voltage, Vref , by means of an error amplier whose

output signal, Vcmfb , is injected back into the FD amplier so as to close a negative feedback loop. The CM loop must be able to operate with high accuracy at least up to the highest frequency at which output balancing is desired [1], [2]. Therefore, the CMFB circuit must be designed in such a way that CM and differential-mode (DM) loops provide similar accuracy and speed response, which entails LGCM = LGDM LGBWCM = LGBWDM (1a) (1b)

Manuscript received March 30, 2010; revised June 15, 2010; accepted July 28, 2010. Date of current version November 17, 2010. This work was supported by the Junta de Extremadura R&D Plan under Grants 3PR05C008 and PRI09A080. This paper was recommended by Associate Editor N. Neihart. J. M. Carrillo, M. A. Domnguez, R. Prez-Aloe, J. M. Valverde, and J. F. Duque-Carrillo are with the Department of Electronics, University of Extremadura, 06006 Badajoz, Spain (e-mail: jmcarcal@unex.es). G. Torelli is with the Department of Electronics, University of Pavia, 27100 Pavia, Italy (e-mail: guido.torelli@unipv.it). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TCSII.2010.2068090

that is, the CM open-loop DC gain, LGCM , and gain-bandwidth product, LGBWCM , must be comparable to the corresponding parameters for the DM signal, i.e., LGDM and LGBWDM , respectively [1]. These requirements may be met by providing similar paths to the DM and CM components of the signal. There is an additional drawback when the FD amplier is required to operate in low-voltage conditions. In a system involving different basic building blocks, the output DC voltage of each block should be set to a level compatible with the input voltage range of the cascaded stage. Nevertheless, the most convenient level for the output CM voltage of the overall system is usually midsupply, as in this case the output signal swing is maximized. If the supply voltage is lower than 2|VGS | (VGS being the gate-to-source voltage of an MOS transistor in its active region), the DC level at midsupply is not sufcient to turn either a p- or an n-channel transistor on. In this case, a conventional CM detector based on gate-driven MOS devices cannot be directly driven by the amplier output terminals and passive voltage shifters or non-standard CMOS fabrication technologies should be used [8]. Besides, even when the supply voltage is above 2|VGS |, a conventional CM detector network could have difculties to operate in worst-case conditions and/or could show a very limited signal swing. A possible solution to implement low-voltage continuoustime basic building blocks in standard CMOS technology is

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Fig. 2. Conceptual implementation of a CM detector scheme based on two passive resistors and two voltage buffers.

to use bulk-driven MOS transistors [9][12]. In this brief, this approach is followed to design four different continuoustime CM detectors able to operate over a wide voltage range under low-voltage conditions. In Section II, conventional (gatedriven) continuous-time CMFB circuits and their limits are briey reviewed, and bulk-driven counterparts are proposed. These blocks were included in a low-voltage FD buffer as illustrated in Section III. An experimental comparison of the proposed CM detectors is provided in Section IV and, nally, conclusions are drawn in Section V. II. B ULK -D RIVEN CMFB S IN S TANDARD CMOS T ECHNOLOGY A key building block in the implementation of an FD amplier is the CM detector. This circuit must generate a voltage, Vs , that monotonously tracks the output CM voltage, Vout,CM , of the FD amplier. If the value of Vs is linearly related to Vout,CM , the linearity of the amplier is further enhanced. To this end, different approaches have been reported in literature [1][4], [8], [13][15]. The simplest network for CM detection is illustrated in the shadowed area of Fig. 2, assuming + and Vout to be directly connected to Va and Vb , voltages Vout respectively. The operation principle of this circuit is based on generating voltage Vs with the help of two identical seriesconnected passive resistors, R. Ideally, the value of Vs is equal to the CM voltage of the applied signals, Vout,CM . Nevertheless, an important limitation of this scheme is the loading effect of resistors on the FD amplier. A conventional solution to overcome this drawback is to use voltage buffers as illustrated in the overall circuit of Fig. 2. The unity gain ampliers may be easily implemented by means of source followers (SFs) [1]. However, the drawback of using voltage buffers is the distortion introduced by active devices. The linearity of the overall FD amplier may be enhanced if the voltage buffers are implemented by using ipped voltage followers (FVFs) [13]. Another possibility to build a CM detector is to take advantage of the operation of a differential pair (DP) [1]. Indeed, when a differential pair works in its linear region, the voltage at the common source terminal of the input transistors follows the CM component of the voltage signals applied to their input terminals with (ideally) unity gain. The main drawback of this approach is the reduced input DM range of a CMOS differential pair, which leads to substantial distortion amounts even when the applied differential signal is very small. Linearity may be improved by connecting two pairs of the same polarity in parallel to implement a current-based (CB) solution [1], [14]. In this case, one of the input terminals of both differential pairs is connected to reference voltage Vref and the outputs of the FD amplier are connected to the other two input terminals of the pairs. A signal current is generated and gives rise to

Fig. 3. Low-voltage bulk-driven CM detectors relying on (a) a differential pair (DP), (b) a source follower (SF), (c) a ipped voltage follower (FVF), and (d) current-based operation (CB).

control voltage Vcmfb in the FD amplier. Improved linearity is achieved thanks to the differential structure and operation of the CM detector. The circuit techniques described above were previously implemented by using standard gate-driven transistors which imposes a minimum supply voltage of 2(VGS + VDSat + Vsignal ), where VDSat is the drain-to-source saturation voltage of an MOS transistor and Vsignal is the peak amplitude of the processed signal. The factor of two in the above expression holds assuming that the output CM voltage is set to midsupply. The supply requirements of a continuous-time CM detector may be reduced if a bulk-driven approach [9][12] is followed, as in this case the minimum required supply voltage is only VGS + VDSat . Indeed, it is not necessary to spend a part of the voltage applied to the input terminals to turn the input devices on. The bulk-driven implementation of four different CM detector circuits derived from the gate-driven schemes depicted above, namely, solutions relying on a differential pair (DP), a source follower (SF), a ipped voltage follower (FVF), and CB operation, is illustrated in Fig. 3. The operation principle of circuits DP [Fig. 3(a)], SF [Fig. 3(b)], and FVF [Fig. 3(c)] is similar to that of the corresponding gate-driven counterpart, which has been explained above. In these cases, the block diagram shown in Fig. 1 for the FD amplier is used and voltage Vref can be generated with the help of a replica of the main CM detector: this way, the two blocks are affected by the same variations during fabrication and hence, errors in

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Fig. 5. Low-voltage error amplier (Vb represents a suitable bias voltage).

Fig. 4. FDDA: (a) circuit schematic; (b) unity-gain non-inverting FD buffer conguration.

setting Vout,CM to the required value are reduced. Regarding the approach in Fig. 3(d), a current Icmfb is generated by the CM detector and is then fed to the FD amplier by means of voltage Vcmfb , thus closing the feedback loop with no need for any error amplier. The input-referred noise contribution of a bulk-driven MOS transistor is higher as compared to that of a gate-driven device [9], [11]. Nevertheless, as the CMFB circuit directly acts over the output branches of the FD amplier, the noise contribution of the bulk-driven transistors in the CMFB is divided by the overall gain of the amplier when its input-referred noise is calculated. Thus, the noise contribution of the bulk-driven transistors in the above CMFB networks is negligible as compared to the noise contribution of the input transistors of the FD amplier. Finally, it is worth to note that the maximum input current of bulk-driven MOS transistors when their parasitic pn source-bulk junction is forward biased can be kept to a very low level [16], as will be shown in Section IV. III. L OW-VOLTAGE FD B UFFER With the goal of comparing the performance of the four CM detector networks introduced above, the FD difference amplier (FDDA) illustrated in Fig. 4(a) was designed [17]. The amplier was connected according to the conguration shown in Fig. 4(b), thus obtaining a FD voltage buffer. The input stage of the FDDA is based on bulk-driven input transistors and drives an output stage biased in class A. The goal of using a bulk-driven input stage in the FDDA is to achieve input rail-to-rail operation, so as to verify the operating voltage range of the proposed bulk-driven CM detectors. The frequency response of the two-stage scheme is compensated by means of a conventional Miller network including a zero-nulling resistor. The FD amplier outputs are capacitively loaded by the bulkdriven MOS transistors of the CM detector. However, this capacitance is connected in parallel with the load capacitor, CL , and, typically, its effect is almost negligible. The error amplier

Fig. 6. Chip microphotograph of the four FD buffers fabricated.

in Fig. 5 was included in the CMFB loop based on the DP, the SF, and the FVF solutions in order to set the output CM voltage to the desired value, Vref . In order to accomplish (1), the paths for the DM and the CM signals should be as similar as possible. For the circuits proposed, the DM signal path coincides exactly with the path provided by the FDDA in Fig. 4(a). On the other hand, the CM loop includes the CM detector (which is based on bulk-driven devices) and the error amplier (if any) along with the input stage of the FDDA (driven by transistors MA7 and MA8) as an input section and the class-A stage of the FDDA as an output section. Therefore, it is not difcult to achieve the conditions in (1) as in each case, both the DM and the CM path include a bulk-driven stage cascaded by a gate-driven stage (the latter being the same for the two paths). When a gate-driven approach is followed for the input stage of the FD amplier, the gain and the frequency response of the bulk-driven CM detector may be enhanced by using appropriate circuit techniques [11] to satisfy requirements in (1). Finally, it is worth to point out that the lowgain conguration chosen for the error amplier in Fig. 5 makes it easier to compensate the frequency response of the CM loop, where the two high-gain stages indicated above are present. IV. E XPERIMENTAL R ESULTS Four FD buffers, including the FDDA in Fig. 4(a), the CM detector networks in Fig. 3 (DP, SF, FVF, and CB approach, respectively), and the error amplier in Fig. 5 when required, were designed in standard 0.35-m CMOS technology (nominal threshold voltage values equal to 0.5 V and 0.65 V for n-channel and p-channel devices, respectively) to operate with

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Fig. 8. Measured THD as a function of the input signal amplitude Vin,pp for an input frequency of (a) 1 kHz and (b) 10 kHz.

Fig. 7. Measured DC transfer characteristic of the four FD buffers: (a) single+ + ended (Vout , Vout ) and (b) fully differential (Vout,DM = Vout Vout ) outputs.

a 1.5-V supply voltage (VDD = VSS = 0.75 V). A microphotograph of the chip is depicted in Fig. 6. The biasing currents of the input and the output stage of the FDDA, IB and IBO , were set to 10 A and 20 A, respectively, while the value of biasing currents in the CM detectors and their respective replica circuits, IB,CMFB , (when needed) was chosen equal to 10 A. The quiescent values of currents IB,E1 and IB,E2 in the error amplier were set to 15 A and 2.5 A, respectively. There is no risk that current sources IB and IB,CMFB operate in the triode region. Indeed, the connection of the gate terminal of the bulk-driven MOS transistors to VSS provides these current sources with a large value of the drain-to-source voltage, VDS . This degree of freedom for VDS allows including cascode transistors in the current sources when a demanding CM rejection ratio (CMRR) performance is required. The value of resistors R, which were implemented with nonsilicided polysilicon, was selected to be equal to 10 k. The channel length of MOS transistors was set to 1 m in order to minimize the effect of mismatches, except for the devices involved in the biasing

circuitry, for which a length equal to 2 m was used for the sake of accuracy. The simulated values of LGDM and LGBWDM , which correspond to the DC gain and the gain-bandwidth product of the FDDA in Fig. 4(a), were 71 dB and 1.2 MHz, respectively. The simulated LGCM and LGBWCM were equal to 78 dB and 1.0 MHz for the FD buffer with the DP, the SF, and the FVF CM detector whereas, for the FD buffer based on the CB approach, the simulated LGCM and LGBWCM were equal to 80 dB and 1.3 MHz, respectively. The improvement in the frequency response is due to the fact that, in the last solution, no error amplier is involved in the CM path. The experimental DC transfer characteristics of the FD buffers with the four different CM detectors are illustrated in + and Vout ) of each CMFB Fig. 7. The individual responses (Vout circuit, depicted in Fig. 7(a) as a function of the input voltage + and Vin ), are linearized when one of the two comple(Vin mentary output voltage signals is subtracted from the other to obtain the differential output Vout,DM , which is illustrated in Fig. 7(b). The linearization is due to the cancellation of even-order harmonics. According to Fig. 7, the CB approach provides the output response that is closest to the input signal for a wider voltage range. It is worth noting that the worst-case

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TABLE I E XPERIMENTAL P ERFORMANCE C OMPARISON OF F OUR FD B UFFERS C ONTAINING THE CM D ETECTORS IN FIG. 3 (T ECHNOLOGY: 0.35-m CMOS, VDD = VSS = 0.75 V, Vref = 0 V, CL = 10 pF)

midsupply even for supply voltages as low as VGS + VDSat , which represents an important reduction in terms of minimum supply voltage as compared to the case of a conventional continuous-time CMFB circuit based on gate-driven devices. The operation of the proposed solution was validated by means of measurements on four FD buffers using different bulkdriven CM detectors, which demonstrated their good linearity performance and suitability to low-voltage operation. ACKNOWLEDGMENT The authors wish to thank the support of I. Brinquete in fabricating the printed circuit boards used for test purposes. R EFERENCES
[1] J. F. Duque-Carrillo, Control of the common-mode component in CMOS continuous-time fully differential signal processing, Analog Integr. Circuits Signal Process., vol. 4, no. 2, pp. 131140, Sep. 1993. [2] M. Banu, J. M. Khoury, and Y. Tsividis, Fully differential operational ampliers with accurate output balancing, IEEE J. Solid-State Circuits, vol. 23, no. 6, pp. 14101414, Dec. 1988. [3] P. Pandey, J. Silva-Martinez, and X. Liu, A CMOS 140-mW fourthorder continuous-time low-pass lter stabilized with a class AB commonmode feedback operating at 500 MHz, IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 4, pp. 811820, Apr. 2006. [4] M.-C. Huang and S.-I. Liu, A fully differential comparator-based switched-capacitor modulator, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 5, pp. 369373, May 2009. [5] P.-H. Lu, C.-Y. Wu, and M.-K. Tsai, The design of fully differential CMOS operational ampliers without extra common-mode feedback circuits, Analog Integr. Circuits Signal Process., vol. 4, no. 2, pp. 173186, Sep. 1993. [6] A. Wyszynski and R. Schaumann, Avoiding common-mode feedback in continuous-time gm -C lters by use of lossy integrators, in Proc. IEEE ISCAS, London, U.K., May 1994, vol. 5, pp. 281284. [7] P. D. Walker and M. M. Green, An approach to fully differential circuit design without common-mode feedback, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 43, no. 11, pp. 752762, Nov. 1996. [8] T. Pasch, U. Kleine, and R. Klinke, A common mode feedback structure for differential opamps using NMOS depletion transistors, Analog Integr. Circuits Signal Process., vol. 27, no. 3, pp. 191196, May 2001. [9] B. J. Blalock, P. E. Allen, and G. A. Rincon-Mora, Designing 1-V opamps using standard digital CMOS technology, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 7, pp. 769780, Jul. 1998. [10] S. Chatterjee, Y. T. Tsividis, and P. Kinget, 0.5-V analog circuit techniques and their application in OTA and lter design, IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 23732387, Dec. 2005. [11] J. M. Carrillo, G. Torelli, R. Prez-Aloe, and J. F. Duque-Carrillo, 1-V rail-to-rail CMOS opamp with improved bulk-driven input stage, IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 508517, Mar. 2007. [12] Y.-L. Lo, W.-B. Yang, T.-S. Chao, and K.-H. Cheng, Designing an ultralow-voltage phase-locked loop using a bulk-driven technique, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 5, pp. 339343, May 2009. [13] J. M. Carrillo, J. L. Ausn, and J. F. Duque-Carrillo, CMOS continuoustime CMFB circuit with improved linearity, in Proc. Eur. Conf. Circuit Theory Des., Sevilla, Spain, Aug. 2007, pp. 4043. [14] T.-Y. Lo and C.-C. Hung, Multimode Gm -C channel selection lter for mobile applications in 1-V supply voltage, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 4, pp. 314318, Apr. 2008. [15] M.-H. Shen, P.-H. Lan, and P.-C. Huang, A 1-V CMOS pseudodifferential amplier with multiple common-mode stabilization and frequency compensation loops, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 5, pp. 409413, May 2008. [16] J. M. Carrillo, G. Torelli, M. A. Domnguez, and J. F. Duque-Carrillo, On the input common-mode voltage range of CMOS bulk-driven input stages, Int. J. Circuit Theory Appl., published online, Jun. 2010. [17] H. Alzaher and M. Ismail, A CMOS fully balanced differential difference amplier and its applications, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 6, pp. 614620, Jun. 2001.

DC input current arises for Vin,cm = VSS , where the measured value of Ii for the four implementations ranges between 2 nA and 4 nA. This leads to a worst-case effective input resistance, Ri , between 7.4 M and 17.0 M. In order to determine the linearity of the four schemes implemented, the total harmonic distortion (THD) of the output signal of the FD buffers was measured. Fig. 8 illustrates the experimental THD as a function of the input signal peak-topeak amplitude for two different input frequencies, that is, 1 kHz [Fig. 8(a)] and 10 kHz [Fig. 8(b)]. Approaches CB and FVF provide the best performance. Fig. 8 also shows the distortion level introduced by the circuit used to convert a single-ended input voltage into the FD signal that is fed to the FD buffer. A summary of the experimental performance of the four FD buffers is provided in Table I, where statistical data refer to measurements on 20 different samples of each circuit. The DC gain, Av , was measured for the FDDA in open-loop conguration, while the unity gain bandwidth, U GB , stands for the 3-dB bandwidth of the FDDA in the buffer conguration illustrated in Fig. 4(b). The CM offset voltage, Vos,CM , shows the accuracy of the CMFB circuit in setting Vout,CM to the desired reference value, whereas the DM offset voltage, Vos,DM , is a consequence of mismatches between the two sides of the FD circuit. It may be deduced from Figs. 7 and 8, as well as from Table I, that the CMFB approach CB represents the most linear solution, while also leading to the lowest power and area consumption, mainly due to the fact that no additional error amplier is required in this case. V. C ONCLUSION The use of bulk-driven MOS transistors is a suitable approach to implement low-voltage continuous-time CMFB networks. Bulk-driven standard MOS devices allow setting the CM component of the output voltage of a FD amplier to