TABLE 5-1: Special Function Register Map For Pic18F2Xk20/4Xk20 Devices

PIC18F2XK20/4XK20
TABLE 5-1:
Address FFFh FFEh FFDh FFCh FFBh FFAh FF9h FF8h FF7h FF6h FF5h FF4h FF3h FF2h FF1h FF0h FEFh FEDh FECh FEBh FEAh FE9h FE8h FE7h FE5h FE4h FE3h FE2h FE1h FE0h FDFh FDDh FDCh FDBh FDAh FD9h FD8h Note 1: 2: 3: 4:
SPECIAL FUNCTION REGISTER MAP FOR PIC18F2XK20/4XK20 DEVICES

Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0(1)
(1)
Address FD7h FD6h FD5h FD4h FD3h FD2h FD1h FD0h FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC7h FC6h FC5h FC4h FC3h FC2h FC1h FC0h FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB7h FB6h FB5h FB4h FB3h FB2h FB1h FB0h
Name TMR0H TMR0L T0CON (2) OSCCON HLVDCON WDTCON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 CCPR1H CCPR1L CCP1CON CCPR2H CCPR2L CCP2CON PSTRCON BAUDCON PWM1CON ECCP1AS CVRCON CVRCON2 TMR3H TMR3L T3CON SPBRGH
Address FAFh FAEh FADh FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FA0h F9Fh F9Eh F9Dh F9Ch F9Bh F9Ah F99h F98h F97h F96h F95h F94h F93h F92h F91h F90h F8Fh F8Eh F8Dh F8Ch F8Bh F8Ah F89h F88h
Name SPBRG RCREG TXREG TXSTA RCSTA EEADRH(4) EEADR EEDATA EECON2(1) EECON1 (2)
(2)
Address F87h F86h F85h F84h F83h F82h F81h F80h F7Fh F7Eh F7Dh F7Ch F7Bh F7Ah F79h F78h F77h F76h F75h F74h F73h F72h F71h F70h F6Fh F6Eh F6Dh F6Ch F6Bh F6Ah F69h F68h F67h F66h F65h F64h F63h F62h F61h F60h
Name (2) (2) (2) PORTE PORTD(3) PORTC PORTB PORTA ANSELH ANSEL IOCB WPUB CM1CON0 CM2CON0 CM2CON1 SLRCON SSPMSK (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2) (2)
(2) IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 (2) OSCTUNE (2) (2) (2) (2) TRISE(3) TRISD(3) TRISC TRISB TRISA
(2)
FEEh POSTINC0
POSTDEC0(1) PREINC0(1) PLUSW0 FSR0L WREG INDF1(1) POSTDEC1(1) PREINC1(1) PLUSW1(1) FSR1H FSR1L BSR INDF2(1) POSTDEC2(1) PREINC2(1) PLUSW2(1) FSR2H FSR2L STATUS
(1)
FSR0H
FE6h POSTINC1(1)
(2) (2) (2) LATE(3) LATD(3) LATC LATB LATA (2)
FDEh POSTINC2(1)
This is not a physical register. Unimplemented registers are read as 0. This register is not available on PIC18F2XK20 devices. This register is only implemented in the PIC18F46K20 and PIC18F26K20 devices.
DS41303G-page 78
2010 Microchip Technology Inc.
PIC18F2XK20/4XK20
TABLE 24-2:
Mnemonic, Operands
PIC18FXXXX INSTRUCTION SET

16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes
BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB SUBWF SUBWFB SWAPF TSTFSZ XORWF Note 1: f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a f, d, a f, d, a f, d, a f, a f, d, a Add WREG and f Add WREG and CARRY bit to f AND WREG with f Clear f Complement f Compare f with WREG, skip = Compare f with WREG, skip > Compare f with WREG, skip < Decrement f Decrement f, Skip if 0 Decrement f, Skip if Not 0 Increment f Increment f, Skip if 0 Increment f, Skip if Not 0 Inclusive OR WREG with f Move f Move fs (source) to 1st word fd (destination) 2nd word Move WREG to f Multiply WREG with f Negate f Rotate Left f through Carry Rotate Left f (No Carry) Rotate Right f through Carry Rotate Right f (No Carry) Set f Subtract f from WREG with borrow Subtract WREG from f Subtract WREG from f with borrow Swap nibbles in f Test f, skip if 0 Exclusive OR WREG with f 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 (2 or 3) 1 (2 or 3) 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 0010 01da0 0010 0da 0001 01da 0110 101a 0001 11da 0110 001a 0110 010a 0110 000a 0000 01da 0010 11da 0100 11da 0010 10da 0011 11da 0100 10da 0001 00da 0101 00da 1100 ffff 1111 ffff 0110 111a 0000 001a 0110 110a 0011 01da 0100 01da 0011 00da 0100 00da 0110 100a 0101 01da 0101 0101 0011 0110 0001 11da 10da 10da 011a 10da ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff C, DC, Z, OV, N C, DC, Z, OV, N Z, N Z Z, N None None None C, DC, Z, OV, N None None C, DC, Z, OV, N None None Z, N Z, N None None None C, DC, Z, OV, N C, Z, N Z, N C, Z, N Z, N None C, DC, Z, OV, N 1, 2 1, 2 1,2 2 1, 2 4 4 1, 2 1, 2, 3, 4 1, 2, 3, 4 1, 2 1, 2, 3, 4 4 1, 2 1, 2 1
1, 2 1, 2
1, 2
ffff C, DC, Z, OV, N ffff C, DC, Z, OV, N ffff None ffff None ffff Z, N
1, 2
4 1, 2
2: 3: 4:
When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is 1 for a pin configured as input and is driven low by an external device, the data will be written back with a 0. If this instruction is executed on the TMR0 register (and where applicable, d = 1), the prescaler will be cleared if assigned. If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. Some instructions are two-word instructions. The second word of these instructions will be executed as a NOP unless the first word of the instruction retrieves the information embedded in these 16 bits. This ensures that all program memory locations have a valid instruction.
DS41303G-page 318
PIC18F2XK20/4XK20
TABLE 24-2:
Mnemonic, Operands BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG BC BN BNC BNN BNOV BNZ BOV BRA BZ CALL CLRWDT DAW GOTO NOP NOP POP PUSH RCALL RESET RETFIE RETLW RETURN SLEEP Note 1: f, b, a f, b, a f, b, a f, b, a f, d, a n n n n n n n n n n, s n n s k s Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f Branch if Carry Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Call subroutine 1st word 2nd word Clear Watchdog Timer Decimal Adjust WREG Go to address 1st word 2nd word No Operation No Operation Pop top of return stack (TOS) Push top of return stack (TOS) Relative Call Software device Reset Return from interrupt enable Return with literal in WREG Return from Subroutine Go into Standby mode 1 1 1 (2 or 3) 1 (2 or 3) 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 2 1 1 1 1 2 1 2 2 2 1 1001 1000 1011 1010 0111 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0000 0000 0000 bbba bbba bbba bbba bbba 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 1100 0000 0000 ffff ffff ffff ffff ffff nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 kkkk 0001 0000 ffff ffff ffff ffff ffff nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s None None None None None None None None None None None None None None None TO, PD C None 1, 2 1, 2 3, 4 3, 4 1, 2
PIC18FXXXX INSTRUCTION SET (CONTINUED)

CONTROL OPERATIONS
None None None None None All GIE/GIEH, PEIE/GIEL kkkk None 001s None 0011 TO, PD
2: 3: 4:
DS41303G-page 319
PIC18F2XK20/4XK20
TABLE 24-2:
Mnemonic, Operands LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR MOVLB MOVLW MULLW RETLW SUBLW XORLW TBLRD* TBLRD*+ TBLRD*TBLRD+* TBLWT* TBLWT*+ TBLWT*TBLWT+* Note 1: k k k f, k k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSR(f) 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG from literal Exclusive OR literal with WREG Table Read Table Read with post-increment Table Read with post-decrement Table Read with pre-increment Table Write Table Write with post-increment Table Write with post-decrement Table Write with pre-increment 1 1 1 2 1 1 1 2 1 1 2 0000 0000 0000 1110 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1011 1001 1110 0000 0001 1110 1101 1100 1000 1010 0000 0000 0000 0000 0000 0000 0000 0000 kkkk kkkk kkkk 00ff kkkk 0000 kkkk kkkk kkkk kkkk kkkk 0000 0000 0000 0000 0000 0000 0000 0000 kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 1000 1001 1010 1011 1100 1101 1110 1111 C, DC, Z, OV, N Z, N Z, N None None None None None C, DC, Z, OV, N Z, N None None None None None None None None
PIC18FXXXX INSTRUCTION SET (CONTINUED)

DATA MEMORY
PROGRAM MEMORY OPERATIONS
2: 3: 4:
DS41303G-page 320
PIC18F2XK20/4XK20
24.1.1
ADDLW
Syntax: Operands: Operation: Status Affected: Encoding: Description:
STANDARD INSTRUCTION SET

ADD literal to W
ADDLW 0 k 255 W Operation: kkkk kkkk Status Affected: Encoding: Description: k
ADDWF
Syntax: Operands:
ADD W to f
ADDWF 0 d a f 255 [0,1] [0,1] dest f {,d {,a}}
(W) + k
N, OV, C, DC, Z 0000 1111
(W) + (f)
N, OV, C, DC, Z 0010 01da ffff ffff
The contents of W are added to the 8-bit literal k and the result is placed in W. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode
Q2 Read literal k
Q3 Process Data
Q4 Write to W
Example:
ADDLW
15h
Before Instruction W = 10h After Instruction W = 25h Words: Cycles:
Add W to register f. If d is 0, the result is stored in W. If d is 1, the result is stored back in register f (default). If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
Q Cycle Activity: Q1 Decode Q2 Read register f ADDWF 17h 0C2h 0D9h 0C2h Q3 Process Data REG, 0, 0 Q4 Write to destination
Example: W = REG = After Instruction W REG = =
Before Instruction
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction format then becomes: {label} instruction argument(s).
DS41303G-page 321
PIC18F2XK20/4XK20
ADDWFC
Syntax: Operands:
ADD W and CARRY bit to f

ADDWFC 0 d a f 255 [0,1] [0,1] dest f {,d {,a}}
ANDLW
Syntax: Operands: Operation: Status Affected: Encoding:
AND literal with W

ANDLW 0 k 255 W k
(W) .AND. k N, Z 0000
Operation: Status Affected: Encoding: Description:
(W) + (f) + (C) N,OV, C, DC, Z 0010 00da
1011
kkkk
kkkk
ffff
ffff
Description: Words: Cycles: Q Cycle Activity: Q1 Decode
The contents of W are ANDed with the 8-bit literal k. The result is placed in W. 1 1 Q2 Read literal k ANDLW A3h 03h Q3 Process Data 05Fh Q4 Write to W
Add W, the CARRY flag and data memory location f. If d is 0, the result is placed in W. If d is 1, the result is placed in data memory location f. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
Example: W = After Instruction W =
Before Instruction
Q2 Read register f ADDWFC 1 02h 4Dh 0 02h 50h
Q3 Process Data REG, 0, 1
Q4 Write to destination
Example:
Before Instruction CARRY bit = REG = W = After Instruction CARRY bit = REG = W =
DS41303G-page 322
PIC18F2XK20/4XK20
ANDWF
Syntax: Operands:
AND W with f
ANDWF 0 d a f 255 [0,1] [0,1] dest f {,d {,a}}
BC
Syntax: Operands: Operation: Status Affected: Encoding: ffff ffff
Branch if Carry
BC -128 n n 127
if CARRY bit is 1 (PC) + 2 + 2n PC None 1110 0010 nnnn nnnn
(W) .AND. (f) N, Z 0001
01da
Description:
The contents of W are ANDed with register f. If d is 0, the result is stored in W. If d is 1, the result is stored back in register f (default). If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
If the CARRY bit is 1, then the program will branch. The 2s complement number 2n is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation
Q2 Read literal n No operation Q2 Read literal n HERE = = = = =
Q3 Process Data No operation Q3 Process Data BC 5
Q4 Write to PC No operation Q4 No operation
Q2 Read register f ANDWF 17h C2h 02h C2h
If No Jump: Q1 Decode
Example:
Before Instruction
Before Instruction PC After Instruction If CARRY PC If CARRY PC
address (HERE) 1; address (HERE + 12) 0; address (HERE + 2)
DS41303G-page 323
PIC18F2XK20/4XK20
BCF
Syntax: Operands:
Bit Clear f
BCF 0 0 a 0 f, b {,a}
BN
Syntax: Operands: Operation: Status Affected: Encoding: bbba ffff ffff Description:
Branch if Negative
BN -128 n n 127
f 255 b 7 [0,1] f
if NEGATIVE bit is 1 (PC) + 2 + 2n PC None 1110 0110 nnnn nnnn
None 1001
Bit b in register f is cleared. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
If the NEGATIVE bit is 1, then the program will branch. The 2s complement number 2n is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode
Q3 Process Data No operation Q3 Process Data BN Jump
Q2 Read register f BCF
Q3 Process Data FLAG_REG, C7h 47h
Q4 Write register f 7, 0
No operation If No Jump: Q1 Decode
Example:
Before Instruction FLAG_REG = After Instruction FLAG_REG =
Example:
Before Instruction PC After Instruction If NEGATIVE PC If NEGATIVE PC
address (HERE) 1; address (Jump) 0; address (HERE + 2)
DS41303G-page 324
PIC18F2XK20/4XK20
BNC
Branch if Not Carry

BNC -128 n n 127
BNN
Syntax: Operands: Operation: Status Affected:
Branch if Not Negative

BNN -128 n n 127
if CARRY bit is 0 (PC) + 2 + 2n PC None 1110 0011 nnnn nnnn
if NEGATIVE bit is 0 (PC) + 2 + 2n PC None 1110 0111 nnnn nnnn
Encoding: Description:
If the CARRY bit is 0, then the program will branch. The 2s complement number 2n is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
If the NEGATIVE bit is 0, then the program will branch. The 2s complement number 2n is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode
Words: Cycles: Q Cycle Activity: If Jump: Q2 Q3 Process Data No operation Q3 Process Data BNC Jump Q4 Write to PC No operation Q4 No operation Q1 Decode No operation If No Jump: Q2 Q1 Decode
Q3 Process Data No operation Q3 Process Data BNN Jump
Read literal n No operation
Read literal n HERE = = = = =
Example:
Example:
Before Instruction PC After Instruction If CARRY PC If CARRY PC
Before Instruction PC After Instruction If NEGATIVE PC If NEGATIVE PC
DS41303G-page 325
PIC18F2XK20/4XK20
BNOV
Branch if Not Overflow

BNOV -128 n n 127
BNZ
Branch if Not Zero

BNZ -128 n n 127
if OVERFLOW bit is 0 (PC) + 2 + 2n PC None 1110 0101 nnnn nnnn
if ZERO bit is 0 (PC) + 2 + 2n PC None 1110 0001 nnnn nnnn
Encoding: Description:
If the OVERFLOW bit is 0, then the program will branch. The 2s complement number 2n is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
If the ZERO bit is 0, then the program will branch. The 2s complement number 2n is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Words: Cycles: Q Cycle Activity: If Jump: Q2 Q3 Process Data No operation Q3 Process Data BNOV Jump address (HERE) 0; address (Jump) 1; address (HERE + 2) Q4 Write to PC No operation Q4 No operation Q1 Decode No operation If No Jump: Q2 Q1 Decode
Q3 Process Data No operation Q3 Process Data BNZ Jump
Read literal n No operation
Read literal n HERE
Example:
Example:
Before Instruction PC = After Instruction If OVERFLOW = PC = If OVERFLOW = PC =
Before Instruction PC After Instruction If ZERO PC If ZERO PC
DS41303G-page 326
PIC18F2XK20/4XK20
BRA
Unconditional Branch
BRA -1024 n n 1023 PC
BSF
Syntax: Operands:
Bit Set f
BSF 0 0 a 1 f, b {,a}
(PC) + 2 + 2n None 1101
f 255 b 7 [0,1] f
Operation: 0nnn nnnn nnnn Status Affected: Encoding: Description:
None 1000 bbba ffff ffff
Add the 2s complement number 2n to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. 1 2
Words: Cycles: Q Cycle Activity: Q1 Decode No operation
Q2 Read literal n No operation
Q3 Process Data No operation
Q4 Write to PC No operation Words: Cycles:
Bit b in register f is set. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
Example:
Q Cycle Activity: HERE = = BRA Jump Q1 Decode Q2 Read register f BSF = = Q3 Process Data Q4 Write register f
Before Instruction PC After Instruction PC
address (HERE) address (Jump)
Example:
FLAG_REG, 7, 1 0Ah 8Ah
Before Instruction FLAG_REG After Instruction FLAG_REG
DS41303G-page 327
PIC18F2XK20/4XK20
BTFSC
Syntax: Operands:
Bit Test File, Skip if Clear

BTFSC f, b {,a} 0 0 a f 255 b 7 [0,1]
BTFSS
Syntax: Operands:
Bit Test File, Skip if Set

BTFSS f, b {,a} 0 0 a f 255 b<7 [0,1]
skip if (f) = 0 None 1011 bbba ffff ffff
skip if (f) = 1 None 1010 bbba ffff ffff
If bit b in register f is 0, then the next instruction is skipped. If bit b is 0, then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction.
If bit b in register f is 1, then the next instruction is skipped. If bit b is 1, then the next instruction fetched during the current instruction execution is discarded and a NOP is executed instead, making this a two-cycle instruction. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation BTFSS : : Q4 No operation Q4 No operation Q4 No operation No operation
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE FALSE TRUE = = = = = Q3 No operation Q3 No operation No operation BTFSC : : Q4 No operation Q4 No operation No operation Q2 Read register f Q3 Process Data Q4 No operation
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE FALSE TRUE = = = = = Q2 Read register f
If skip and followed by 2-word instruction:
FLAG, 1, 0
FLAG, 1, 0
Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC
address (HERE) 0; address (TRUE) 1; address (FALSE)
Before Instruction PC After Instruction If FLAG<1> PC If FLAG<1> PC
address (HERE) 0; address (FALSE) 1; address (TRUE)
DS41303G-page 328
PIC18F2XK20/4XK20
BTG
Syntax: Operands:
Bit Toggle f
BTG f, b {,a} 0 0 a f 255 b<7 [0,1] f
BOV
Syntax: Operands: Operation: Status Affected: Encoding: ffff ffff
Branch if Overflow
BOV -128 n n 127
if OVERFLOW bit is 1 (PC) + 2 + 2n PC None 1110 0100 nnnn nnnn
(f) None 0111
bbba
Description:
Bit b in data memory location f is inverted. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
If the OVERFLOW bit is 1, then the program will branch. The 2s complement number 2n is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
Q2 Read literal n No operation Q2 Read literal n HERE
Q3 Process Data No operation Q3 Process Data BOV Jump
Q2 Read register f BTG
Q3 Process Data PORTC, 4, 0
Q4 Write register f
Example:
Before Instruction: PORTC = 0111 0101 [75h] After Instruction: PORTC = 0110 0101 [65h]
Example:
Before Instruction PC = After Instruction If OVERFLOW = PC = If OVERFLOW = PC =
DS41303G-page 329
PIC18F2XK20/4XK20
BZ
Branch if Zero
BZ -128 n n 127
CALL
Syntax: Operands: Operation:
Subroutine Call
CALL k {,s} 0 s k 1048575 [0,1]
if ZERO bit is 1 (PC) + 2 + 2n PC None 1110 0000 nnnn nnnn
If the ZERO bit is 1, then the program will branch. The 2s complement number 2n is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is then a two-cycle instruction. 1 1(2)
(PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (Status) STATUSS, (BSR) BSRS None 1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8
Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description:
Q3 Process Data No operation Q3 Process Data BZ Jump
Subroutine call of entire 2-Mbyte memory range. First, return address (PC + 4) is pushed onto the return stack. If s = 1, the W, Status and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If s = 0, no update occurs (default). Then, the 20-bit value k is loaded into PC<20:1>. CALL is a two-cycle instruction. 2 2
Q2
Q3
Q4 Read literal k<19:8>, Write to PC No operation
Read literal PUSH PC to k<7:0>, stack No operation HERE No operation CALL
Example:
Before Instruction PC After Instruction If ZERO PC If ZERO PC
No operation Example:
THERE, 1
Before Instruction PC = After Instruction PC = TOS = WS = BSRS = STATUSS =
address (HERE) address (THERE) address (HERE + 4) W BSR Status
DS41303G-page 330
PIC18F2XK20/4XK20
CLRF
Clear f
CLRF 0 a f {,a}
CLRWDT
Clear Watchdog Timer

CLRWDT None 000h WDT, WDT postscaler, 000h 1 TO, 1 PD TO, PD 0000 0000 0000 0100
f 255 [0,1] f
000h 1 Z Z 0110
101a
ffff
ffff
Status Affected: Encoding: Description:
Clears the contents of the specified register. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
CLRWDT instruction resets the

Watchdog Timer. It also resets the postscaler of the WDT. Status bits, TO and PD, are set.
1 1 Q2 No operation CLRWDT = = = = = ? 00h 0 1 1 Q3 Process Data Q4 No operation
Example: Q2 Q3 Process Data FLAG_REG, 1 5Ah 00h Q4 Write register f
Read register f CLRF = =
Example:
Before Instruction WDT Counter After Instruction WDT Counter WDT Postscaler TO PD
Before Instruction FLAG_REG After Instruction FLAG_REG
DS41303G-page 331
PIC18F2XK20/4XK20
COMF
Syntax: Operands:
Complement f
COMF 0 d a (f) N, Z 0001 11da ffff ffff f {,d {,a}}
CPFSEQ
Compare f with W, skip if f = W

CPFSEQ 0 a f 255 [0,1] f {,a}
f 255 [0,1] [0,1] dest
(f) (W), skip if (f) = (W) (unsigned comparison) None 0110 001a ffff ffff Compares the contents of data memory location f to the contents of W by performing an unsigned subtraction. If f = W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q4 No operation Q4 No operation Q4 No operation No operation
The contents of register f are complemented. If d is 0, the result is stored in W. If d is 1, the result is stored back in register f (default). If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
Words: Q2 Read register f COMF 13h If skip: 13h ECh Q3 Process Data REG, 0, 0 Q4 Write to destination Q Cycle Activity: Q1 Decode Cycles:
Example:
Q2 Read register f
Before Instruction REG = After Instruction REG = W =
Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NEQUAL EQUAL = = = = = =
CPFSEQ REG, 0 : : HERE ? ? W; Address (EQUAL) W; Address (NEQUAL)
Before Instruction PC Address W REG After Instruction If REG PC If REG PC
DS41303G-page 332
PIC18F2XK20/4XK20
CPFSGT
Compare f with W, skip if f > W

CPFSGT 0 a f 255 [0,1] f {,a}
CPFSLT
Compare f with W, skip if f < W

CPFSLT 0 a f 255 [0,1] f {,a}
(f) W), skip if (f) > (W) (unsigned comparison) None 0110 010a ffff ffff Compares the contents of data memory location f to the contents of the W by performing an unsigned subtraction. If the contents of f are greater than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction.
(f) W), skip if (f) < (W) (unsigned comparison) None 0110 000a ffff ffff
Compares the contents of data memory location f to the contents of W by performing an unsigned subtraction. If the contents of f are less than the contents of W, then the fetched instruction is discarded and a NOP is executed instead, making this a two-cycle instruction. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation Q4 No operation Q4 No operation Q4 No operation No operation
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 Q2 No operation Q2 No operation No operation HERE NLESS LESS = = < = = No operation Q1 Q2 Read register f
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 Q2 Q3 No No No operation operation operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No No No operation operation operation No No No operation operation operation Example: HERE NGREATER GREATER = = Q4 No operation Q4 No operation No operation Q2 Read register f Q3 Process Data Q4 No operation
If skip and followed by 2-word instruction: No operation No operation Example:
CPFSLT REG, 1 : : Address (HERE) ? W; Address (LESS) W; Address (NLESS)
CPFSGT REG, 0 : :
Before Instruction PC W After Instruction If REG PC If REG PC
Before Instruction PC W After Instruction If REG PC If REG PC
Address (HERE) ? W; Address (GREATER) W; Address (NGREATER)
= =
DS41303G-page 333
PIC18F2XK20/4XK20
DAW
Decimal Adjust W Register

DAW None If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0>; If [W<7:4> + DC > 9] or [C = 1] then (W<7:4>) + 6 + DC W<7:4> ; else (W<7:4>) + DC W<7:4>
DECF
Syntax: Operands:
Decrement f
DECF f {,d {,a}} 0 d a f 255 [0,1] [0,1] dest
(f) 1
C, DC, N, OV, Z 0000 01da ffff ffff
C 0000 0000 0000 0111
DAW adjusts the eight-bit value in W, resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. 1 1 Words: Q2 Read register W DAW Q3 Process Data Q4 Write W Cycles: Q Cycle Activity: Q1 Decode
Words: Cycles: Q Cycle Activity: Q1 Decode Example1:
Decrement register f. If d is 0, the result is stored in W. If d is 1, the result is stored back in register f (default). If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1 Q2 Read register f DECF 01h 0 00h 1 Q3 Process Data CNT, 1, 0 Q4 Write to destination
Before Instruction W = C = DC = After Instruction W C DC Example 2: = = = A5h 0 0 05h 1 0 Example:
Before Instruction CNT = Z = After Instruction CNT = Z =
Before Instruction W = C = DC = After Instruction W C DC = = = CEh 0 0 34h 1 0
DS41303G-page 334
PIC18F2XK20/4XK20
DECFSZ
Syntax: Operands:
Decrement f, skip if 0
DECFSZ f {,d {,a}} 0 d a f 255 [0,1] [0,1]
DCFSNZ
Syntax: Operands:
Decrement f, skip if not 0

DCFSNZ 0 d a f 255 [0,1] [0,1] f {,d {,a}}
(f) 1 dest, skip if result = 0 None 0010 11da ffff ffff
(f) 1 dest, skip if result 0 None 0100 11da ffff ffff
The contents of register f are decremented. If d is 0, the result is placed in W. If d is 1, the result is placed back in register f (default). If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction.
Words: Cycles:
The contents of register f are decremented. If d is 0, the result is placed in W. If d is 1, the result is placed back in register f (default). If the result is not 0, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation DCFSNZ : : = = = = = ? TEMP 1, 0; Address (ZERO) 0; Address (NZERO) Q4 Write to destination Q4 No operation Q4 No operation No operation
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE CONTINUE Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC = Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE + 2) Q3 No operation Q3 No operation No operation DECFSZ GOTO Q4 No operation Q4 No operation No operation CNT, 1, 1 LOOP If skip: Q1 No operation Q1 No operation No operation Example: Q2 Q2 Read register f Q3 Process Data Q4 Write to destination Q Cycle Activity: Q1 Decode Q2
Read register f
No operation Q2 No operation No operation HERE ZERO NZERO
TEMP, 1, 0
Before Instruction TEMP After Instruction TEMP If TEMP PC If TEMP PC
DS41303G-page 335
PIC18F2XK20/4XK20
GOTO
Syntax: Operands: Operation: Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description:
Unconditional Branch
GOTO k 0 k k 1048575
INCF
Syntax: Operands:
Increment f
INCF 0 d a f {,d {,a}}
PC<20:1> Operation: 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 Status Affected: Encoding: Description:
f 255 [0,1] [0,1] dest
None 1110 1111
(f) + 1
C, DC, N, OV, Z 0010 10da ffff ffff
GOTO allows an unconditional branch

anywhere within entire 2-Mbyte memory range. The 20-bit value k is loaded into PC<20:1>. GOTO is always a two-cycle instruction.
2 2 Q2 Read literal k<7:0>, No operation GOTO THERE Q3 No operation No operation Q4 Read literal k<19:8>, Write to PC No operation
The contents of register f are incremented. If d is 0, the result is placed in W. If d is 1, the result is placed back in register f (default). If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
Q2 Read register f INCF FFh 0 ? ? 00h 1 1 1
Q3 Process Data CNT, 1, 0
After Instruction PC = Address (THERE)
Example:
Before Instruction CNT = Z = C = DC = After Instruction CNT = Z = C = DC =
DS41303G-page 336
PIC18F2XK20/4XK20
INCFSZ
Syntax: Operands:
Increment f, skip if 0
INCFSZ 0 d a f 255 [0,1] [0,1] f {,d {,a}}
INFSNZ
Syntax: Operands:
Increment f, skip if not 0

INFSNZ 0 d a f 255 [0,1] [0,1] f {,d {,a}}
(f) + 1 dest, skip if result = 0 None 0011 11da ffff ffff
dest, (f) + 1 skip if result 0 None 0100 10da ffff ffff The contents of register f are incremented. If d is 0, the result is placed in W. If d is 1, the result is placed back in register f (default). If the result is not 0, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q3 Process Data Q3 No operation Q3 No operation No operation INFSNZ Q4 Write to destination Q4 No operation Q4 No operation No operation
The contents of register f are incremented. If d is 0, the result is placed in W. If d is 1, the result is placed back in register f (default). If the result is 0, the next instruction, which is already fetched, is discarded and a NOP is executed instead, making it a two-cycle instruction. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction.
Words: Cycles:
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE NZERO ZERO Q3 No operation Q3 No operation No operation INCFSZ : : Q4 No operation Q4 No operation No operation Q2 Read register f Q3 Process Data Q4 Write to destination
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE ZERO NZERO Q2 Read register f
CNT, 1, 0
REG, 1, 0
Before Instruction PC = After Instruction CNT = If CNT = PC = If CNT PC =
Address (HERE) CNT + 1 0; Address (ZERO) 0; Address (NZERO)
Before Instruction PC = After Instruction REG = If REG PC = If REG = PC =
Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO)
DS41303G-page 337
PIC18F2XK20/4XK20
IORLW
Inclusive OR literal with W

IORLW k 0 k 255 W
IORWF
Syntax: Operands:
Inclusive OR W with f
IORWF 0 d a f {,d {,a}}
(W) .OR. k N, Z 0000
f 255 [0,1] [0,1] dest
Operation: 1001 kkkk kkkk Status Affected: Encoding: Description:
(W) .OR. (f) N, Z 0001
The contents of W are ORed with the eight-bit literal k. The result is placed in W. 1 1
00da
ffff
ffff
Q2 Read literal k IORLW 9Ah
Q3 Process Data 35h
Q4 Write to W
Example: W = After Instruction W =
Before Instruction
Inclusive OR W with register f. If d is 0, the result is placed in W. If d is 1, the result is placed back in register f (default). If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
Words: BFh Cycles: Q Cycle Activity: Q1 Decode
Q2 Read register f IORWF 13h 91h 13h 93h
Q3 Process Data RESULT, 0, 1
Example:
Before Instruction RESULT = W = After Instruction RESULT = W =
DS41303G-page 338
PIC18F2XK20/4XK20
LFSR
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal k MSB Q3 Process Data Q4 Write literal k MSB to FSRfH Write literal k to FSRfL
Load FSR
LFSR f, k 0 0 k f 2 k 4095 FSRf
MOVF
Syntax: Operands:
Move f
MOVF 0 d a f f {,d {,a}}
f 255 [0,1] [0,1] dest
None 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk
N, Z 0101 00da ffff ffff
The 12-bit literal k is loaded into the File Select Register pointed to by f. 2 2
Decode
Read literal k LSB
Process Data
Example: After Instruction FSR2H FSR2L
LFSR 2, 3ABh = = 03h ABh Words: Cycles: Q Cycle Activity: Q1 Decode
The contents of register f are moved to a destination dependent upon the status of d. If d is 0, the result is placed in W. If d is 1, the result is placed back in register f (default). Location f can be anywhere in the 256-byte bank. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1 Q2 Read register f MOVF = = = = Q3 Process Data REG, 0, 0 22h FFh 22h 22h Q4 Write W
Example:
Before Instruction REG W After Instruction REG W
DS41303G-page 339
PIC18F2XK20/4XK20
MOVFF
Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description:
Move f to f
MOVFF fs,fd 0 0 (fs) None 1100 1111 ffff ffff ffff ffff ffffs ffffd fs fd 4095 4095 fd
MOVLB
Move literal to low nibble in BSR

MOVLW k 0 k k 255
BSR
0000 0001 kkkk kkkk
None
The contents of source register fs are moved to destination register fd. Location of source fs can be anywhere in the 4096-byte data space (000h to FFFh) and location of destination fd can also be anywhere from 000h to FFFh. Either source or destination can be W (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. 2 2 (3)
The eight-bit literal k is loaded into the Bank Select Register (BSR). The value of BSR<7:4> always remains 0, regardless of the value of k7:k4. 1 1
Q2 Read literal k MOVLB 02h 05h
Q3 Process Data 5
Q4 Write literal k to BSR
Example:
Before Instruction BSR Register = After Instruction BSR Register =
Q2 Read register f (src) No operation No dummy read
Q4 No operation Write register f (dest)
Decode
Example:
MOVFF = = = =
REG1, REG2 33h 11h 33h 33h
Before Instruction REG1 REG2 After Instruction REG1 REG2
DS41303G-page 340
PIC18F2XK20/4XK20
MOVLW
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal k MOVLW W = 5Ah Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read register f MOVWF 4Fh FFh 4Fh 4Fh Q3 Process Data REG, 0 Q4 Write register f Q3 Process Data 5Ah Q4 Write to W
Move literal to W
MOVLW k 0 k k W 255
MOVWF
Move W to f
MOVWF 0 a (W) None 0110 111a ffff ffff f 255 [0,1] f f {,a}
None 0000 1110 kkkk kkkk
The eight-bit literal k is loaded into W. 1 1
Example: After Instruction
Move data from W to register f. Location f can be anywhere in the 256-byte bank. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
Before Instruction
DS41303G-page 341
PIC18F2XK20/4XK20
MULLW
Multiply literal with W

MULLW 0 k k
MULWF
Multiply W with f
MULWF 0 a f 255 [0,1] PRODH:PRODL f {,a}
255 PRODH:PRODL
(W) x k None 0000
(W) x (f) None 0000
1101
kkkk
kkkk
An unsigned multiplication is carried out between the contents of W and the 8-bit literal k. The 16-bit result is placed in the PRODH:PRODL register pair. PRODH contains the high byte. W is unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. 1 1
001a
ffff
ffff
Q2 Read literal k
Q3 Process Data
Q4 Write registers PRODH: PRODL
Example: Before Instruction W PRODH PRODL After Instruction W PRODH PRODL
MULLW = = = = = =
0C4h E2h ? ? E2h ADh 08h Words: Cycles: Q Cycle Activity: Q1 Decode
An unsigned multiplication is carried out between the contents of W and the register file location f. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both W and f are unchanged. None of the Status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1 Q2 Read register f Q3 Process Data Q4 Write registers PRODH: PRODL
Example: Before Instruction W REG PRODH PRODL After Instruction W REG PRODH PRODL
MULWF = = = = = = = =
REG, 1 C4h B5h ? ? C4h B5h 8Ah 94h
DS41303G-page 342
PIC18F2XK20/4XK20
NEGF
Negate f
NEGF 0 a f {,a}
NOP
Syntax: Operands: Operation: f Status Affected: Encoding: ffff ffff Description: Words: Cycles: Q Cycle Activity: Q1 Decode 110a
No Operation
NOP None No operation None 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx
f 255 [0,1]
(f)+1
N, OV, C, DC, Z 0110
Location f is negated using twos complement. The result is placed in the data memory location f. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
No operation. 1 1 Q2 No operation Q3 No operation Q4 No operation
Example: None.
Q2 Read register f NEGF
Q3 Process Data REG, 1
Q4 Write register f
Example:
Before Instruction REG = After Instruction REG =
0011 1010 [3Ah] 1100 0110 [C6h]
DS41303G-page 343
PIC18F2XK20/4XK20
POP
Pop Top of Return Stack

POP None (TOS) None 0000 0000 0000 0110 bit bucket
PUSH
Push Top of Return Stack

PUSH None (PC + 2) None 0000 0000 0000 0101 TOS
The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. 1 1
The PC + 2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS and then pushing it onto the return stack. 1 1
Words: Cycles: Q Cycle Activity: Q1
Q2 PUSH PC + 2 onto return stack PUSH = =
Q3 No operation
Q4 No operation
Q2 No operation POP GOTO
Q3 POP TOS value
Q4 No operation
Decode
Example:
Example: NEW = = 0031A2h 014332h
Before Instruction TOS Stack (1 level down) After Instruction TOS PC
Before Instruction TOS PC After Instruction PC TOS Stack (1 level down)
345Ah 0124h
= =
014332h NEW
= = =
0126h 0126h 345Ah
DS41303G-page 344
PIC18F2XK20/4XK20
RCALL
Relative Call
RCALL -1024 n n 1023
RESET
Reset
RESET None Reset all registers and flags that are affected by a MCLR Reset. All 0000 0000 1111 1111
(PC) + 2 TOS, PC (PC) + 2 + 2n None 1101 1nnn nnnn nnnn
Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode
Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack. Then, add the 2s complement number 2n to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction. 1 2
This instruction provides a way to execute a MCLR Reset by software. 1 1 Q2 Start Reset RESET Reset Value Reset Value Q3 No operation Q4 No operation
Example: Q2 Q3 Process Data Q4 Write to PC After Instruction Registers = Flags* =
Read literal n PUSH PC to stack
No operation HERE
No operation RCALL Jump
No operation
Before Instruction PC = Address (HERE) After Instruction PC = Address (Jump) TOS = Address (HERE + 2)
DS41303G-page 345
PIC18F2XK20/4XK20
RETFIE
Return from Interrupt

RETFIE {s} s [0,1]
RETLW
Return literal to W
RETLW k 0 k 255
(TOS) PC, GIE/GIEH or PEIE/GIEL, 1 if s = 1 (WS) W, Status, (STATUSS) (BSRS) BSR, PCLATU, PCLATH are unchanged. GIE/GIEH, PEIE/GIEL. 0000 0000 0001 000s
k W, PC, (TOS) PCLATU, PCLATH are unchanged None 0000 1100 kkkk kkkk
Return from interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting either the high or low priority global interrupt enable bit. If s = 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, Status and BSR. If s = 0, no update of these registers occurs (default). 1 2
W is loaded with the eight-bit literal k. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. 1 2
Q2 Read literal k No operation
Q4 POP PC from stack, Write to W No operation
No operation Example: Q2 Q3 No operation Q4 POP PC from stack Set GIEH or GIEL
No operation
No operation RETFIE 1
No operation
No operation
After Interrupt PC W BSR Status GIE/GIEH, PEIE/GIEL
= = = = =
TOS WS BSRS STATUSS 1
CALL TABLE ; ; ; ; : TABLE ADDWF PCL ; RETLW k0 ; RETLW k1 ; : : RETLW kn ; Before Instruction W = After Instruction W =
contains table offset value now has table value
= offset Begin table
End of table
07h value of kn
DS41303G-page 346
PIC18F2XK20/4XK20
RETURN
Return from Subroutine

RETURN {s} s [0,1]
RLCF
Syntax: Operands:
Rotate Left f through Carry

RLCF 0 d a f {,d {,a}}
(TOS) PC, if s = 1 (WS) W, (STATUSS) Status, BSR, (BSRS) PCLATU, PCLATH are unchanged None 0000 0000 0001 001s
f 255 [0,1] [0,1]
Operation:
(f<n>) dest<n + 1>, (f<7>) C, dest<0> (C) C, N, Z 0011 01da ffff ffff
Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If s= 1, the contents of the shadow registers, WS, STATUSS and BSRS, are loaded into their corresponding registers, W, Status and BSR. If s = 0, no update of these registers occurs (default). 1 2
Q2 No operation No operation
Q4 POP PC from stack No operation Words: Cycles: Q Cycle Activity:
The contents of register f are rotated one bit to the left through the CARRY flag. If d is 0, the result is placed in W. If d is 1, the result is stored back in register f (default). If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. C 1 1 register f
Example:
RETURN
Q1 Decode
Q2 Read register f RLCF
Q3 Process Data
After Instruction: PC = TOS
Example: Before Instruction REG = C = After Instruction REG = = C =
REG, 0, 0
1110 0110 0 1110 0110 1100 1100 1
DS41303G-page 347
PIC18F2XK20/4XK20
RLNCF
Syntax: Operands:
Rotate Left f (No Carry)

RLNCF 0 d a f 255 [0,1] [0,1] dest<n + 1>, dest<0> f {,d {,a}}
RRCF
Syntax: Operands:
Rotate Right f through Carry

RRCF 0 d a f {,d {,a}}
f 255 [0,1] [0,1]
(f<n>) (f<7>) N, Z 0100
Operation:
(f<n>) dest<n 1>, (f<0>) C, dest<7> (C) C, N, Z 0011 00da ffff ffff
01da
ffff
ffff
The contents of register f are rotated one bit to the left. If d is 0, the result is placed in W. If d is 1, the result is stored back in register f (default). If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. register f
The contents of register f are rotated one bit to the right through the CARRY flag. If d is 0, the result is placed in W. If d is 1, the result is placed back in register f (default). If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. C register f
1 1 Words: Q2 Read register f RLNCF Q3 Process Data Q4 Write to destination Cycles: Q Cycle Activity: Q1 Decode Q2 1 1
Example: Before Instruction REG = After Instruction REG =
REG, 1, 0 Example:
Read register f RRCF
1010 1011 0101 0111
Before Instruction REG = C = After Instruction REG = = C =
1110 0110 0 1110 0110 0111 0011 0
DS41303G-page 348
PIC18F2XK20/4XK20
RRNCF
Syntax: Operands:
Rotate Right f (No Carry)

RRNCF 0 d a f {,d {,a}}
SETF
Set f
SETF 0 a f {,a}
f 255 [0,1] [0,1] dest<n 1>, dest<7>
f 255 [0,1] f
FFh None
(f<n>) (f<0>) N, Z 0100
0110
100a
ffff
ffff
00da
ffff
ffff
Description:
The contents of register f are rotated one bit to the right. If d is 0, the result is placed in W. If d is 1, the result is placed back in register f (default). If a is 0, the Access Bank will be selected (default), overriding the BSR value. If a is 1, then the bank will be selected as per the BSR value. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. register f
The contents of the specified register are set to FFh. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
Q2 Read register f SETF = = 5Ah FFh
Q3 Process Data REG, 1
Q4 Write register f
1 1 Q2 Read register f RRNCF Q3 Process Data REG, 1, 0 Q4 Write to destination Example:
Before Instruction REG After Instruction REG
Example 1:
Before Instruction REG = After Instruction REG = Example 2: W = REG = After Instruction REG = =
1101 0111 1110 1011 REG, 0, 0
RRNCF
Before Instruction ? 1101 0111 1110 1011 1101 0111
DS41303G-page 349
PIC18F2XK20/4XK20
SLEEP
Enter Sleep mode

SLEEP None 00h WDT, WDT postscaler, 0 1 TO, 0 PD TO, PD 0000 0000 0000 0011
SUBFWB
Syntax: Operands:
Subtract f from W with borrow

SUBFWB 0 d a f 255 [0,1] [0,1] dest f {,d {,a}}
(W) (f) (C) N, OV, C, DC, Z 0101 01da
ffff
ffff
The Power-down Status bit (PD) is cleared. The Time-out Status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into Sleep mode with the oscillator stopped. 1 1
Q2 No operation SLEEP
Q3 Process Data
Q4 Go to Sleep Words: Cycles: Q Cycle Activity: Q1 Decode
Subtract register f and CARRY flag (borrow) from W (2s complement method). If d is 0, the result is stored in W. If d is 1, the result is stored in register f (default). If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1 Q2 Read register f Q3 Process Data Q4 Write to destination
Example: Before Instruction TO = ? ? PD =
After Instruction TO = 1 PD = 0 If WDT causes wake-up, this bit is cleared.
Example 1: SUBFWB REG, 1, 0 Before Instruction REG = 3 W = 2 C = 1 After Instruction REG = FF W = 2 C = 0 Z = 0 N = 1 ; result is negative Example 2: SUBFWB REG, 0, 0 Before Instruction REG = 2 W = 5 C = 1 After Instruction REG = 2 W = 3 C = 1 Z = 0 N = 0 ; result is positive Example 3: SUBFWB REG, 1, 0 Before Instruction REG = 1 W = 2 C = 0 After Instruction REG = 0 W = 2 C = 1 Z = 1 ; result is zero N = 0
DS41303G-page 350
PIC18F2XK20/4XK20
SUBLW
Syntax: Operands: Operation: Status Affected: Encoding: Description Words: Cycles: Q Cycle Activity: Q1 Decode Example 1: Before Instruction W = C = After Instruction W = C = Z = N = Example 2: Before Instruction W = C = After Instruction W = C = Z = N = Example 3: Before Instruction W = C = After Instruction W = C = Z = N = Q2 Read literal k SUBLW 01h ? 01h 1 ; result is positive 0 0 SUBLW 02h ? 00h 1 ; result is zero 1 0 SUBLW 03h ? FFh ; (2s complement) 0 ; result is negative 0 1 02h 02h Q3 Process Data 02h Q4 Write to W
Subtract W from literal

SUBLW k 0 k 255 W
SUBWF
Syntax: Operands:
Subtract W from f
SUBWF 0 d a f 255 [0,1] [0,1] dest f {,d {,a}}
k (W)
N, OV, C, DC, Z 0000 1000 kkkk kkkk
(f) (W)
N, OV, C, DC, Z 0101 11da ffff ffff
W is subtracted from the eight-bit literal k. The result is placed in W. 1 1
Subtract W from register f (2s complement method). If d is 0, the result is stored in W. If d is 1, the result is stored back in register f (default). If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
Words: Cycles: Q Cycle Activity: Q1 Decode Example 1: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 2: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = W = C = After Instruction REG = W = C = Z = N =
Q2 Read register f SUBWF 3 2 ? 1 2 1 0 0 SUBWF 2 2 ? 2 0 1 1 0 SUBWF 1 2 ?
; result is positive
REG, 0, 0
; result is zero
REG, 1, 0
FFh ;(2s complement) 2 0 ; result is negative 0 1
DS41303G-page 351
PIC18F2XK20/4XK20
SUBWFB
Syntax: Operands:
Subtract W from f with Borrow

SUBWFB
0 d a f 255 [0,1] [0,1] dest ffff ffff
SWAPF
Syntax: Operands:
Swap f
SWAPF f {,d {,a}} 0 d a f 255 [0,1] [0,1] dest<7:4>, dest<3:0>
f {,d {,a}}
(f) (W) (C) N, OV, C, DC, Z 0101
(f<3:0>) (f<7:4>) None 0011
10da
Subtract W and the CARRY flag (borrow) from register f (2s complement method). If d is 0, the result is stored in W. If d is 1, the result is stored back in register f (default). If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
10da
ffff
ffff
Words: Cycles: Q Cycle Activity: Q1 Decode Example 1:
The upper and lower nibbles of register f are exchanged. If d is 0, the result is placed in W. If d is 1, the result is placed in register f (default). If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
Words: Cycles:
Q2 Read register f SUBWFB 19h 0Dh 1 0Ch 0Dh 1 0 0
Q Cycle Activity: Q1 Decode Q2 Read register f SWAPF 53h 35h Q3 Process Data REG, 1, 0 Q4 Write to destination
Before Instruction REG = = C = After Instruction REG = = C = Z = N = Example 2: Before Instruction REG = = C = After Instruction REG = W = C = Z = N = Example 3: Before Instruction REG = = C = After Instruction REG = C Z N = = = =
(0001 1001) (0000 1101) (0000 1100) (0000 1101) ; result is positive
Example:
Before Instruction REG = After Instruction REG =
SUBWFB REG, 0, 0 1Bh 1Ah 0 1Bh 00h 1 1 0 SUBWFB 03h 0Eh 1 F5h 0Eh 0 0 1 (0001 1011) (0001 1010) (0001 1011) ; result is zero REG, 1, 0 (0000 0011) (0000 1110) (1111 0101) ; [2s comp] (0000 1110) ; result is negative
DS41303G-page 352
PIC18F2XK20/4XK20
TBLRD
Table Read
TBLRD ( *; *+; *-; +*) None if TBLRD *, TABLAT; (Prog Mem (TBLPTR)) TBLPTR No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT;
TBLRD
Example1:
Table Read (Continued)

TBLRD *+ ; = = = = = 55h 00A356h 34h 34h 00A357h
Before Instruction TABLAT TBLPTR MEMORY (00A356h) After Instruction TABLAT TBLPTR Example2: TBLRD
+* ; = = = = = = AAh 01A357h 12h 34h 34h 01A358h
Status Affected: None Encoding: 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +*
Before Instruction TABLAT TBLPTR MEMORY (01A357h) MEMORY (01A358h) After Instruction TABLAT TBLPTR
Description:
This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: no change post-increment post-decrement pre-increment 1 2
Words: Cycles: Q1 Decode No operation
Q Cycle Activity: Q2 No operation No operation (Read Program Memory) Q3 No operation Q4 No operation
No No operation operation (Write TABLAT)
DS41303G-page 353
PIC18F2XK20/4XK20
TBLWT
Table Write
TBLWT ( *; *+; *-; +*) None if TBLWT*, (TABLAT) Holding Register; TBLPTR No Change; if TBLWT*+, (TABLAT) Holding Register; TBLPTR; (TBLPTR) + 1 if TBLWT*-, (TABLAT) Holding Register; TBLPTR; (TBLPTR) 1 if TBLWT+*, (TBLPTR) + 1 TBLPTR; Holding Register; (TABLAT) None 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +*
TBLWT
Example1:
Table Write (Continued) TBLWT *+;
Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After Instructions (table write completion) TABLAT = 55h TBLPTR = 00A357h HOLDING REGISTER (00A356h) = 55h Example 2:
TBLWT +*;
Status Affected: Encoding:
Description:
This instruction uses the 3 LSBs of TBLPTR to determine which of the 8 holding registers the TABLAT is written to. The holding registers are used to program the contents of Program Memory (P.M.). (Refer to Section 6.0 Flash Program Memory for additional details on programming Flash memory.) The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2-MByte address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: no change post-increment post-decrement pre-increment 1 2 Q1 Decode Q2 Q3 Q4
Before Instruction TABLAT = 34h TBLPTR = 01389Ah HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = FFh After Instruction (table write completion) TABLAT = 34h TBLPTR = 01389Bh HOLDING REGISTER (01389Ah) = FFh HOLDING REGISTER (01389Bh) = 34h
Words: Cycles: Q Cycle Activity:
No No No operation operation operation
No No No No operation operation operation operation (Write to (Read TABLAT) Holding Register )
DS41303G-page 354
PIC18F2XK20/4XK20
TSTFSZ
Test f, skip if 0
TSTFSZ f {,a} 0 a f 255 [0,1]
XORLW
Exclusive OR literal with W

XORLW k 0 k 255 W
(W) .XOR. k N, Z 0000
skip if f = 0 None 0110 011a ffff ffff
1010
kkkk
kkkk
Description:
If f = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction. If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction.
The contents of W are XORed with the 8-bit literal k. The result is placed in W. 1 1
Q2 Read literal k XORLW B5h 1Ah
Q3 Process Data 0AFh
Q4 Write to W
Example: Before Instruction W = After Instruction W =
Words: Cycles:
Q Cycle Activity: Q1 Decode If skip: Q1 No operation Q1 No operation No operation Example: Q2 No operation Q2 No operation No operation HERE NZERO ZERO = = = = Q3 No operation Q3 No operation No operation TSTFSZ : : Q4 No operation Q4 No operation No operation Q2 Read register f Q3 Process Data Q4 No operation
CNT, 1
Before Instruction PC After Instruction If CNT PC If CNT PC
Address (HERE) 00h, Address (ZERO) 00h, Address (NZERO)
DS41303G-page 355
PIC18F2XK20/4XK20
XORWF
Syntax: Operands:
Exclusive OR W with f
XORWF 0 d a f 255 [0,1] [0,1] dest f {,d {,a}}
(W) .XOR. (f) N, Z 0001
10da
ffff
ffff
Exclusive OR the contents of W with register f. If d is 0, the result is stored in W. If d is 1, the result is stored back in the register f (default). If a is 0, the Access Bank is selected. If a is 1, the BSR is used to select the GPR bank. If a is 0 and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.3 Byte-Oriented and Bit-Oriented Instructions in Indexed Literal Offset Mode for details. 1 1
Q2 Read register f XORWF AFh B5h 1Ah B5h
Example:
Before Instruction REG = W = After Instruction REG = W =
DS41303G-page 356
PIC18F2XK20/4XK20
24.2 Extended Instruction Set
In addition to the standard 75 instructions of the PIC18 instruction set, PIC18F2XK20/4XK20 devices also provide an optional extension to the core CPU functionality. The added features include eight additional instructions that augment indirect and indexed addressing operations and the implementation of Indexed Literal Offset Addressing mode for many of the standard PIC18 instructions. The additional features of the extended instruction set are disabled by default. To enable them, users must set the XINST Configuration bit. The instructions in the extended set can all be classified as literal operations, which either manipulate the File Select Registers, or use them for indexed addressing. Two of the instructions, ADDFSR and SUBFSR, each have an additional special instantiation for using FSR2. These versions (ADDULNK and SUBULNK) allow for automatic return after execution. The extended instructions are specifically implemented to optimize re-entrant program code (that is, code that is recursive or that uses a software stack) written in high-level languages, particularly C. Among other things, they allow users working in high-level languages to perform certain operations on data structures more efficiently. These include: dynamic allocation and deallocation of software stack space when entering and leaving subroutines function pointer invocation software Stack Pointer manipulation manipulation of variables located in a software stack A summary of the instructions in the extended instruction set is provided in Table 24-3. Detailed descriptions are provided in Section 24.2.2 Extended Instruction Set. The opcode field descriptions in Table 24-1 apply to both the standard and extended PIC18 instruction sets. Note: The instruction set extension and the Indexed Literal Offset Addressing mode were designed for optimizing applications written in C; the user may likely never use these instructions directly in assembler. The syntax for these commands is provided as a reference for users who may be reviewing code that has been generated by a compiler.
24.2.1
EXTENDED INSTRUCTION SYNTAX
Most of the extended instructions use indexed arguments, using one of the File Select Registers and some offset to specify a source or destination register. When an argument for an instruction serves as part of indexed addressing, it is enclosed in square brackets ([ ]). This is done to indicate that the argument is used as an index or offset. MPASM Assembler will flag an error if it determines that an index or offset value is not bracketed. When the extended instruction set is enabled, brackets are also used to indicate index arguments in byteoriented and bit-oriented instructions. This is in addition to other changes in their syntax. For more details, see Section 24.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands. Note: In the past, square brackets have been used to denote optional arguments in the PIC18 and earlier instruction sets. In this text and going forward, optional arguments are denoted by braces ({ }).
TABLE 24-3:
Mnemonic, Operands ADDFSR ADDULNK CALLW MOVSF MOVSS PUSHL SUBFSR SUBULNK f, k k
EXTENSIONS TO THE PIC18 INSTRUCTION SET

16-Bit Instruction Word Description Add literal to FSR Add literal to FSR2 and return Call subroutine using WREG Move zs (source) to 1st word fd (destination) 2nd word Move zs (source) to 1st word zd (destination) 2nd word Store literal at FSR2, decrement FSR2 Subtract literal from FSR Subtract literal from FSR2 and return Cycles MSb 1 2 2 2 2 1 1 2 1110 1110 0000 1110 1111 1110 1111 1110 1110 1110 1000 1000 0000 1011 ffff 1011 xxxx 1010 1001 1001 ffkk 11kk 0001 0zzz ffff 1zzz xzzz kkkk ffkk 11kk LSb kkkk kkkk 0100 zzzz ffff zzzz zzzz kkkk kkkk kkkk Status Affected None None None None None None None None
zs, fd zs, zd k f, k k
DS41303G-page 357
PIC18F2XK20/4XK20
24.2.2
ADDFSR
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Q2 Read literal k Q3 Process Data Q4 Write to FSR
EXTENDED INSTRUCTION SET

Add Literal to FSR
ADDFSR f, k 0 k 63 f [ 0, 1, 2 ] FSR(f) + k None 1110 1000 ffkk kkkk The 6-bit literal k is added to the contents of the FSR specified by f. 1 1 FSR(f) Status Affected: Encoding: Description:
ADDULNK
Add Literal to FSR2 and Return

ADDULNK k 0 k 63 FSR2, PC 1000 11kk kkkk FSR2 + k (TOS) None 1110 The 6-bit literal k is added to the contents of FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the ADDFSR instruction, where f = 3 (binary 11); it operates only on FSR2. 1 2
Example:
ADDFSR 2, 23h 03FFh 0422h
Words: Cycles: Q Cycle Activity: Q1 Decode No Operation
Before Instruction FSR2 = After Instruction FSR2 =
Q2 Read literal k No Operation
Q3 Process Data No Operation
Q4 Write to FSR No Operation
Example:
ADDULNK 23h 03FFh 0100h 0422h (TOS)
Before Instruction FSR2 = PC = After Instruction FSR2 = PC =
Note:
All PIC18 instructions may take an optional label argument preceding the instruction mnemonic for use in symbolic addressing. If a label is used, the instruction syntax then becomes: {label} instruction argument(s).
DS41303G-page 358
PIC18F2XK20/4XK20
CALLW
Subroutine Call Using WREG

CALLW None TOS, (PC + 2) PCL, (W) (PCLATH) PCH, (PCLATU) PCU None 0000 0000 0001 0100
MOVSF
Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description:
Move Indexed to f
MOVSF [zs], fd 0 0 z s 127 fd 4095 fd
((FSR2) + zs) None 1110 1111
Status Affected: Encoding: Description
1011 ffff
0zzz ffff
zzzzs ffffd
First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded. Then, the contents of PCLATH and PCLATU are latched into PCH and PCU, respectively. The second cycle is executed as a NOP instruction while the new next instruction is fetched. Unlike CALL, there is no option to update W, Status or BSR. 1 2
Q2 Read WREG No operation
Q3 PUSH PC to stack No operation
Q4 No operation No operation Words: Cycles: Q Cycle Activity: Q1 Decode
The contents of the source register are moved to destination register fd. The actual address of the source register is determined by adding the 7-bit literal offset zs in the first word to the value of FSR2. The address of the destination register is specified by the 12-bit literal fd in the second word. Both addresses can be anywhere in the 4096-byte data space (000h to FFFh). The MOVSF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. 2 2 Q2 Q3 Q4 Read source reg Write register f (dest)
Example:
HERE
CALLW Decode
Determine Determine source addr source addr No operation No dummy read No operation
Before Instruction PC = PCLATH = PCLATU = W = After Instruction PC = TOS = PCLATH = PCLATU = W =
address (HERE) 10h 00h 06h 001006h address (HERE + 2) 10h 00h 06h Example:
MOVSF = = = = = =
[05h], REG2 80h 33h 11h 80h 33h 33h
Before Instruction FSR2 Contents of 85h REG2 After Instruction FSR2 Contents of 85h REG2
DS41303G-page 359
PIC18F2XK20/4XK20
MOVSS
Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (dest.) Description
Move Indexed to Indexed

MOVSS [zs], [zd] 0 z s 127 0 z d 127 ((FSR2) + zs) None 1110 1111 1011 xxxx 1zzz xzzz zzzzs zzzzd ((FSR2) + z d)
PUSHL
Store Literal at FSR2, Decrement FSR2

PUSHL k 0 k 255
k (FSR2), FSR2 FSR2 1 None 1111 1010 kkkk kkkk
The contents of the source register are moved to the destination register. The addresses of the source and destination registers are determined by adding the 7-bit literal offsets zs or zd, respectively, to the value of FSR2. Both registers can be located anywhere in the 4096-byte data memory space (000h to FFFh). The MOVSS instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. If the resultant source address points to an indirect addressing register, the value returned will be 00h. If the resultant destination address points to an indirect addressing register, the instruction will execute as a NOP. 2 2
The 8-bit literal k is written to the data memory address specified by FSR2. FSR2 is decremented by 1 after the operation. This instruction allows users to push values onto a software stack. 1 1
Q2 Read k
Q3 Process data
Example:
PUSHL 08h = = 01ECh 00h
Before Instruction FSR2H:FSR2L Memory (01ECh) After Instruction FSR2H:FSR2L Memory (01ECh)
Words: Cycles: Q Cycle Activity: Q1 Decode Decode
= =
01EBh 08h
Q2
Q3
Q4 Read source reg Write to dest reg
Determine Determine source addr source addr Determine dest addr Determine dest addr
Example:
MOVSS [05h], [06h] = = = = = = 80h 33h 11h 80h 33h 33h
Before Instruction FSR2 Contents of 85h Contents of 86h After Instruction FSR2 Contents of 85h Contents of 86h
DS41303G-page 360
PIC18F2XK20/4XK20
SUBFSR
Subtract Literal from FSR

SUBFSR f, k 0 f k 63 FSRf 1001 ffkk kkkk [ 0, 1, 2 ]
SUBULNK
Subtract Literal from FSR2 and Return

SUBULNK k 0 k 63 FSR2 PC 1001 11kk kkkk FSR2 k (TOS)
FSR(f) k None 1110
Status Affected: None Encoding: Description: 1110 The 6-bit literal k is subtracted from the contents of the FSR2. A RETURN is then executed by loading the PC with the TOS. The instruction takes two cycles to execute; a NOP is performed during the second cycle. This may be thought of as a special case of the SUBFSR instruction, where f = 3 (binary 11); it operates only on FSR2. 1 2 Q1 Q2 Read register f No Operation Q3 Process Data No Operation Q4 Write to destination No Operation
The 6-bit literal k is subtracted from the contents of the FSR specified by f. 1 1
Q2 Read register f
Q3 Process Data
Q4 Write to destination Words: Cycles:
Example: Before Instruction FSR2 = After Instruction FSR2 =
SUBFSR 2, 23h 03FFh 03DCh
Q Cycle Activity: Decode No Operation
Example: Before Instruction FSR2 = PC = After Instruction FSR2 = PC =
SUBULNK 23h 03FFh 0100h 03DCh (TOS)
DS41303G-page 361
PIC18F2XK20/4XK20
24.2.3 BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE
Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely.
24.2.3.1
Extended Instruction Syntax with Standard PIC18 Commands
Note:
In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 5.5.1 Indexed Addressing with Literal Offset). This has a significant impact on the way that many commands of the standard PIC18 instruction set are interpreted. When the extended set is disabled, addresses embedded in opcodes are treated as literal memory locations: either as a location in the Access Bank (a = 0), or in a GPR bank designated by the BSR (a = 1). When the extended instruction set is enabled and a = 0, however, a file register argument of 5Fh or less is interpreted as an offset from the pointer value in FSR2 and not as a literal address. For practical purposes, this means that all instructions that use the Access RAM bit as an argument that is, all byte-oriented and bitoriented instructions, or almost half of the core PIC18 instructions may behave differently when the extended instruction set is enabled. When the content of FSR2 is 00h, the boundaries of the Access RAM are essentially remapped to their original values. This may be useful in creating backward compatible code. If this technique is used, it may be necessary to save the value of FSR2 and restore it when moving back and forth between C and assembly routines in order to preserve the Stack Pointer. Users must also keep in mind the syntax requirements of the extended instruction set (see Section 24.2.3.1 Extended Instruction Syntax with Standard PIC18 Commands). Although the Indexed Literal Offset Addressing mode can be very useful for dynamic stack and pointer manipulation, it can also be very annoying if a simple arithmetic operation is carried out on the wrong register. Users who are accustomed to the PIC18 programming must keep in mind that, when the extended instruction set is enabled, register addresses of 5Fh or less are used for Indexed Literal Offset Addressing. Representative examples of typical byte-oriented and bit-oriented instructions in the Indexed Literal Offset Addressing mode are provided on the following page to show how execution is affected. The operand conditions shown in the examples are applicable to all instructions of these types.
When the extended instruction set is enabled, the file register argument, f, in the standard byte-oriented and bit-oriented commands is replaced with the literal offset value, k. As already noted, this occurs only when f is less than or equal to 5Fh. When an offset value is used, it must be indicated by square brackets ([ ]). As with the extended instructions, the use of brackets indicates to the compiler that the value is to be interpreted as an index or an offset. Omitting the brackets, or using a value greater than 5Fh within brackets, will generate an error in the MPASM Assembler. If the index argument is properly bracketed for Indexed Literal Offset Addressing, the Access RAM argument is never specified; it will automatically be assumed to be 0. This is in contrast to standard operation (extended instruction set disabled) when a is set on the basis of the target address. Declaring the Access RAM bit in this mode will also generate an error in the MPASM Assembler. The destination argument, d, functions as before. In the latest versions of the MPASM assembler, language support for the extended instruction set must be explicitly invoked. This is done with either the command line option, /y, or the PE directive in the source listing.
24.2.4
CONSIDERATIONS WHEN ENABLING THE EXTENDED INSTRUCTION SET
It is important to note that the extensions to the instruction set may not be beneficial to all users. In particular, users who are not writing code that uses a software stack may not benefit from using the extensions to the instruction set. Additionally, the Indexed Literal Offset Addressing mode may create issues with legacy applications written to the PIC18 assembler. This is because instructions in the legacy code may attempt to address registers in the Access Bank below 5Fh. Since these addresses are interpreted as literal offsets to FSR2 when the instruction set extension is enabled, the application may read or write to the wrong data addresses. When porting an application to the PIC18F2XK20/ 4XK20, it is very important to consider the type of code. A large, re-entrant application that is written in C and would benefit from efficient compilation will do well when using the instruction set extensions. Legacy applications that heavily use the Access Bank will most likely not benefit from using the extended instruction set.
DS41303G-page 362
PIC18F2XK20/4XK20
ADDWF
ADD W to Indexed (Indexed Literal Offset mode)

ADDWF 0 d k 95 [0,1] dest [k] {,d}
BSF
Bit Set Indexed (Indexed Literal Offset mode)

BSF [k], b 0 0 1 f 95 b 7 ((FSR2) + k)
(W) + ((FSR2) + k) N, OV, C, DC, Z 0010 01d0
None 1000 bbb0 kkkk kkkk
kkkk
kkkk
Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode
The contents of W are added to the contents of the register indicated by FSR2, offset by the value k. If d is 0, the result is stored in W. If d is 1, the result is stored back in register f (default). 1 1
Bit b of the register indicated by FSR2, offset by the value k, is set. 1 1 Q2 Read register f BSF = = = Q3 Process Data Q4 Write to destination
Q2 Read k
Q3 Process Data [OFST] , 0 = = = = = = 17h 2Ch 0A00h 20h 37h 20h
Example:
[FLAG_OFST], 7 0Ah 0A00h 55h
Example: W OFST FSR2 Contents of 0A2Ch After Instruction W Contents of 0A2Ch
ADDWF
Before Instruction
Before Instruction FLAG_OFST FSR2 Contents of 0A0Ah After Instruction Contents of 0A0Ah
D5h
SETF
Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode
Set Indexed (Indexed Literal Offset mode)

SETF [k] 0 k 95 ((FSR2) + k)
FFh None
0110
1000
kkkk
kkkk
The contents of the register indicated by FSR2, offset by k, are set to FFh. 1 1 Q2 Read k Q3 Process Data [OFST] 2Ch 0A00h 00h Q4 Write register
Example:
SETF = = =
Before Instruction OFST FSR2 Contents of 0A2Ch After Instruction Contents of 0A2Ch
FFh
DS41303G-page 363

TABLE 5-1: Special Function Register Map For Pic18F2Xk20/4Xk20 Devices

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TABLE 5-1: Special Function Register Map For Pic18F2Xk20/4Xk20 Devices

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PIC18F2XK20/4XK20

SPECIAL FUNCTION REGISTER MAP FOR PIC18F2XK20/4XK20 DEVICES

(2) (2) (2) LATE(3) LATD(3) LATC LATB LATA (2)

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PIC18FXXXX INSTRUCTION SET

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PIC18FXXXX INSTRUCTION SET (CONTINUED)

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PIC18FXXXX INSTRUCTION SET (CONTINUED)

PROGRAM MEMORY OPERATIONS

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STANDARD INSTRUCTION SET

N, OV, C, DC, Z 0000 1111

N, OV, C, DC, Z 0010 01da ffff ffff

Words: Cycles: Q Cycle Activity: Q1 Decode

Before Instruction W = 10h After Instruction W = 25h Words: Cycles:

Example: W = REG = After Instruction W REG = =

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ADD W and CARRY bit to f

AND literal with W

(W) .AND. k N, Z 0000

Operation: Status Affected: Encoding: Description:

(W) + (f) + (C) N,OV, C, DC, Z 0010 00da

Description: Words: Cycles: Q Cycle Activity: Q1 Decode

Example: W = After Instruction W =

Words: Cycles: Q Cycle Activity: Q1 Decode

Q2 Read register f ADDWFC 1 02h 4Dh 0 02h 50h

Q3 Process Data REG, 0, 1

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if CARRY bit is 1 (PC) + 2 + 2n PC None 1110 0010 nnnn nnnn

Operation: Status Affected: Encoding: Description:

(W) .AND. (f) N, Z 0001

Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation

Q2 Read literal n No operation Q2 Read literal n HERE = = = = =

Q3 Process Data No operation Q3 Process Data BC 5

Q4 Write to PC No operation Q4 No operation

Words: Cycles: Q Cycle Activity: Q1 Decode

Q2 Read register f ANDWF 17h C2h 02h C2h

Q3 Process Data REG, 0, 0

Example: W = REG = After Instruction W REG = =

Before Instruction PC After Instruction If CARRY PC If CARRY PC

address (HERE) 1; address (HERE + 12) 0; address (HERE + 2)

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f 255 b 7 [0,1] f<b>

if NEGATIVE bit is 1 (PC) + 2 + 2n PC None 1110 0110 nnnn nnnn

Operation: Status Affected: Encoding: Description:

Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode

Words: Cycles: Q Cycle Activity: Q1 Decode

Q2 Read literal n No operation Q2 Read literal n HERE = = = = =

Q3 Process Data No operation Q3 Process Data BN Jump

Q4 Write to PC No operation Q4 No operation

Q2 Read register f BCF

Q3 Process Data FLAG_REG, C7h 47h

No operation If No Jump: Q1 Decode

Before Instruction FLAG_REG = After Instruction FLAG_REG =

Before Instruction PC After Instruction If NEGATIVE PC If NEGATIVE PC

address (HERE) 1; address (Jump) 0; address (HERE + 2)

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Branch if Not Carry

Branch if Not Negative

if CARRY bit is 0 (PC) + 2 + 2n PC None 1110 0011 nnnn nnnn

if NEGATIVE bit is 0 (PC) + 2 + 2n PC None 1110 0111 nnnn nnnn

Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation If No Jump: Q1 Decode