Program I: To Simulate and Gate: Digital Circuits and Systems - Ii Lab

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DIGITAL CIRCUITS AND SYSTEMS II LAB
PROGRAM I: TO SIMULATE AND GATE

library ieee; use ieee.std_logic_1164.all; entity andgate is port(a,b : in std_logic; y : out std_logic); end andgate; architecture andgate_arc of andgate is begin y<=a AND b; end andgate_arc;
TEST FILE:
Library ieee; use ieee.std_logic_1164.all; entity Test is end Test; architecture Test_arc of Test is component andgate port(a,b : in std_logic; y : out std_logic); end component; signal s1,s2,s3 : std_logic; begin A1:andgate port map(s1,s2,s3); process begin s1<='0'; s2<='0';
wait for 100ns; s1<='0'; s2<='1'; wait for 100ns; s1<='1'; s2<='0'; wait for 100ns; s1<='1'; s2<='1'; wait for 100ns; end process; end Test_arc;
OUTPUT:
PROGRAM II: TO SIMULATE OR GATE

library ieee; use ieee.std_logic_1164.all; entity orgate is port(a,b : in std_logic; y : out std_logic); end orgate; architecture orgate_arc of orgate is begin y<= a OR b; end orgate_arc;
TEST FILE:
Library ieee; use ieee.std_logic_1164.all; entity Test is end Test; architecture Test_arc of Test is component orgate port(a,b : in std_logic; y : out std_logic); end component; signal s1,s2,s3 : std_logic; begin O1:orgate port map(s1,s2,s3); process begin s1<='0'; s2<='0';
wait for 100ns; s1<='0'; s2<='1'; wait for 100ns; s1<='1'; s2<='0'; wait for 100ns; s1<='1'; s2<='1'; wait for 100ns; end process; end Test_arc;
OUTPUT:
PROGRAM III: TO SIMULATE NOT GATE

library ieee; use ieee.std_logic_1164.all; entity notgate is port(a : in std_logic; y : out std_logic); end notgate; architecture notgate_arc of notgate is begin y<= NOT a; end notgate_arc;
TEST FILE:
Library ieee; use ieee.std_logic_1164.all; entity Test is end Test; architecture Test_arc of Test is component notgate port(a : in std_logic; y : out std_logic); end component; signal s1,s2 : std_logic; begin N1:notgate port map(s1,s2); process
begin s1<='0'; wait for 100ns; s1<='1'; wait for 100ns; end process; end Test_arc;
OUTPUT:
PROGRAM IV: TO SIMULATE NAND GATE

library ieee; use ieee.std_logic_1164.all; entity nandgate is port(a,b : in std_logic; y : out std_logic); end nandgate; architecture nandgate_arc of nandgate is begin y<=a NAND b; end nandgate_arc;
TEST FILE:
Library ieee; use ieee.std_logic_1164.all; entity Test is end Test; architecture Test_arc of Test is component nandgate port(a,b : in std_logic; y : out std_logic); end component; signal s1,s2,s3 : std_logic; begin N2:nandgate port map(s1,s2,s3); process
begin s1<='0'; s2<='0'; wait for 100ns; s1<='0'; s2<='1'; wait for 100ns; s1<='1'; s2<='0'; wait for 100ns; s1<='1'; s2<='1'; wait for 100ns; end process; end Test_arc;
OUTPUT:
PROGRAM V: TO SIMULATE NOR GATE

library ieee; use ieee.std_logic_1164.all; entity norgate is port(a,b : in std_logic; y : out std_logic); end norgate; architecture norgate_arc of norgate is begin y<=a NOR b; end norgate_arc;
TEST FILE:
Library ieee; use ieee.std_logic_1164.all; entity Test is end Test; architecture Test_arc of Test is component norgate port(a,b : in std_logic; y : out std_logic); end component; signal s1,s2,s3 : std_logic; begin N3:norgate port map(s1,s2,s3); process
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OUTPUT:
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PROGRAM VI: TO SIMULATE XOR GATE

library ieee; use ieee.std_logic_1164.all; entity xorgate is port(a,b : in std_logic; y : out std_logic); end xorgate; architecture xorgate_arc of xorgate is begin y<=a XOR b; end xorgate_arc;
TEST FILE:
Library ieee; use ieee.std_logic_1164.all; entity Test is end Test; architecture Test_arc of Test is component xorgate port(a,b : in std_logic; y : out std_logic); end component; signal s1,s2,s3 : std_logic; begin X1:xorgate port map(s1,s2,s3); process
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OUTPUT:
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PROGRAM VII: TO SIMULATE XNOR GATE

library ieee; use ieee.std_logic_1164.all; entity xnorgate is port(a,b : in std_logic; y : out std_logic); end xnorgate; architecture xnorgate_arc of xnorgate is begin y<=a XNOR b; end xnorgate_arc;
TEST FILE:
Library ieee; use ieee.std_logic_1164.all; entity Test is end Test; architecture Test_arc of Test is component xnorgate port(a,b : in std_logic; y : out std_logic); end component; signal s1,s2,s3 : std_logic; begin X2:xnorgate port map(s1,s2,s3); process
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OUTPUT:
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PROGRAM VIII: TO SIMULATE HALF ADDER

Library ieee; use ieee.std_logic_1164.all; entity halfadd is port(a,b : in std_logic; s,c : out std_logic); end halfadd; architecture halfadd_arc of halfadd is begin s<= a XOR b; c<= a AND b; end halfadd_arc;
TEST FILE:
Library ieee; use ieee.std_logic_1164.all; entity Test is end Test; architecture Test_arc of Test is component halfadd port(a,b : in std_logic; s,c : out std_logic); end component; signal s1,s2,s3,s4 : std_logic; begin HA1:halfadd port map(s1,s2,s3,s4);
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process begin s1<='0'; s2<='0'; wait for 100ns; s1<='0'; s2<='1'; wait for 100ns; s1<='1'; s2<='0'; wait for 100ns; s1<='1'; s2<='1'; wait for 100ns; end process; end Test_arc;
OUTPUT:
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PROGRAM IX: TO SIMULATE FULL ADDER

Library ieee; use ieee.std_logic_1164.all; entity fulladd is port(a,b,c : in std_logic; s,car : out std_logic); end fulladd; architecture fulladd_arc of fulladd is begin s<= a XOR b XOR c; car<= (a AND b) OR (a AND c) OR (b and c); end fulladd_arc;
TEST FILE:
Library ieee; use ieee.std_logic_1164.all; entity Test is end Test; architecture Test_arc of Test is component fulladd port(a,b,c : in std_logic; s,car : out std_logic); end component; signal s1,s2,s3,s4,s5 : std_logic; begin FA1:fulladd port map(s1,s2,s3,s4,s5);
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process begin s1<='0'; s2<='0'; s3<='0'; wait for 100ns; s1<='0'; s2<='0'; s3<='1'; wait for 100ns; s1<='0'; s2<='1'; s3<='0'; wait for 100ns; s1<='0'; s2<='1'; s3<='1'; wait for 100ns; s1<='1'; s2<='0'; s3<='0'; wait for 100ns; s1<='1'; s2<='0'; s3<='1'; wait for 100ns; s1<='1'; s2<='1'; s3<='0'; wait for 100ns; s1<='1'; s2<='1'; s3<='1'; wait for 100ns; end process; end Test_arc;
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OUTPUT:
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PROGRAM X: TO SIMULATE HALF SUBTRACTOR
Library ieee; use ieee.Std_logic_1164.all;
entity HS_2 is Port(a,b:in std_logic; dif,bor:out std_logic); end HS_2; architecture HS_2_A of HS_2 is begin dif<=a XOR b; bor<=(NOT a) AND b; end HS_2_A;
TEST FILE:
Library ieee; use ieee.Std_logic_1164.all; entity Test is end Test; architecture Test_A of Test is component HS_2 Port(a,b:in std_logic; dif,bor:out std_logic); end component;
Signal a,b,dif,bor:std_logic;
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begin A1:HS_2 port map(a,b,dif,bor); Process begin a<='0'; b<='0'; wait for 100 ns; a<='0'; b<='1'; wait for 100 ns; a<='1'; b<='0'; wait for 100 ns; a<='1'; b<='1'; wait for 100 ns; end process; end Test_A;
OUTPUT:
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PROGRAM XI: TO SIMULATE FULL SUBTRACTOR

Library ieee; use ieee.Std_logic_1164.all; entity FS_2 is Port(a,b,bin:in std_logic; dif,bout:out std_logic); end FS_2; architecture FS_2_A of FS_2 is begin dif<=((a XOR b)XOR bin); bout<=((NOT a)AND b) OR ((NOT a) AND bin) OR (b AND bin) ; end FS_2_A;
TEST FILE: (USING VECTOR)

Library ieee; use ieee.Std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Test is end Test; architecture Test_A of Test is component FS_2 Port(a,b,bin:in std_logic; dif,bout:out std_logic); end component; Signal a,b,bin,dif,bout:std_logic; begin A1:FS_2 port map(a,b,bin,dif,bout);
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Process Variable t:std_logic_vector(2 downto 0):= "000"; begin a<=t(2); b<=t(1); bin<=t(0); wait for 100 ns; t:=t+ "001"; end process; end Test_A;
OUTPUT:
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PROGRAM XII: TO SIMULATE 4X1 MULTIPLEXER

Library ieee; use ieee.Std_logic_1164.all; entity MUX_4X1 is Port(s1,s0,i3,i2,i1,i0:in std_logic; Y:out std_logic); end MUX_4X1; architecture MUX_4X1_A of MUX_4X1 is begin Y<= ((NOT s0) AND ((NOT s1) AND i0) ) OR((NOT s0) AND (s1 AND i0)) OR ((NOT s0) AND (NOT s1) AND i2) OR (s0 AND (NOT s1) AND i0); end MUX_4X1_A;
TEST FILE(USING VECTOR):

Library ieee; use ieee.Std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Test is end Test; architecture Test_A of Test is component MUX_4X1 Port(s1,s0,i3,i2,i1,i0:in std_logic; Y:out std_logic); end component;
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Signal s1,s0,i3,i2,i1,i0,Y:Std_logic; begin A1: MUX_4X1 port map(s1,s0,i3,i2,i1,i0,Y);
Process variable t:std_logic_vector(5 downto 0):= "000000"; begin s1<=t(5); s0<=t(4); i3<=t(3); i2<=t(2); i1<=t(1); i0<=t(0); wait for 100 ns; t:=t+ "00001"; end process; end Test_A ;
OUTPUT:
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PROGRAM XIII: TO SIMULATE 4X1 MULTIPLEXER USING SELECT SIGNAL ASSIGNMENT STATEMENT
Library ieee; use ieee.Std_logic_1164.all; entity MUX_4X1 is Port(I:in std_logic_vector(3 downto 0); S:in std_logic_vector(1 downto 0); Y:out std_logic); end MUX_4X1; architecture MUX_4X1_A of MUX_4X1 is begin with s select Y<= I(0) when "00" , I(1) when "01" , I(2) when "10" , I(3) when "11"; end MUX_4X1_A;

Library ieee; use ieee.Std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Test is end Test; architecture Test_A of Test is component MUX_4X1 Port(I:in std_logic_vector(3 downto 0); S:in std_logic_vector(1 downto 0);
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Y:out std_logic); end component; Signal S : std_logic_vector(1 downto 0); Signal I : std_logic_vector(3 downto 0); signal Y : Std_logic; begin A1: MUX_4X1 port map(I,S,Y); Process variable t:std_logic_vector(1 downto 0):= "00"; begin S<=t; wait for 100 ns; t:=t+ "01"; end process; I<="0101" ; end Test_A ;
OUTPUT:
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PROGRAM XIV: TO SIMULATE 4X1 MULTIPLEXER USING CONDITIONAL SIGNAL ASSIGNMENT STATEMENT
Library ieee; use ieee.Std_logic_1164.all; entity MUX_4X1 is Port(I:in std_logic_vector(3 downto 0); S:in std_logic_vector(1 downto 0); Y:out std_logic); end MUX_4X1; architecture MUX_4X1_A of MUX_4X1 is begin Y<= I(0) when S="00" else I(1) when S="01" else I(2) when S="10" else I(3); end MUX_4X1_A;

Library ieee; use ieee.Std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Test is end Test; architecture Test_A of Test is component MUX_4X1 Port(I:in std_logic_vector(3 downto 0); S:in std_logic_vector(1 downto 0); Y:out std_logic);
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end component; Signal S : std_logic_vector(1 downto 0); Signal I : std_logic_vector(3 downto 0); signal Y : Std_logic; begin A1: MUX_4X1 port map(I,S,Y);
Process variable t:std_logic_vector(1 downto 0):= "00"; begin S<=t; wait for 100 ns; t:=t+ "01"; end process;
I<="0101" ; end Test_A ;
OUTPUT:
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PROGRAM XV: TO SIMULATE HALF ADDER WITH ENABLE USING BLOCKS

Library ieee; use ieee.Std_logic_1164.all; entity FA_2 is Port(a,b,E:in std_logic; sum,carry:out std_logic); end FA_2; architecture FA_2_A of FA_2 is
begin B1 : Block(E='1') begin sum<=a XOR b ; carry<= a AND b; end block B1; end FA_2_A;
TEST FILE:
Library ieee; use ieee.Std_logic_1164.all; entity Test is end Test; architecture Test_A of Test is component FA_2 Port(a,b,E:in std_logic; sum,carry:out std_logic);
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end component;
Signal a,b,sum,carry,E:Std_logic; begin A1:FA_2 port map(a,b,E,sum,carry);
Process begin E<='0';a<='0'; b<='0'; wait for 100 ns;
E<='0';a<='0'; b<='1'; wait for 100 ns;
E<='0';a<='1'; b<='0'; wait for 100 ns;
E<='0';a<='1'; b<='1'; wait for 100 ns;
E<='1';a<='0'; b<='0'; wait for 100 ns;
E<='1';a<='0'; b<='1'; wait for 100 ns;
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E<='1';a<='1'; b<='0'; wait for 100 ns;
E<='1';a<='1'; b<='1'; wait for 100 ns;
end process; end Test_A;
OUTPUT:
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PROGRAM XVI: PROGRAM TO SIMULATE HALF ADDER USING STRUCTURE MODELLING

Library ieee; use ieee.Std_logic_1164.all; entity AND_2 is Port(a,b:in std_logic; y:out std_logic); end AND_2; architecture AND_2_A of AND_2 is begin y<=a AND b; end AND_2_A; Library ieee; use ieee.Std_logic_1164.all; entity XOR_2 is Port(a,b:in std_logic; y:out std_logic); end XOR_2; architecture XOR_2_A of XOR_2 is begin y<=a XOR b; end XOR_2_A; entity HA_2 is port(a,b: in std_logic; sum,cout:out std_logic); end HA_2; architecture HA_2_A of HA_2 is
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component AND_2 Port(a,b:in std_logic; y:out std_logic); end component; component XOR_2 Port(a,b:in std_logic; y:out std_logic); end component; begin X1:XOR_2 port map(a,b,sum); A1:AND_2 port map(a,b,cout); end HA_2_A;
TEST FILE:
Library ieee; use ieee.Std_logic_1164.all; entity Test is end Test; architecture Test_A of Test is component HA_2 Port(a,b:in std_logic; sum,cout:out std_logic); end component; Signal a,b,sum,cout:Std_logic; begin A1:HA_2 port map(a,b,sum,cout);
Process
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begin a<='0'; b<='0'; wait for 100 ns;
a<='0'; b<='1'; wait for 100 ns;
a<='1'; b<='0'; wait for 100 ns;
a<='1'; b<='1'; wait for 100 ns;
end process; end Test_A;
OUTPUT:
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PROGRAM XVII: TO SIMULATE FULL ADDER USING STRUCTURE MODELLING

Library ieee; use ieee.Std_logic_1164.all; entity AND_2 is Port(a,b:in std_logic; y:out std_logic); end AND_2; architecture AND_2_A of AND_2 is begin y<=a AND b; end AND_2_A; Library ieee; use ieee.Std_logic_1164.all; entity XOR_2 is Port(a,b:in std_logic; y:out std_logic); end XOR_2; architecture XOR_2_A of XOR_2 is begin y<=a XOR b; end XOR_2_A; library ieee; use ieee.std_logic_1164.all; entity OR_3 is port(a,b,c:in std_logic;y:out std_logic); end OR_3;
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architecture OR_3_A of OR_3 is begin y<= (a OR b) OR c; end OR_3_A; entity OR_3 is port(a,b,c:in std_logic;y:out std_logic); end OR_3; architecture OR_3_A of OR_3 is begin y<= (a OR b) OR c; end OR_3_A; entity FA is port(a,b,cin:in std_logic; sum,cout:out std_logic); end FA; architecture FA_A of FA is component AND_2 Port(a,b:in std_logic; y:out std_logic); end component; component XOR_2 Port(a,b:in std_logic; y:out std_logic); end component; component OR_3 port(a,b,c:in std_logic;y:out std_logic); end component; signal t1,t2,t3,t4:std_logic; begin
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X1:XOR_2 port map(a,b,t1); X2:XOR_2 port map(cin,t1,sum); A1:AND_2 port map(a,b,t2); A2:AND_2 port map(b,cin,t3); A3:AND_2 port map(cin,a,t4); O1:OR_3 port map(t2,t3,t4,cout); end FA_A;
TEST FILE:
Library ieee; use ieee.Std_logic_1164.all; entity Test is end Test; architecture Test_A of Test is component FA Port(a,b,cin:in std_logic; sum,cout:out std_logic); end component; Signal a,b,cin,sum,cout:Std_logic; begin A1:FA port map(a,b,cin,sum,cout); Process begin a<='0'; b<='0'; cin<='0'; wait for 100 ns; a<='0'; b<='0'; cin<='1'; wait for 100 ns; a<='0'; b<='1'; cin<='0';
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wait for 100 ns; a<='0'; b<='1'; cin<='1'; wait for 100 ns; a<='1'; b<='0'; cin<='0'; wait for 100 ns; a<='1'; b<='0'; cin<='1'; wait for 100 ns; a<='1'; b<='1'; cin<='0'; wait for 100 ns; a<='1'; b<='1'; cin<='1'; wait for 100 ns; end process; end Test_A;
OUTPUT:
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PROGRAM XVIII: TO SIMULATE 4-BIT PARALLEL ADDER USING STRUCTURE MODELLING

Library ieee; use ieee.Std_logic_1164.all; entity FA is Port(a,b,c:in std_logic; sum,co:out std_logic); end FA; architecture FA_A of FA is begin sum <= (a xor b)xor c; co <= (a and b) or (b and c)or (a and c); end FA_A; Library ieee; use ieee.Std_logic_1164.all; entity FA4 is port(A,B: in std_logic_vector (3 downto 0); S: out std_logic_vector (3 downto 0); cout : out std_logic); end FA4; architecture FA4_A of FA4 is component FA Port(a,b,c:in std_logic; sum,co:out std_logic); end component FA; signal t: std_logic_vector (2 downto 0); begin
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F1 : FA port map (A(0),B(0),'0',S(0),t(0)); F2 : FA port map (A(1),B(1),t(0),S(1),t(1)); F3 : FA port map (A(2),B(2),t(1),S(2),t(2)); F4 : FA port map (A(3),B(3),t(2),S(3),cout); end FA4_A; test Library ieee; use ieee.Std_logic_1164.all; use ieee.std_logic_unsigned.all;
entity Test is end Test;
architecture Test_A of Test is component FA4 Port(A,B:in std_logic_vector(3 downto 0); S:out std_logic_vector(3 downto 0); C:out std_logic); end component;
Signal A,B,S:Std_logic_vector(3 downto 0); signal C:Std_logic; begin A1: FA4 port map(A,B,S,C);
Process variable t:std_logic_vector(7 downto 0):= "00000000";
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begin A<=t(7 downto 4); B<=t(3 downto 0); wait for 100 ns; t:=t+ "0000001";
end process; end Test_A ;
OUTPUT:
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PROGRAM XIX: JK FLIP FLOP WITH SYNCHRONOUS SET AND ASYNCHRONOUS RESET (BEHAVIOURAL MODELLING)
library ieee; use ieee.std_logic_1164.all; entity jk is port(j,k,clk,reset:in bit; Q :inout bit); end jk; architecture jk of jk is begin process(clk,reset) begin if reset='0' then Q<='0'; end if; if clk='0' and clk'event then Q<=(J and (not Q)) or ((not k) and Q); end if; end process; end jk;
TEST BENCH
library ieee; use ieee.std_logic_1164.all; entity test is end test; architecture test of test is component jk is port(j,k,clk,reset:in bit; Q:inout bit); end component; signal j,k,clk,reset,Q:bit; begin u1:jk port map(j,k,clk,reset,Q); process begin clk<='0' ; wait for 100ns; clk<='1' ; wait for 100ns; end process; process
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begin reset<='0'; wait for 120ns; reset<='1' ; wait for 120ns; end process; process begin j<='0';k<='0'; wait for 100ns; j<='0'; k<='1'; wait for 100ns; j<='1';k<='0'; wait for 100ns; j<='1' ; k<='1'; wait for 100ns; end process; end test;
OUTPUT
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PROGRAM XX: SR FLIP FLOP WITH SYNCHRONOUS SET AND ASYNCHRONOUS RESET (BEHAVIOURAL MODELLING)
library ieee; use ieee.std_logic_1164.all; entity SR is port(s,r,clk,reset:in std_logic; Q :inout std_logic); end SR; architecture sr of SR is begin process(clk,reset) begin if reset='0' then Q<='0'; elsif (clk='0' and clk'event) then if (s='1' and r='1') then Q<='-'; elsif (s='0' and r='0') then Q<=Q; elsif (s='0' and r='1') then Q<='0'; elsif (s='1' and r='0') then Q<='1'; end if; end if; end process; end sr;
TEST BENCH
library ieee; use ieee.std_logic_1164.all; entity test is end test; architecture test of test is component SR is port(s,r,clk,reset:in std_logic; Q:inout std_logic); end component;
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signal s,r,clk,reset,Q:std_logic; begin u1:SR port map(s,r,clk,reset,Q); process begin clk<='0' ; wait for 100ns; clk<='1' ; wait for 100ns; end process; process begin reset<='0'; wait for 120ns; reset<='1' ; wait for 120ns; end process; process begin s<='0';s<='0'; wait for 100ns; s<='0'; r<='1'; wait for 100ns; s<='1';r<='0'; wait for 100ns; s<='1' ; r<='1'; wait for 100ns; end process; end test;
OUTPUT
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PROGRAM XXI: T FLIP FLOP WITH SYNCHRONOUS SET AND ASYNCHRONOUS RESET (BEHAVIOURAL MODELLING)
library ieee; use ieee.std_logic_1164.all; entity T is port(t,clk,reset:in std_logic; Q :inout std_logic); end T; architecture tfilp of T is begin process(clk,reset) variable f:std_logic; begin if reset='0' then f:='0'; elsif falling_edge(clk) then if t='0' then f:=Q; elsif t='1' then f:=(not Q); end if; end if; Q<=f; end process; end tfilp;
TEST BENCH
library ieee; use ieee.std_logic_1164.all; entity test is end test; architecture test of test is component T is port(t,clk,reset:in std_logic; Q:inout std_logic); end component; signal t,clk,reset,Q:std_logic; begin
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u1:T port map(t,clk,reset,Q); process begin clk<='0' ; wait for 100ns; clk<='1' ; wait for 100ns; end process; process begin reset<='0'; wait for 120ns; reset<='1' ; wait for 120ns; end process; process begin t<='0'; wait for 80ns; t<='1' ; wait for 80ns; end process; end test;
OUTPUT
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PROGRAM XXII: D FLIP FLOP WITH SYNCHRONOUS SET AND

ASYNCHRONOUS RESET (BEHAVIOURAL MODELLING) PROGRAM
library ieee; use ieee.std_logic_1164.all; entity D is port(d,clk,reset:in std_logic; Q :inout std_logic); end D; architecture dfilp of D is begin process(clk,reset) begin if reset='0' then Q<='0'; elsif (clk='0' and clk'event) then if d='0' then Q<='0'; elsif d='1' then Q<='1'; end if; end if; end process; end dfilp;
TEST BENCH
library ieee; use ieee.std_logic_1164.all; entity test is end test; architecture test of test is component D is port(d,clk,reset:in std_logic; Q:inout std_logic); end component;
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signal d,clk,reset,Q:std_logic; begin u1:D port map(d,clk,reset,Q); process begin clk<='0' ; wait for 100ns; clk<='1' ; wait for 100ns; end process; process begin reset<='0'; wait for 120ns; reset<='1' ; wait for 120ns; end process; process begin d<='0'; wait for 80ns; d<='1' ; wait for 80ns; end process; end test;
OUTPUT
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PROGRAM XXIII: BCD TO DECIMAL DECODER (DATA FLOW

MODELLING)
library ieee; use ieee.std_logic_1164.all; entity bcd is port(b:in std_logic_vector(3 downto 0); y:out integer); end bcd; architecture bcd of bcd is begin with b select y<= 0 when "0000" , 1 when "0001", 2 when "0010", 3 when "0011", 4 when "0100", 5 when "0101", 6 when "0110", 7 when "0111", 8 when "1000", 9 when "1001"; end bcd;
TEST BENCH
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity test is end test; architecture test1 of test is component bcd is port(b:in std_logic_vector(3 downto 0); y:out integer); end component; signal b: std_logic_vector(3 downto 0); signal y: integer; begin
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u1:bcd port map(b,y); process variable t:std_logic_vector(3 downto 0):="0000"; begin t:=t+"0001"; wait for 100ns; if( t="1010") then t:="0000"; end if; b<=t; end process; end test1;
OUTPUT
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PROGRAM XXIV: BCD TO EXCESS 3 CODE CONVERTER (DATA FLOW MODELLING)

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bcd is port(b:in std_logic_vector(3 downto 0); y:out std_logic_vector(3 downto 0)); end bcd; architecture bcd of bcd is begin y <= (b + "0011"); end bcd;;
TEST BENCH
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity test is end test; architecture test1 of test is component bcd is port(b:in std_logic_vector(3 downto 0); y:out std_logic_vector(3 downto 0)); end component; signal b,y: std_logic_vector(3 downto 0); begin u1:bcd port map(b,y); process variable t:std_logic_vector(3 downto 0):="0000"; begin t:=t+"0001"; wait for 100ns; if( t="1010") then t:="0000"; end if;
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b<=t; end process; end test1;
OUTPUT
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PROGRAM XXV: 2 X 4 DECODER (DATA FLOW MODELLING)

library ieee; use ieee.std_logic_1164.all; entity Decoder_2 is port(a,b:in std_logic; I:out std_logic_vector(3 downto 0)); end Decoder_2; architecture D2 of Decoder_2 is signal Abar,Bbar:Std_logic; begin Abar<=Not a; Bbar<=Not b; I(0)<=Abar and Bbar; I(1)<=Abar and b; I(2)<=a and Bbar; I(3)<=a and b; end D2;
TEST BENCH
library ieee; use ieee.std_logic_1164.all; entity test is end test; architecture test_a of test is component Decoder_2 port(a,b:in std_logic; I:out std_logic_vector(3 downto 0));
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end component; signal a,b:std_logic; signal I:std_logic_vector(3 downto 0); begin D1:Decoder_2 port map(a,b,I); Process begin a<='0';b<='0'; wait for 100ns;
a<='0';b<='1'; wait for 100ns; a<='1';b<='0'; wait for 100ns; a<='1';b<='1'; wait for 100ns; end process; end test_a;
OUTPUT
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PROGRAM XXVI: 2 X 4 DECODER (BEHAVIOURAL MODELLING)

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity decoder is port(b:in std_logic_vector(1 downto 0); y:out std_logic_vector(3 downto 0)); end decoder; architecture decoder of decoder is begin process(b) begin if b="00" then y<="0001"; elsif b="01" then y<="0010" ; elsif b="10" then y<="0100" ; elsif b="11" then y<="1000"; end if; end process; end decoder;
TEST BENCH
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity test is end test; architecture test1 of test is component decoder is port(b:in std_logic_vector(1 downto 0); y:out std_logic_vector(3 downto 0)); end component; signal b: std_logic_vector(1 downto 0);
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signal y:std_logic_vector(3 downto 0); begin u1:decoder port map(b,y); process variable t:std_logic_vector(1 downto 0):="00"; begin t:=t+"01"; wait for 100ns; if( t > "11") then t:="00"; end if; b<=t; end process; end test1;
OUTPUT
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PROGRAM XXVII: GRAY TO BINARY CODE CONVERTER (DATA FLOW MODELLING)

library ieee; use ieee.std_logic_1164.all; entity graytobin is port(g:in std_logic_vector(3 downto 0); b:out std_logic_vector(3 downto 0)); end graytobin; architecture graytobin_a of graytobin is begin b(3)<=g(3); b(2)<=g(3) xor g(2); b(1)<=g(1) xor g(3) xor g(2); b(0)<=g(0) xor g(1) xor g(3) xor g(2); end graytobin_a;
TEST BENCH
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity test is end test; architecture test_a of test is component graytobin port(g: in std_logic_vector(3 downto 0); b: out std_logic_vector(3 downto 0)); end component;
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signal b,g:std_logic_vector(3 downto 0); begin gb1:graytobin port map(g,b); process variable t: std_logic_vector(3 downto 0):="0000"; begin for i in 0 to 15 loop g(0)<=t(0); g(1)<=t(1); g(2)<=t(2); g(3)<=t(3); wait for 100ns; t:=t+"0001"; end loop; end process; end test_a;
OUTPUT
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PROGRAM XXVIII: 2 BIT COMPARATOR (DATA FLOW MODELLING)

library ieee; use ieee.std_logic_1164.all; entity comp is port(a,b:in std_logic_vector(1 downto 0); y:out integer); end comp; architecture comp of comp is begin y<=0 when a=b else 1 when a>b else 2 when a<b; end comp;
TEST BENCH
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity test is end test; architecture test1 of test is component comp is port(a,b:in std_logic_vector(1 downto 0); y:out integer); end component; signal a,b: std_logic_vector(1 downto 0); signal y:integer; begin u1:comp port map(a,b,y); process variable t:std_logic_vector(3 downto 0):="0000"; begin t:=t+"0001"; wait for 100ns; a<=t(3 downto 2); b<=t(1 downto 0); if( t="1111") then
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t:="0000"; end if; end process; end test1;
OUTPUT
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PROGRAM XXIX: 2 BIT MULTIPLIER (DATA FLOW MODELLING)

library ieee; use ieee.std_logic_1164.all; entity twobitmul is port(A:in std_logic_vector(1 downto 0); B:in std_logic_vector(1 downto 0); y:out std_logic_vector(3 downto 0)); end twobitmul; architecture twobitmul_A of twobitmul is begin y(3)<=A(1) and B(1) and A(0) and B(0); y(2)<=(A(1) and A(0)) and (not B(1) or not B(0)); y(1)<=(A(1) and not A(0) and B(0)) or (A(1) and not B(1) and B(0))or (A(0) and not A(1) and B(1)) or (A(0) and not B(0) and B(1)); y(0)<=B(1) and B(0); end twobitmul_A;
TEST BENCH
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Test is end Test; architecture Test_A of Test is component twobitmul is port(A:in std_logic_vector(1 downto 0); B:in std_logic_vector(1 downto 0); y: out std_logic_vector(3 downto 0));
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end component; signal A:std_logic_vector(1 downto 0); signal B:std_logic_vector(1 downto 0); signal y:std_logic_vector(3 downto 0); begin t1:twobitmul port map(A,B,y); process variable t:std_logic_vector(3 downto 0):="0000"; begin for i in 0 to 15 loop A(1)<=t(3); B(1)<=t(2); A(0)<=t(1); B(0)<=t(0); t:=t+"0001"; wait for 100ns; end loop; end process; end Test_A;
OUTPUT
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PROGRAM XXX : SHIFT REGISTER (BEHAVIOURAL MODELLING)

library ieee; use ieee.std_logic_1164.all; entity shift is port(si,clk,reset:in std_logic; Q:out std_logic_vector(3 downto 0)); end shift; architecture sh of shift is begin process(clk,reset) variable x:std_logic_vector(3 downto 0):="1111"; begin if falling_edge(clk) then if reset='0' then x:="1111"; else x:=si & x(3 downto 1); end if; end if; Q<=x; end process; end sh;
TEST BENCH
library ieee; use ieee.std_logic_1164.all; entity test is end test; architecture test of test is component shift is port(si,clk,reset:in std_logic; Q :out std_logic_vector(3 downto 0)); end component; signal si,clk,reset:std_logic; signal Q:std_logic_vector(3 downto 0); begin u1:shift port map(si,clk,reset,Q); process begin
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si<='0';wait for 5ns; si<='0';wait for 5ns; end process; process begin clk<='0';wait for 20ns; clk<='1';wait for 20ns; end process; process begin reset<='0';wait for 150ns; reset<='1';wait for 150ns; end process; end test;
OUTPUT
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PROGRAM XXXI: 3 BIT COUNTER (BEHAVIOURAL MODELLING)

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity counter is port(clk,reset:in std_logic; Q:out std_logic_vector(2 downto 0)); end counter; architecture counter of counter is begin process(clk,reset) variable t:std_logic_vector(2 downto 0):="000"; begin if falling_edge(clk) then if reset='0' then t:="000"; else t:= t + "001"; end if; end if; Q<=t; end process; end counter;
TEST BENCH
library ieee; use ieee.std_logic_1164.all; entity test is end test; architecture test of test is component counter is port(clk,reset:in std_logic; Q:out std_logic_vector(2 downto 0)); end component; signal Q:std_logic_vector(2 downto 0); signal clk,reset:std_logic; begin u1:counter port map(clk,reset,Q);
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process begin clk<='0' ;wait for 20ns; clk<='1' ;wait for 20ns; end process; process begin reset<='0'; wait for 280ns; reset<='1' ;wait for 280ns; end process; end test;
OUTPUT
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Program XXXII: Binary to Gray code convertor

library ieee; use ieee.std_logic_1164.all; entity BinTGray is port(b : in std_logic_vector(3 downto 0); g : out std_logic_vector(3 downto 0)); end BinTGray;
architecture BinTGray_A of BinTGray is begin g(0)<=b(0) xor b(1); g(1)<=b(1) xor b(2); g(2)<=b(2) xor b(3); g(3)<=b(3); end BinTGray_A;
TestBench:
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Test is end Test; architecture Test_A of Test is component BinTGray port(b:in std_logic_vector(3 downto 0); g:out std_logic_vector(3 downto 0)); end component;
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signal b,g:std_logic_vector(3 downto 0); begin BG1:BinTGray port map(b,g); process variable t:std_logic_vector(3 downto 0):="0000"; begin for i in 0 to 15 loop b(0)<=t(0); b(1)<=t(1); b(2)<=t(2); b(3)<=t(3); wait for 100ns; t:=t+"0001"; end loop; end process; end Test_A;
Output:
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Program XXXIII: BCD to seven segment decoder

library ieee; use ieee.std_logic_1164.all; entity BCDTDecimal is port(b:in std_logic_vector(3 downto 0); output:out std_logic_vector(6 downto 0)); end BCDTDecimal; architecture BCDTDecimal_A of BCDTDecimal is begin with b select output <="1111110" when "0000", "0110000" when "0001", "1101101" when "0010", "1111001" when "0011", "0110011" when "0100", "1011011" when "0101", "1011111" when "0110", "1110000" when "0111", "1111111" when "1000", "1111011" when "1001"; end BCDTDecimal_A;
Testbench:
library ieee; use ieee.std_logic_1164.all;
entity BCDTDecimal is port(b:in std_logic_vector(3 downto 0);
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output:out std_logic_vector(6 downto 0)); end BCDTDecimal;
architecture BCDTDecimal_A of BCDTDecimal is begin with b select output<="1111110" when "0000", "0110000" when "0001", "1101101" when "0010", "1111001" when "0011", "0110011" when "0100", "1011011" when "0101", "1011111" when "0110", "1110000" when "0111", "1111111" when "1000", "1111011" when "1001"; end BCDTDecimal_A;
Output:

Program I: To Simulate and Gate: Digital Circuits and Systems - Ii Lab

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DIGITAL CIRCUITS AND SYSTEMS II LAB