Reg. No.

Question Paper Code : 11280

B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2011 Third Semester

Electronics and Communication Engineering EC 2203 DIGITAL ELECTRONICS (Regulation 2008)

(Common to PTEC 2203 Digital Electronics for B.E. (Part-Time) Electronics and Communication Engineering Third Semester Regulation 2009) Time : Three hours Answer ALL questions PART A (10 2 = 20 marks) 1. 2. 3. State DeMorgans theorem. What is a totem output? Maximum : 100 marks

Write the logic expressions for the difference and borrow of a half subtractor.

4. 5. 6. 7. 8. 9. 10.

Design a single bit magnitude comparator to compare two words A and B. Write the characteristic equation of a JK flip flop. State the differences between Mealy and Moore State machines. What is the difference between PAL and PLA? Implement the exclusive-or function using ROM. What are the basic building blocks of a Algorithmic state machine chart? What are the two types of Asynchronous sequential circuits? PART B (5 16 = 80 marks)

11.

31
(a) (i) (ii)

Express the Boolean function F = A + B C in a sum of minterms. (6) Simplify the Boolean function using K-map
F (w , x , y , z ) = (0 , 1, 2 , 4 , 5 , 6 , 8 , 9 , 12 , 13 , 14 )

31

31 5

(10)

Or (b) (i) Simplify the following Quine-McCluskey method. Boolean function by using a (8)

F ( A , B , C , D ) = m (0 , 2 , 3 , 6 , 7 , 8 , 10 , 12 , 13 )

(ii)

Draw the schematic and explain the operation of a CMOS inverter. Also explain its characteristics. (8)

(ii)

Explain the operation of a BCD Adder. Or

(b)

(i) (ii)

Draw the logic diagram of a 2-bit by 2-bit binary multiplier and explain its operation. (8) Implement the following function using suitable multiplexer
F ( A , B , C , D ) = (1, 3 , 4 , 11 , 12 , 13 , 14 , 15 )

13.

(a)

(i) (ii)

Convert D flip flop to T flip flop. Design a serial binary adder.

(b)

(i) (ii)

Explain the operation of a BCD ripple counter with JK flip flops.(8)

14.

31

(a)

(i)

Design a combinational circuit using a ROM. The circuit accepts a 3-bit number and generates an output binary number equal to the square of the input number. Briefly explain the EPROM and EEPROM technology. Or (6)

31

Design a clocked sequential machine using T flip-flops for the following state diagram. (use straight binary assignment). (8)

Or

31 5

12.

(a)

(i)

Design a full Adder using two half adders and an OR gate.

(6)

(10)

(8)

(6) (10)

(10)

(ii)

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(b)

(i)

Implement the following functions using 3 input, 4 product term and 2 output PLA
F1 = A B + AC + A B C
F 2 = ( AC + BC )

(8)

(ii) 15. (a) (i)

With logic diagram, explain the basic macrocell.

Draw the ASM chart for the following state diagram.

(ii)

Design the following synchronous sequential circuit using D flip flop and logic gates. (8)

(b)

What is an Hazard? What are the types of hazards? Check whether the following circuit contains an hazard or not
x3 Y = x1 x 2 + x 2

31

If the hazard is present, demonstrate its removal.

31
Or 3

5
(16)

31 5

(8) (8)

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