Homework 4

Q1. Equation 5.3 was derived under the assumption that the transistor are velocity Saturated. Show that when PMOS and NMOS are long-channel devices, or when the supply voltage is low, velocity saturation does not occur and under these circumstances equation 5.6 holds for VM. Derive this equation.

Q2. The layout of a static CMOS inverter is given in Figure1(b), (= 0.125m). You can infer the

sizes of NMOS and PMOS transistors. Looking at the figure it is inferred that the sizes are (NMOS) wn=1.0m, ln=0.25m, (PMOS)wp=0.5m, and lp=0.25 m. a. Derive its parameters (VOH, VOL, and VM), numerically. Use piece-wise linear approximation to derive the value of VIH, and VIL and estimate noise margin. Hint: Before you drive the value of VM, infer the device operating conditions from the simulated VTC given below.(VOH=2.5V, VOL=0V, VM=0.886V, g= -33.45, VIH=0.912V, VIL=0.8V) b. Figure1(a) shows the simulated VTC, infer the value of VIH, and VIL VM and noise margins and compare the device parameters derived in part a. You will notice small deviation from the derived result. Explain the causes of error. c. Is the VTC affected when the output of the gates is connected to the inputs of 4 similar gates? d. What can you do to decrease or increase the value of VM.? Repeat part (a) for wp=3m while keeping wn same. How will the noise margins be effected by these changes?

(a). Simulated VTC

(b). CMOS inverter layout Figure 1.

Q 3. Figure 2 shows a piecewise linear approximation for the VTC. The transistor region is approximated by a straight line with a slope equal to the inverter gain at VM. The intersection of this line with the VOH and VOL lines defines VIH and VIL. a) Use the following data to determine sizing ratio r of NMOS and PMOS transistors for a symmetrical VTC, that will result in equal Noise margins.(Note do not use the approximation used in equation 5.4.) r=1.4

b) Section 5.3.2 of the text uses this piecewise linear approximation to drive simplified expression for NMH and NML in terms of inverter gain. The derivation of gain is based on the assumption that both the NMOS and PMOS devices are velocity saturated at VM. For what range of r is this assumption valid? What is the corresponding range of VM? (1.06<VM<1.1) c) Derive expressions for the inverter gain at VM for the cases when the sizing ratio is just above and just below the limits of the range where both devices are velocity saturated. What are the operating regions of the NMOS and the PMOS for each case?

Figure 2. Q 4. Figure 3 shows an NMOS inverter with resistive load. a. Qualitatively discuss why this circuit behaves as an inverter. b. You are given that IDD=32.717A when Vin=2.5V, What is the value resistance offered by the transistor at this voltage. Find VOH and VOL and also calculate VM, VIH and VIL. (VOH=2.5, VOL=46.2mV, Rn=1.4K, VM=0.793V, g= -9.4V, VIL=0.61V, VIH=0.8776V, NMH=1.63, NML=0.563) c. Now assume that you are not given the value of current through NMOS transistor when Vin=2.5V. Make reasonable assumption to calculate the value of VOL. (Note the error should be small) d. Find NML and NMH, and plot the VTC (NMH=1.63, NML=0.563)

e. Compute the average power dissipation for: (i) Vin= 0 V (P=0V) and (ii) Vin= 2.5 V (P=81.95 micro watt) f. Qualitatively discuss what will happen to the value of VM if the value of the resistance RL is increased or decreased.

Figure 3 Q5. For the inverter of Figure 3 and an output load of 3 pF: a. Calculate tplh, tphl, and tp. (tplh=155.25ns, tphl=9.1ns, tp=82.175ns) b. Are the rising and falling delays equal? Why or why not? c. Compute the static and dynamic power dissipation assuming the gate is clocked as fast as possible (static: 0, 82 microwatt; Dynamic: 0.111mW) Q6. The next figure shows two implementations of MOS inverters. The first inverter uses only NMOS transistors. Calculate VOH, VOL, VM for each case.

Figure 4

(For case a: VOH=1.764V, VOL=0.263V, VM=1.27V; for case b: VM=1.09V, VOH=2.5, VOL=0V) Q7. Consider the following NMOS inverter. Assume that the bulk terminals of all NMOS device are connected to GND. Assume that the input IN has a 0V to 2.5V swing.

Figure 5 a. Set up the equation(s) to compute the voltage on node x. Assume =0.5. (Vx=1.7) b. What are the modes of operation of device M2? Assume =0. c. What is the value on the output node OUT for the case when IN =0V?Assume =0. Q8. In the class we learnt to infer voltage transfer characteristics graphically. The circuit below features a PMOS transistor that is coupled with a non-linear load device represented by a shaded box. Accompanying the figure is the I-V characteristic for this non-linear load device. The I-V curves for PMOS is also included. a. Verify if the following relation hold true for this system. Answer in true and false. If false then give the correct mathematical description of this system. VDD= -VDS+Vshaded-Box VOUT=VDD+VDS VIN=VDD+VGS b. From figure c infer the VTC for this circuit and draw and label it. Determine (or estimate, if necessary, from your VTC) the following parameters: VOH, VOL, VM. Also estimate from your figure the approximate values of VIL, and VIH. c. If you are given that the value of threshold voltage for PMOS is Vth=-0.64, then determine the region of operation for A, B C, D, E points. Also give the reason for the choice you make in your answer. Vth= -0.64 seems like an optimistic value. You can by observing figure c give a rough estimate of Vth. I believe the correct value of Vth is close to -1.05. Can you guess how could I have possibly arrived at this conclusion (hint: observe point A and D for a better guess)? d. This circuit can be used as an alternative to a traditional CMOS inverter (where you have an NMOS in place of the given non-linear device). From the concepts discussed thus far in lecture and from the result of your VTC what are the disadvantages of this method? In particular you are required to compare this inverter with traditional CMOS inverter and describe the disadvantages well have with this transistor in terms of rail to rail swing, power consumption, symmetry of VTC and its effect on Noise margins. Give reasons to your answer.

Figure 6.a. I-Vshaded-box characteristic for non-linear load device

Q9. Sizing a chain of inverters. a) In order to drive a large capacitance (CL = 20 pF) from a minimum size gate (with input capacitance Ci = 10fF), you decide to introduce a two-staged buffer as shown in Figure.0.

Assume that the propagation delay of a minimum size inverter is 70 ps. Also assume that the input capacitance of a gate is proportional to its size. Determine the sizing of the two additional buffer stages that will minimize the propagation delay. 1 is the minimum size inverter.

a) If you could add any number of stages to achieve the minimum delay, how many stages would you insert? what will be the propagation delay in this case?

b) Describe the advantages and disadvantages of the methods shown in (a) and (b). Q10. You are given the following data W/L 1.3125/0.2 5 VT0(V) -0.4 VDSAT(V) -1 Req(K) 31

PMOS

30 115

-0.1

NMOS 0.375/0.25

0.43

0.63

0.06

13

Assume CL(H-L)=6pF=CL(L-H) a) Calculate switching threshold (VM) for the inverter. b) Given the normalized resistance as above calculate tpHL, and tpLH

c) Find the optimum Sizing ratio , and symmetrical sizing ratio. d) If you are given NMH=NML=1.2, assuming piece-wise linear approximation of VTC, what is the gain of the inverter. e) (Design problem)Suppose you are receiving a noisy 0 at the input and a good high. Will you increase the NML or decrease it. Assuming that the gain is same as that calculated in part d, Suggest a reasonable value(increase or decrease 15% compared to the above value) of NML, and find the VM in accordance with this new value. Also design the sizing ratio in accordance with this new value

Reading assignment: You are required to do all the relevant example problems given in the book. Work out the details and match your solutions with the answers given in the book. Also be prepared for MCQs which will require you to go through the post sessional 1 topics of chapter 3 and 5, covered in the class. All the best!