ON-CHIP SPECTRUM/VECTOR ANALYZER FOR BUILT-IN

TESTING OF ANALOG INTEGRATED CIRCUITS

A Thesis

by

MARCIA GISELA MENDEZ RIVERA

Submitted to the Office

of Graduate Studies of

Texas A&M University

in partial fulfillment

of the requirements for the degree of

MASTER OF SCIENCE

December 2002

Major Subject. Electrical Engineering

ON-CHIP SPECTRUM/VECTOR ANALYZER FOR BUILT-IN

TESTING OF ANALOG INTEGRATED CIRCUITS

A Thesis
by

MARCIA GISELA MENDEZ RIVERA

Submitted to Texas A&M University in partial fulfillment of the requirement for the degree of

MASTER OF SCIENCE

Approved as t

ty

and content by:

Jose
(Chair

lva-Martinez

of Committee)

anchez-Sinencio ember)

Aydin Karsilayan (Member)

Frede ck Stricter (Member)

Eva Sevick-Muraca
(Member)

anan Sin

(Head

of Department)

December 2002

Major Subject: Electrical Engineering

ABSTRACT

On-Chip Spectrum/Vector

Analyzer for Built-In Testing

of Analog

Integrated Circuits.

(December 2002)
Marcia Gisela Mendez Rivera,

B.E., University of Guanajuato,

Guanajuato, Mexico;

M. S., Instituto Nacional de Astrofisica, Optics y Electronica, Puebla, Mexico

Chair

of Committee: Dr. Jose Silva-Martinez

The number

of functions

that can be integrated on a single chip has increased during the

last years, making the functional testing

digital testing

of circuits a challenging task. Even

and well-defined

though the

has reached certain maturity

techniques

have been

developed, we cannot use the same techniques

for analog and mixed-signal

circuits due

to the different nature of digital and analog circuits. In the case of analog circuits, the
number

of possible

values is unlimited and there is not a specific value that tells us

properly.

if the

circuit is working

The complexity

and sensitivity

of the time

and voltage

nature in analog circuits makes the testing task even more difficult. Even more, the

analog circuits have to be tested under different conditions; e.g. , sweeping frequency and
amplitude.

Due to the fact that there are not specific and efficient techniques for testing

analog circuits, every analog circuit requires a particular design in order to be tested. As

a result of this, the test cost is the dominant issue in many products and the investment
made in this stage is not recovered.

This work deals with some

techniques

of the

fundamental

problems faced in analog testing. New

to characterize and test analog circuits using an external digital tester rather
used is a built-in self-test
that tells us

than an analog tester have been developed. The architecture

circuit. The test is made in an automatic way, obtaining information

if the
that

circuit works or not based on certain error margin. In our case, the parameters

concern us are transfer function (magnitude and phase response) and harmonic distortion
components.

The techniques
capability

proposed to measure the frequency response

of the DUT

rely on the
signal to be

of the circuit to

generate a low distortion and accurate sinusoidal

used as stimuli.
synchronization

The switched-capacitor

based circuit techniques

used ensure

the

between the blocks involved.

The use of the same digital signal for

controlling these blocks assures that the tracking error could be within

0.5'/o if switched-

capacitor techniques are used.

To my beloved family:
My husband Ari, my daughter Aimee,
my parents Luts Alfonso and Lydia and my brother Luis Alfonso

ACKNOWLEDGMENTS

I would like to thank my advisor Dr. Jose Silva-Martinez for his support, guidance, and
patience beyond the advisor-student
invaluable
friendship

relationship

during this research work and for his

during all these years. The advice and time he always shared with

me are a very important part

of my education. I also

would like to thank Dr. Sanchez-

Sinencio for his support during the time I spent in the AMSC group, as well as express
my gratitude to all the members

of my

committee, Dr. Karsilayan,

Dr. Stricter and Dr.

Sevick, for their support and help to complete this work.

I would like to thank in a very special way to the family Silva-Rivas whose support
played a very important role in the culmination

of this

work, especially Mayo, whose

Iriendship and support were primordial

and priceless.

I also want to thank to all of my friends

and colleagues in the

AMSC group that helped

in one way or another during this work. The interaction I had with all
important during my studies here at Texas A&M.

of them

was really

Finally I would like to dedicate this work to the most important persons in my life: my
husband

Ari, my daughter Aimee, my parents Luis Alfonso and Lydia and my brother
to make my dreams came

Luis Alfonso, whose love and support were the foundations

true. This works belongs to all

of you.

vn

TABLE OF CONTENTS
Page

ABSTRACT.
DEDICATION.
ACKNOWLEDGMENTS.

nl

V1

TABLE OF CONTENTS.

V11

LIST OF FIGURES.
LIST OF TABLES.
CHAPTER

1X

X11

INTRODUCTION.

A.

B.

Introduction. Motivation.

C. Basics on Testing . D. Organization.

4 6 7

II

ON-CHIP SPECTRUM AND NETWORK ANALYZER PRINCIPLES.

A.

Introduction.

9
10
15

B. Basic Principles.
C. Proposed Solution. D. Specifications.

19
24 24 24 29 37 39 41

III

BASIC BUILDING BLOCKS.

A.

B.
C. D.

E. F.

Introduction. Sinewave Generator Bandpass Filter Voltage Gain Amplifier (VGA) . . Operational Amplifier (Opamp) . . Analog-to-Digital Converter.

vnt

CHAPTER

Page

IV

SIMULATION AND EXPERIMENTAL RESULTS

..

45

A.

Introduction.

B.

Sinewave Generator . C. Bandpass Filter D. Voltage Gain Amplifier.

45 46 50 55

CONCLUSIONS

REFERENCES.
APPENDIX.

61

64
75

VITA.

LIST OF FIGURES
FIGURE
Test at each stage
Page

of the

manufacturing

process. . .
steps. . .

1.2 1.3

Test economics in the manufacturing

Production cost. Manufacturing
simulations,

cost includes the design, high-level

actual device-level design, layout and fabrication for

production.

1.4 1.5 1.6

2. 1

Digital vs. analog functionality

Testing in circuits. Block diagram.

Parameters to be measured in analog circuits . .

Relationship between time and frequency domains. . .

10

2.2 2.3 2.4

Frequency domain representation

of a filter

bank . .

Block diagram of a superheterodyne

Typical swept-tuned

spechnm analyzer. . .

13 13

spectrum analyzer.

2.5
2.6

Spectrum analyzer measurement

On-chip spectrum/vector
On-chip spectrum/vector

for different values

of 14ir and ST.

14
16
18

analyzer basic block diagram. . analyzer block diagram. . .

2.7 2.8

Center-to-sampling

f'requency relationship.

(a) f, = 8 f, . (b) f, = /6.

22

3.1 3.2 3.3

3.4 3.5

Variable gain amplifier used to generate the sinewave. . .

25 26

Logic control for the sinewave generator.

-Output sequence for the

logic.

Simulated control signals and output

Quality factor effects in the selection

of the of the

sinewave generator. . . . .

27

harmonic distortion

component. (a) High Q (b) Low Q.

30

3.6 3.7

Effect

of the

accuracy

of the

center frequency on fundamental,

second and third harmonic measurements.

31
32

Switched-capacitor

bandpass filter.

FIGURE

Page
bandpass filter.

3.8

Block diagram for the switched-capacitor

.
= '/4 .

33

3.9

Bandpass filter with additional sampling frequency in Cti. (fj'

fi

and

js '= '/~. fj). .

for the filter.

35

3.10 3.11 3.12

3.13

Switcap simulation

36
37 38

Simulated time response for the bandpass filter. .

Variable gain amplifier.

Opamp schematic

40
41
42 44 44
45

3.14 3.15 3.16 3.17 4. 1 4.2

4.3 4.4 4.5

Block diagram of the algorithmic A/D converter. . .

Flow graph for the algorithmic approach.

(a) Schematic

of the

multiplier by two. (b) Phases. . .

Multiplier by two: circuit configuration

for each phase. . .

.

(a) Cadence layout

Simulated output

of the chip. (b) Microphotograph of the sinewave generator . . of the

sinewave generator . .
1

46

Measured output signal

47
48

Sinusoidal signal spectrum at

kHz and +50 mV reference voltage .

Spectral noise density for the output

V,

of the

sinewave generator with

~+100 mV

and 1 kHz center frequency.

..

4.6 4.7 4.8

4.9

Measured transfer function for the bandpass filter. . .

51 51
52

Error in the center frequency for the bandpass filter. . .

Gain for the bandpass filter.
Quality factor for the bandpass filter.

52

4. 10 4. 11 4. 12 4. 13
4. 14
A. 1

Intermodulation

measurement

for the bandpass filter. . .

53

Noise

of the

bandpass filter.

54
56
The input signal amplitude is +100

VGA output for different gains.

Error in the VGA measurements.

mV.
Noise in the VGA.

56 57
bandpass filter.

Switched-capacitor

67

FIGURE

Page
bandpass filter. .

A.2

Block diagram for the switched-capacitor

Opamp schematic

67

B.I

69

LIST OF TABLES
TABLE
Page
Target specifications for the on-chip network/spectrum
analyzer. .

2. 1

23

3.1 3.2 3.3 3.4 3.5 3.6

4. 1 4.2 4.3 4.4

Capacitor values for the sinewave generator. . . Capacitor values for the SC bandpass filter.

29
35 35 38
41

.. ..

New capacitor values for the SC bandpass filter. . .

Final capacitor values for the SC bandpass filter.

Capacitor values for the VGA.

Sizes for the opamp transistors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Simulated and experimental
results for the harmonic components

of
46
50
55

the sinewave generator for V, /=50 mV.

Sinewave generator measurements

summary

..

Bandpass filter measurement

Measurement
summary

summary

57
72

B.1

Sizes for the opamp transistors.

CHAPTER

INTRODUCTION
A. Introduction
The process of making integrated
specifications must be translated

circuits consists

of several steps. First,

the idea and

into a design that is simulated

and optimized until it

works within the specs. Once the design is finished, the layout is made: in this step, postlayout simulations
help to determine

if the

original design corresponds

to the schematic

that has been developed.

When the chip is fabricated, it is tested to verify that the main

specifications
properly,

are within

certain boundaries.

Finally, provided

that the circuit works

it is sent to major production.

Again, testing is necessary to ensure proper

performance of each fabncated circuit.

Testing is present in several steps

of

the production

process. Fig

I.l

shows the ideal

process of placing a product on the market [1,2]. If in any of these steps a failure exist,
optimization

or modifications

of the original design

must be made. Some

of these

failures can occur at the layout level, on the wafer or in packaged parts. There are many

issues that can make the circuit to work improperly:

environmental

bad design or layout, chemical or

agents and even careless handling

can affect the final performance

of the

chip. The distribution

of

the test throughout

the manufacturing

process is more cost

effective because only non-defective components are permitted to move to the next level

of assembly.

This thesis follows the style and format

of the IEEE Journal of Solid-State Circuits.

Wafer
Process
Test

Die
Pastose
Bum-ia

Test

Discard

Board
Substrate
Process
Test
Ininal Assembly

System
Test
Fmal Assembly

Fmal

Test

To Fteld

Diagnosis and Repatr

Diagnosis and Repair

Repair

Fig. 1.1 Test at each stage of the manufacturing

process.

Since testing is encountered

fabrication,

many times in the process

of Integrated

Circuits (IC)

a large amount

of

money

is invested

in this stage and ls usually

not

recovered.

Fig. 1.2 shows the cost associated to each stage of the process of making an

integrated circuit. It can be seen that it takes ten times the effort through each successive
manufactunng

step to detect, locate and repair a faulty component. Therefore, the testing

at early stages helps to reduce the testing cost

of the next

stage.

Cost Per Component

1000

100
10

0. 1
'O

Test
Acttvtty

p
M

Fig. 1.2. Test economics in the manufacturing

steps.

B.

Motivation

Modem integrated circuits are becoming more complex, which does not assure optimal
performance
and the access to internal nodes is difficult due to both the limited number

of pins

available

and buffers required,

built-in

making the testing a challenging

and allow diagnosing and number

task. Several

techniques

that involve

self-testing

failures have been

that can be

developed. However,

the growth

in complexity

of functions

integrated on a single-chip have increased rapidly in the last years, making the testing a

difficult task

[3].Even

tough the majority

of these systems are mainly digital, the analog

section is still an important part on such systems.

Albeit the digital testing has reached certain maturity and well-defined

techniques have

been developed, we can not use the same techniques for analog and mixed-signal circuits
due to the different
information
is binary
nature

of

digital

and analog

circuits.

In digital

circuits, the

and only two possible

values are required;

the main issue is,

however, to test both robustness and speed. In the case

of analog

circuits, the number

of
1.4.

possible values is unlimited and there is not a specific value that tells us

if the

circuit is

working properly, so a boundary must be set; a graphic comparison is shown in Fig.

Testing in analog circuits faces many problems that digital testing has overcome. The
complexity and sensitivity

of the time

and voltage nature in analog circuits makes the

testing task even more difficult. Even more, the analog circuits have to be tested under
different conditions; e.g. , sweeping frequency and amplitude.
There are not specific and

efficient techniques for testing analog circuits: every analog circuit requires a particular
design in order to be tested.

Bad

Good

Digital Function

Good

Bad

Bad
Analog Function

Fig. 1.4. Digital vs. analog functionality.

In the case of mixed-signal

circuits, the digital part should be tested separately from the

analog part. Mixed signal testing is not only made difficult by the long testing times analog components
which must be tested on expensive automated

of
to

test equipment

with

mixed signal capabilities,

but also the access to analog nodes is usually

limited

relatively few inputs and outputs since it is not possible to bnng all the analog inputs and
outputs out to the pins.

There are several factors that have contributed to make the mixed-signal
complex, such as the access to the analog components

testing more

and the close interaction between

both digital and analog parts. Other issues to consider are the reduction

of the

test time

and the area used by the testing circuit. They should not represent a large area overhead

for the whole system. Also, the presence of the testing circuit must affect as less as
possible the measurements
obtained.

Mixed-signal

testing techniques can be divided into two parts: DC

BIST and AC BIST

Under Test

[4]. In the

first one, we are only concerned for the DC behavior

of the Device

(DUT): i.e. operation point. In the AC BIST we try to measure the frequency response of
the system. Traditionally,
the AC characterization

of

a linear system is done on the

frequency frequency

domain:

a sinusoidal

signal is applied
output

to the input

of

the DUT and the

of this signal is swept. The

is converted

to the digital format and

analyzed. It may seem quite simple and straightforward

but this process is expensive and

time consuming. Therefore, the need for a solution to this problem is evident.

C. Basics on Testing
Fig. 1.5 shows the block diagram of how the testing is performed
in analog circuits.

There are two blocks: the device under test (DUT) and the circuit performing
Using the switches, normal operation or testing mode can be chosen. The area

the test.

of the test

circuit should be smaller than the DUT. The goal is to test the DUT in an automatic way
without changing its original configuration.

Input

L
some

DUT

Output

Vector
Analyzer

Fig. 1.5. Testing in circuits. Block diagram. Fig. 1.6 shows, some of the many parameters
frequency response, amplitude, application

that can be measured

in analog circuits:

phase, noise, harmonic distortion, etc. Depending on the

of the DUT,

of these parameters are going to be more

an output. In our case, some

important
all

than

others and the circuit should allow us to test the most critical parameters,
using an input signal and measuring

of these of

of the

parameters

concern are:

Transfer function (Iiequency response).

~ ~

Harmonic distortion.

Noise.

Input

DUT

Output

Vector
Analyzer

Amphtude

BIV

Analysis

Fig. 1.6. Parameters to be measured in analog circuits.

The main goal of this research is to develop new techniques

to integrate

the testing

circuit on the same chip and characterize and test analog circuits using an external digital
tester rather that an analog tester in order to reduce test time and cost [5]. The
architecture to be used is a built-in test circuit. The test should be made in an automatic

way, obtaining information

that tells us

if the

circuit works or not based on certain error

margin. The tester is designed in such a way that allows us to test the most important
parameters,
such as transfer

function

(magnitude

and phase response)

and harmonic

distortion components.

This work deals with some

of the

many features than can be

within the

measured in analog systems, and based on them, decide

if the circuit works

required specifications.

D. Organization
The thesis is organized
as follows:

Chapter

II describes the main principle of the

proposed technique as well as some previous proposals. The third chapter deals with the
design issues

of the

main building

blocks involved in the proposed solution. The next

chapter shows simulation

and experimental

results

of

the designed

blocks and the

complete system. Finally, Chapter V lists the summary and conclusions

of the

thesis.

CHAPTER

II

ON-CHIP SPECTRUM AND NETWORK ANALYZER PRINCIPLES

A. Introduction

Spectrum

and

network analyzers are found in many laboratories for the characterization

of analog

systems.

The network and spectrum analyzers in use today are the result of

over half a century

of

continuous

development.

The best commercially

available

spectrum analyzers today have a dynamic range greater than 100 dB (corresponding

to

10 orders of magnitude in power) and over seven orders of magnitude in frequency [6].
With this equipment,
it is possible to analyze the transfer function and the distortion
components of the circuit under test. The use of the spectrum analyzers for production

testing

is prohibited

due to large

testing

time

and

high

costs. In general,

the

charactenzation

or testing of an analog circuit involves the extraction

of the

gain and

phase frequency response as well as the harmonic distortion.

Usually

such measurements

are performed

in a large tester and take

a considerable

amount of time. Besides, the reconfiguration

needed in the device under test adds extra

parasitic to

the circuit that can affect its response. The

best way to correct this problem is

to embed the testing circuitry on the same chip in order to reduce the interaction

of the

system with external conditions that can alter its functionality

this problem have been reported

. Several approaches to
between the stimuli

[7-11], but

the synchronization

generated and the circuits that perform the measurements

demonstrated
that the use

is not assured. In tlus work it is

and a master clock provides

of switched-capacitor techniques

a self-synchrouized

circuit, making the measurements

reliable and precise.

10

B. Basic Principles
The traditional way
parameters

of observing

an electrical signal is using an oscilloscope, where two

are displayed: amplitude

and time. When using frequency-domain

displays,

we observe the same information,

but using frequency

instead

of

time domain. The

spectrum analyzer takes the analog signal (in the time domain) and converts it into the frequency
domain.

The resulting
components

spectrum

measurement

shows

the energy

of

the
this

different
relationship

frequency

along

the

frequency

axis. Fig. 2. 1 shows

[12]; here,

we can see how a signal with two frequency components

that are

not distinguishable

in the time domain can be easily analyzed in the frequency domain.

Ampbtude

eeet
Ii

Amplitude

Amphtude

Time

prequeuey

Fig. 2. 1 Relationship between time and frequency domains.

Many

signals

that are not distinguishable

are clearly defined

in the time domain in the frequency

(such as noise and

Using spectral

harmonic

components)

domain.

11

analysis,

it is possible to observe all the &equency components

in a single frequency
using an

sweep. For a sinusoidal

signal, amplitude

and frequency

can be measured

oscilloscope, but for more complex signals, this task is not possible because such signals
generally

contain more frequency

analyzers

components

with different

amplitudes

and phases.

This is why spectrum

frequency and amplitude

are useful: they allow measuring

and comparing

the

of individual components of a time-dependant

signal.

There are several ways

of measuring the
the input

spectrum

of a

signal. One technique is the use

of

filter banks

[13], where

the time domain

signal

f(t) is mapped into the frequency

domain f(roj by applying

signal into a bank

of

bandpass

filters, each one

centered at a different frequency, as shown in Fig. 2.2. The outputs

then passed through Root Mean Square (RMS) quantifiers
different frequencies

of these

filters are

to calculate the energy at the

of the

input signal. This approach is effective when the filters cover

all the frequency range

of interest. However,

its ability to resolve fiequency components

on the bandwidth

that are close to each other is highly

dependent

of

each filter.

Therefore, in order to obtain a good resolution,

bandwidth
zion,

each filter must achieve a very small

which leads to a large number n

of filters

given by:

= Spectrum bandwidth

(2. 1)

Frequency

Fig. 2.2. Frequency domain representation

of a filter bank.

12

We can see that even for small frequency ranges, the number of required filters can
become very large, which makes this option not a good candidate for on-chip testing,
where silicon area must be optimized.
generated from the overlapping
non-overlapping
Another

problem

is the aliasing that can be

filters as well as frequencies that are not covered in the

frequencies.

Another approach

of spectrum

analysis makes use

of tunable

filters. This technique uses

a filter centered at a fixed frequency and translates the frequency

of the

incoming signal

to the filter frequency.

For this purpose, a mixer and a local oscillator (LO) are used.
the

The &equency of the LO is chosen in such way that the difference between
frequency of the input signal and the one frequency

of the LO are located

at a specific intermediate

(IF); this signal is filtered by an adjustable bandwidth

bandpass

filter. By

sweeping the frequency

of the LO,

the mixer's output, which include all the information

the filter. This process is knows as heterodyne

of

the input signal, is swept through

pnneiple.

Fig. 2.3 shows a superheterodyne

&equency range

spectrum

analyzer.

The low-pass

filter limits the

of the

input signal to avoid alias components. Then, the filtered signal is

mixed with the signal coming from the LO. The envelope of the IF signal is detected and

is used to control the y-axis [6]. The LO frequency is swept in order to downconvert the
frequency of the input signal; the VCO is con&oiled by a ramp generator, which also

controls the x-axis.

In commercial

single range spectrum

The frequency

analyzers,

the IF is chosen

above its highest &equency of operation.

analyzer is determined by the bandwidth

resolution

of

the spectrum

of the IF filter. Since

narrow IF bandwidths

are

difficult to achieve in the Gigahertz range, most of the spectrum analyzers use several IF
stages to mix down the input signal to an IF where the narrowest filtering takes place.

Fig. 2.4 shows the typical swept-tuned

included [12]. The swept-tuned
down-conversions

spectrum analyzer where all these IF stages are

and multiple

spectrum analyzer uses one up-conversion

(IF stages) in order to reject image frequencies. All the filters are

13

fixed-tuned

so better resolutions

can be achieved; also, the bandwidth

of the

final

IF

filter can be changed to control selectivity. The local oscillator sweeps across the desired
range of frequencies (which is translated into a visual swept between the start and stop
frequencies

of the spectrum being studied). The detector is used after the last IF stage to
signal, where the detected signal is converted

recover the incoming

into a dc value,

which represents the amplitude, and is sent to the circuitry that drives the display.

mixer
Input

X
Lo

'"

Envelope Detector

Vertical deflection

Honzontal deflection

vco

Voltage ramp

Fig. 2.3. Block diagram

of a superheterodyne

spectrum analyzer.

LO
d)

IF

if xed

LO~ ~
I

I"Mater
Input
Oet

le

Leman Ftiter
flntaae Reieetteel

I' lP Piller
I" L 0

2 IF alter

3 IF Fdler (Rural te Bandwtdih F It I

IVanaale

3 opC ael

V dee Falter

Fig. 2.4. Typical swept-tuned spectrum analyzer.

14

There are some important

specifications
which

that every spectrum

analyzer
signals

should satisfy.

First, resolution

bandwidth,

is the

ability

to resolve

of

different

&equencies, is determined

by the IF bandpass

filter bandwidth.

Second, the optimum

sweeping time for a given resolution bandwidth

and the frequency span, are related as

follows

[6]:

ST=k.
Rzu

(2.2)

where ST is the sweeping time, k is a constant that depends on the filter shape (for a
Gaussian
bandwidth.

filter is about 2.5), sPan is the &equency sPan and Rsrr is the resolution
Usually,
Rsrr and

ST are adjusted accordingly to the &equency span so a

reasonable

resolution

can be obtained;

if

a higher resolution

is desired, then longer

then it is

sweep times will be needed.

If low

level signals are going to be measured,

necessary to use narrow Rsrr, which implies longer measurement

times. Fig. 2.5 shows

some typical values for these parameters.

R=10kHz,
R s=l
kHz

ST=0 03 sec

R s=3 kHz, ST=0 i sec

ST=0 3 sec

R s=0.3 kHz, ST=3.3 sec

Frequency

Fig. 2.5. Spectrum analyzer measurement

for different values

of Rsrr

and ST.

From the previous

description

it can be seen that the measurement

of

the signal is

performed in the time domain; therefore, it is only an approximation

of the contents of

the actual frequency

of the

signal. Since the spectrum analyzer only measures the power

15

at

a certain frequency, the

phase

of a

given frequency component

is lost; as a result, the

measurement

obtained is not enough for reconstructing

the time domain representation

of the

signal. The detection and measurement

of

magnitude

and phase are required

because these quantities provide information about the transfer function of the system.
The magnitude and phase extraction can be implemented
using peak detectors and phase

detectors but they usually require calibration and are prone to errors over frequency,

power level and temperature

logarithmic

variations.

Calibrated

RF/IF vector analyzers

that use

amplifiers have been reported

[7]; these measurements

are fully ratiometric

since the result is given by the ratio V,,/V, . Another proposed solution is the use of
filter banks that are multiplexed
accordingly to the frequency being analyzed [8-11],but
the silicon area required is quite large, which makes them not very good candidates for

built-in testing.

From the previous discussion, the advantage of integrating

phase characterization
in one technique

frequency,

magnitude

and

results in a considerable

saving on testing time

because there will be no need to use two different tests in order to measure the spectrum
and the transfer function

of the DUT.

C. Proposed Solution
The architecture to be used is a built-in on-chip spectrum analyzer. The parameters

of
is

concern are transfer function, (magnitude

components.

and phase response) and harmonic

distortion
analyzer

For this purpose,

Fig.

the use of an on-chip

spectrum/vector

proposed.

2.6 shows

the basic block diagram

of the

scheme. The source generates

the stimuli that is applied to the DUT and its output is sensed by the detector. Having

both the input and output signals, we can compare and analyze them to decide if the

circuit is within the required specifications.

Device
Under

Test

On-Chip Spectrum/Vector
Analyzer

Source

Signal

Processor

Detector

V
/

External

xz'

Digital Control

Output

Control

Fig. 2.6. On-chip spectrum/vector

analyzer basic block diagram.

The techniques proposed to measure the frequency response of the DUT rely on the
capability of the circuit to generate a low distortion and accurate sinusoidal signal to be used as stimuh. Once this tone has passed through the DUT, it has to be measured and

compared with the stimuli in order to obtain the DUT transfer function.

The process descnbed above is repeated for different frequencies to obtain the full DUT
charactenzation.
In order to perform the harmomc

distortion testing, a single tone at a

fixed frequency is applied to the DUT. Then the center frequency of the high-Q filter is
changed to frequencies that are integer multiples of the frequency applied to the DUT
and their respective amplitudes
are measured. A vanable gain amplifier (VGA) is needed

for the optimization

of the

system dynamic

range. Usually

a very selective bandpass

filter is used in the detector in order to minimize the in-band noise and spurious tones.

Therefore the frequency of the stimuli and the filter's center frequency have to be fully
synchronized
in order

to avoid unwanted

attenuations

in the measured

tones. The

switched-capacitor

based techniques used ensure the synchronization

between the blocks

and bandpass

mentioned

above. It

is shown

in this thesis that

if both

signal generator

filter are controlled by the same digital signal, the tracking error of these parameters lies

17

within

0.5'lo since switched-capacitor

techniques

are used. The resolution

of

the

proposed on-chip spectrum-vector

achievable using switched-capacitors

analyzer

will be limited to 8 bits, which is easily

techniques.

A conceptual

schematic

diagram

of

the proposed

technique

to characterize
synthesizer,

analog

circuits is shown in Fig. 2.7. It consists

of a

digital I'requency

a switchedfilter and an

capacitor sinewave generator, two VGAs, a switched-capacitor

analog-to-digital

bandpass

converter. The system operates as follows: the frequency

synthesizer

generates the master clock used as the sinusoidal

generator sampling frequency as well

as the non-overlapping

clock phases for the switched-capacitor

techniques,

blocks. The sinewave

signal with a signal coming

generator, based on switched-capacitor

frequency

delivers a sinusoidal
amplitude

of I/16 of the master clock frequency. The

amplified/attenuated

of the

from the sinusoidal generator is adjustable to provide the proper level to the stimuli. The
output

of the DUT is

by the second VGA to accommodate it to the

proper input range

of both

bandpass filter and ADC. The narrowband

switched-capacitor

filter is a key building block

of the

spectrum-vector

analyzer,

its function is twofold:

one, it can be centered at the center frequency

second, to select the proper frequency component
characterization.

f, to

obtain the DUT transfer function;

( f2fp, 3f)for harmonic

distortion

Finally, the ADC delivers the signal to a digital tester to be processed.

The main advantage

of

this system

is its inherent

synchronization.

The sinewave

generator is based on switched-capacitor

circuits, with an oscillating frequency equal to

filter, f0, can be precisely defined

f, //6.

The center frequency

of the switched-capacitor

by both clock frequency and capacitor ratios as follows:

18

where

f, is the

sampling frequency, Cr is the integrating

capacitor and Cz is the switching

capacitor. Capacitive ratios can be as precise as 0. 1 rm Hence, adjusting the capacitor

ratios and the clock frequency,

the bandpass

filter's center &equency can be precisely

defined. Even more, given that the stimuli frequency and the filter center &equency are
tracked to each other (since both are generated from the master clock), the system is selfsynchroiuzed;

when the stimuli &equency is changed by the frequency synthesizer,

the

filter center &equency follows these adjustments.

Filter clocks

reference

clk

Frequency Synthesizer

f,
fsr
Smevrave Generator
Signal

Z'fo
3 sf

VGA

System Under Test

VGA

SC Bandpass Fdter
A/D

Converter

DSP, PC,
Drgnal Tester

Fig. 2.7. On-chip spectrum/vector

analyzer block diagram.

From the previous description, it can be noted that the blocks that conform the system
and their main properties are:

19

Digital Frequency Synthesizer: Should be flexible and simple. Since the number
generated

of frequencies to be
used.

is limited at 10, very simple digital circuitry can be

Sinewave

Generator.

A low distortion

switched-capacitor

oscillator (THD &

50dB) is desired for this block. The digital circuitry used to control the switches
should be as simple as possible.

Switched-Capacitor

Bandpass Filter: A biquadratic

implementation

is used; it

should be precise, with low noise, low power and high

g (50). The

capacitor spread

needs to be minimized

to reduce silicon area.

Voltage

Gain Amplifier:

This

is a programmable

gain

amplifier

with

an

attenuation/gain

range from -20 to 20 dB in 4 dB steps.

AnaloglDigital

Converter: 8 bits resolution. Must be simple and cheap.

The particular specifications for these blocks will be discussed in the next section and in
Chapter III.

D. Specifications
In this section we will discuss the main design issues and the specifications
builihng block.

for each

The first limitation to be considered is the distortion allowed in the sinewave generator
and bandpass

filter. Since we are using switched-capacitor

circuits, the limitation

in

resolution comes Irom the maximum

capacitor mismatch, which could be around 0. 1'/0.

This error corresponds to a resolution of 10 bits. A tradeoff between accuracy, system

20

robustness

and implementation

complexity takes us to limit the maximum

resolution of

the system to 8 bits. This value ensures a proper functionality

of the

test circuit under

with

increased

capacitor mismatch
complexity.

conditions

and

also comes in hand

a limited

implementation

A resolution

of 8 bits

corresponds to an error

of 0.4 '/o (-48 dB), From

the previous value

we can set the distortion

specification

for both the bandpass

filter and the sinewave

generator. The third harmonic distortion is set to be I LSB below the resolution
system, such that it is transparent

of the

to the ADC, yielding a value

of 0.2

'/o

(-54dB).

The distortion

of the

sinewave generator mainly depends on the number

of steps used

to

generate the sinusoidal

waveform.

If a

small number

of steps

is chosen, the harmonic

distortion could be very high. Since the introduced

and hold nature
small number

harmonics

are due to the sampling

of the signal, it is necessary to choose a number of steps that provides a of harmonic components along with a small silicon area. If 8 points are

used, the signal obtained can resemble a sinewave, but the number
high.

of harmonics

can be

If we

use 32 points, the signal will be purer, but the digital control logic increases
in the

(as well as the required silicon area) and there is not a significant improvement
harmonic

components

compared with the one obtained using 16 steps. Therefore, the

best option is to use 16 points, which provides a reduced digital logic and therefore a
small area and a proper number ofharmonic

components.

The quality of the harmonic distortion measurement factor

is highly dependent

on the quahty

g of the BP filter.

The higher the

g,

the more accurate the measurement

of the

harmonic distortion is. However a practical limit must be set for the quality factor

of the
the

filter. The following approach sets a quantitative

attenuation

value for Q. For HD3

~-54 dB,

Irom the center frequency fp to the third harmonic 3 fp, yields to:

21

~H(s)

H(s)~,

54dB

or

iH(s)

' &0.005

(2.4)

The transfer function

of a biquadratic

bandpass filter is given by:

No

H(s) =
S +

Ns

(2.5)
S+No

The transfer function of the filter is evaluated at frequencies, fo and 3fo and a Q that

satisfies the following relation is calculated:

64 Q', 9

&0.005

(2.6)

The required quality factor to provide an attenuation of -46 dB according to the previous
equation
is 75, which is extremely

high for this application.

Note that a high Q is

translated into a large capacitive spread or a higher order filter. Since one limitation for
this application is the use

of a small silicon area, this value could be unacceptable. If a Q

is 0.00749 (around 42.5 dB). Even though

of 50 is

assumed,

the obtained attenuation

this attenuation

is smaller than the original target, it provides

a reasonable

tradeoff

between complexity and performance.

Another issue to consider is the center to sampling Irequency ratio fg lf, . This ratio can be

calculated according to the number

of harmonic

components

to be measured.
switching
without

Since the
techniques,

filter transfer function repeats at f, /2 as a consequence

and at least the third frequency

of using

component has to be measurable

any effect

of

22

the aliasing (see fig. 2.8). Using a ratio

offp lf, = I/32

along with high Q, we can ensure

no effect on the first 4 harmonic components.

/
I

fp=
1

I
/

sf

/
p

2fp

3fp

4fp

3fo

6f

7fo

fo

fo

10fo

/
/
'I
1

I
2fp
3fp

f, = 16fo

4fp

ifo

6fp

fp

1 fo

12fo

13f 14f 15f

(b)

Fig. 2.8. Center-to-sampling

frequency relationship.

(a) f, = 8

f,. (b) f, = J6 f,.

Also, the frequency range where the proposed on-chip spectrum analyzer can operate has
to be evaluated. In order to avoid the hard constrain that a high frequency design implies
and since we want to probe the proposed principles only, this particular implementation

is set in the frequency range from 1 kHz to 10 kHz, Therefore a Gain-Bandwidth

product

(GBW) of 1 MHz for the operanonal transconductance

amplifiers (opamps) is proposed.

Finally, we have to set the number

measurement
that allows deciding

of frequency steps if the DUT is working

generated

in order to obtain a

within the specifications. Since

the main ob)ective is just to measure

function

the most important

frequencies

of

the transfer
1

of the DUT,

we set up to 10 different &equencies: &om 1 kHz to 10 kHz in

kHz steps which can be achievable using a simple digital &equency synthesizer.

The most important system specifications are given in table 2. 1.

23

Table 2. 1. Target specifications for the On-Chip network/spectrum

analyzer.

On-Chip

Specs

Network Spectrum
Analyzer

Harmonic

Distortion

&-54 dB
&-42 83

(Sinewave Generator)

Harmonic
(Randpass Filter)

Distortion

()uality

Factor
to

&50
16
1

(Randpass Filter)

Center

Sampling

Frequency Redo

(fJf

Frequency Range
Frequency Resolution

kHz-10 kHz
1

1-10 kHz in

kHz steps

24

CHAPTER III

BASIC BUILDING BLOCKS

A. Introduction
The blocks to be used in this project were defined on the previous chapter. All of them
use switched-capacitor
techniques

in order to assure the self-synchronization

of the

system. In this chapter, the main design issues are thscussed.

B.

Sinewave Generator

The purpose of this block is to generate the stimuli to be applied to the system under test.
Several approaches for generating sinewave signals have been reported
applications,
sinusoidal

[14-16].In many

signals can be generated using digital circuitry and a Digital to

Analog Converter (DAC). The signal to be generated is sampled in several points and

the obtained values are stored in a Read-Only Memory (ROM) and translated

into an

analog signal to be applied to the Device Under Test (DUT). Even though the signals
obtained using this technique have very low distortion and are very accurate when the

DAC and the ROM (or PEA) are added up, the resulting area is quite large. Since we
desire a small area, a simpler but efficient approach has to be used.

Fig. 3.1 shows the schematic diagram of the sinewave generator proposed in this work. It
consists of a programmable
gain amplifier

whose preset gain stages correspond to the

values of an ideal sampled and held sinewave. The amplifier has 4 different gain stages,

which generate a sinusoidal output with 16 steps per period. The switch PZ sets the zero

of the

sinusoidal

waveform. The switches PAI to through

PDl are closed

sequentially

with each clock cycle to generate the first quarter-period

of the sinusoidal waveform. .

25

Once the maximum values is obtained, the switches close in the opposite direction (from

PDI to PA1)
2

in order to generate the second quart-period.

In the second zero crossing,

the signal is generated.

PI,switches
advantage

from V, r to

Vpr

so the lower half

of

The

of this implementation

against direct digital synthesizers

lies in the simplicity

of the logic,

resulting in a very compact implementation.

PDI

CI
PD2

J
PBI

PC2

V,

~
P

j
PBI

PB2

-P

PA2

Voot

Fig. 3.1. Variable gain amplifier used to generate the sinewave.

An important

issue on the design

of the

sinusoidal

generator is the control logic for the

phases for
shows the

switches. Particular attention needs to be taken in generating non-overlapping

each control signal to avoid errors in the generation

logic used to control the switches
bi-directional

of the

sinewave. Fig.

3.2

of the

sinusoidal

generator. It is composed

of a

5-bit

shift register with clear and preset. The control signals generated by the

shift register are multiplied

by the non-overlapping

phases

f&

and f~ that control the

switches

of

the bandpass

filter. In order to obtain a full cycle, 16 clock cycles are

switching sequence obtained using this logic. Fig.

required. Fig.

3.3 shows the

3.4 shows

the simulated results for both the control signals and the sinusoidal output.

0
Ik

0,

0
Ik

D D
Ik

0
Q,
P

0
Ik

Ik

Q.

Ik

f, A

f, C

f. Z

A,

f,

PAI,

PBI,

PCI

PDI

PZI

PA'

PD

PIZ

PI2,

11

PBI

PCI

PDI

PZI

PA

PDI

ICI

Pl

'

Fig. 3.2. Logic control for the sinewave generator.

time

le

12

'13

'14

15

PZ

PD

PC

PBI
PAI

Fig. 3.3. Output sequence for the logic.

27

Sinewave

Generator

Responses

2.6

Pz

88

-2.8
2, 8

pet

88
2.8
2, 8

Pat

88
2.8

28
8.8 2.8

, : Pet

PA1

88
2.8

: trout
588m
8 8

-588

588u

1.2m

em
time

28m

2 em

2 em

(s

Fig. 3.4 Simulated control signals and output of the sinewave generator.

This implementation
and provides

has several advantages.

As stated above, the logic is very simple

signal is generated

a compact implementation.

The sinusoidal
very precise

using a
and since

digital

clock, which makes its frequency

techniques

and controllable

switched-capacitor

are used, the synchronization

with the bandpass

filter is

ensured. Since this circuit uses just one operational

amplifier,

a very compact structure

results.

One

of the

most important

characteristics

of the circuit is

that it should have a very low

harmonic distortion to be able to measure properly the DUT. The main limitations

of this

block are due to the finite parameters of the operational amplifier and clock feed-through

effects. The maximum operation frequency is given by the maximum frequency at which
the opamp
maximum

can work. A rule

of

thumb

for switched

capacitor circuits is that the

frequency is limited by the gain-bandwidth

product according

to:

f, =
Since the sinewave
frequency
is generated
using

2n
10

GBW(Hz)

(3.1)

16 points, the output

trequency

vs. clock

is ratio 1/16. This ratio provides

a good trade-off between implementation

resolution
that is achieved when

complexity

and harmonic

distortion.

The maximum

switched-capacitor
enough.

techniques

are used is 8 bits; therefore, a HD3 less than -46 dB is

From Fig. 2.7, we can see that the amplitude

adjusted by a VGA to provide a proper level
under test (DUT). From Fig.
signal is determmed

of

the sinusoidal

generator

output

is

of the

stimuli to be applied to the device

3.1,

it can be noted that the amphtude

of the

sinusoidal

by the reference voltage + V, A therefore, the use

of the

VGA shown

in Fig. 2.7 can be avoided and the amplitude

of the

sinusoidal

signal is controlled with

the magnitude

of the

reference voltage. The values

of the capacitors used

in the sinewave

generator are calculated according to:

= Sin(90') C,
C,'

C, = =' Sm(67. 5')

C,

' = Sm(45') C,
The minimum
capacitors

C,

' = Sin(22. 5')

Table 3.1 shows the final values of the

capacitor C4 is set to 2 pF.

29

Table
Cr C9 Cs

3. 1. Capacitor
5.22 F 3.7 F 5 22 F

values for the sinewave generator.

Cr
C4
C(ops

4.83 pF 2 F 20 97

C. Bandpass Filter
Another critical building block

of this

system is the bandpass filter. As stated in Chapter

in order to perform

II, a high quality factor is required

measurement

the harmonic

distortion

fmm the DUT. Due to the important role played by the filter in the system,

special care must be taken in its design.

The harmonic distortion measurement

the filter. First, the quality

will set the specifications for the quality factor

of

factor should be high enough

to select the frequency

depicted

component to be measured and attenuate other components. This is graphically

on Fig. 3.5. Consider a bandpass filter with a high quality factor (Q). When measuring
the fundamental

component, all harmonic components

should be attenuated

and the only

component amplified is fp, but when an harmonic distortion measurement

the amplitude

at 2 fp is made,
is

of the

fundamental

should be attenuated

in such way that its magnitude

much smaller than the one at 2 f0 it should be attenuated

at least -46 dB. The same

at 2 fp should be attenuated

applies for the measurement

meanwhile

of 3 fp, where

the component

the one at 3 fp should be passed. Lets consider now a bandpass

filter with a
that when a

wider bandwidth
measurement

(low

g)

like the one shown in Fig.

3.5(b). We can see

of the second

harmonic is performed, the amplitude

of the

fundamental

is

considerably

large, sometimes

even larger than the second harmonic when the filter is

not precisely centered. As we can see, the effect of Q is more critical for the second and
third harmonic distortion characterization.

30

2f

3fo

Frequency

2f

3fFrequency
Frequency

2 "o

3&

Frequency

2t;,

3j,

Frequency

Frequency
o o

Frequency

2o

Frequency

Fig. 3.5. Quality factor effects in the selection of the harmonic distortion component. (a)
High

g (b) Low

Q.

A second issue to consider is the precision of the filter's center &equency. A small
deviation of the center frequency can lead to incorrect measurements
as shown in Fig.

31

3.6. Consider, for instance,

the center frequency
attenuated

the measurement

of the

fundamental;

it can be noted that

if

of this

filter deviates from the desired frequency, this component is

than we expected. This effect is
and harmonic distortion

while the second harmonic is less attenuated

even more severe when high Q filters are used. Both magnitude
measurements

are sensitive to these errors.

+af f; t,

2(,

3fo

Frequency

f.= if+sf
fo

2$

3 f,

Frequency
o o o

Frequency

f,= 3f +sf

2fo

Frequency

Fig. 3.6. Effect of the accuracy of the center frequency on fundamental,

harmonic measurements.

second and third

From the previous discussion, the need of implementing

quality

a bandpass

filter with a high

signal is

factor, accurate center &equency synchronized

with the incoming

must. The first problem implies the use

of a large capacitor

ratio to achieve a high

g; the
in this

need

of a

small area requires the use

of an alternative technique to reduce the capacitive

is the best choice.

spread. The second problem can be solved using a very precise approximation:

case, a predistorted bilinear transformation

32

Since the system is intended for on-chip testing, the silicon area required by the filter
should be minimized,
preventing

the use

of a high

order filter. A second order switchedis employed.

capacitor filter using the bilinear approximation

approximation

Even though the bilinear

yields a more complex implementation

than the forward or the backward

approximations,

it is preferred because it provides better accuracy and move attenuation

of higher

frequencies due to the zero located at f/2.

The specifications to be met are the following:

~ ~

f, lf,
Q

=1/32

=50
and Fig.

Fig. 3.7 shows the bandpass filter implementafion,

block diagram.

3.8

shows its corresponding

C~l
C

C,

OUi

Fig. 3.7. Switched-capacitor bandpass filter.

33

C,
C,
1

z'
z'

Cz
Ci

1-z '

C,
Ci
1

z
V

C, C,

1 1

z'

C, C,

Fig. 3.8. Block diagram for the switched-capacitor

bandpass filter.

The bilinear bandpass transfer function is given by:

-2

H( )=A

z'+a ='+b
shown in Fig.

(3 3)

and the transfer function of the block diagram

3.8 is:

H(z)
2

(3.4)
z
11

By comparing both the bilinear and filter transfer functions (equations 3.3
can find the required values for the capacitors. These values are summarized
for a unity peak gain reahzation. The minimum
design of this filter can be found in appendix A.

and

3.4), we
detailed

on table 3.2

capacitor is set to

0.2 pF. A

34

Table 3.2. Capacitor values for the SC bandpass filter.

Cs Cs
Cg

02 F
10.04 F 10.04 F 0.2 F

Cr Cs Cs
Croiag

5116 F
51.16 F 1.02 F
123 82 F

From table 3.2 it can be seen that the capacitor spread is very large (1:250).Notice that
the smallest capacitors are Cg and Cs, those that connol the quality factor and the peak
gain

of the

filter. For high

g, the capacitance

spread becomes exnemely large. The large

capacitive spread implies many problems

spread
means

in the design

of the

filter. First, the large

a large silicon area and increased

power consumption.

Second, the

mismatch between the capacitors is also increased.

A method that allows to reduce the capacitive spread while maintaining the high
filter is needed

g of the

[17].The

associated resistance

of the switched-capacitor Co is given by:

1

(3 5)

CQ

where

we decrease

f, is the sampling fiequency f, by a factor n, then

and Cti is the capacitor that emulates the resistor.

If

the eqmvalent resistance increases by the same factor

n as follows:

f/

(3.6)

Co

Since the obtained equivalent resistance is n times larger than the original R,~, and the
time constant

(R,q
should

C&)

of

the integrator

must

be maintained,

then the integrating

capacitor

C&

be scaled down by the same factor n, effectively reducing the

35

capacitance

spread by a factor n. Using this technique,

an effective reduction

in the

capacitive spread can be obtained without sacrificing the filter's performance.

Table 3.3 shows the new values

of the capacitors for

n =4. It can be noted that these

values are much smaller than the original ones, leading to a capacitive spread

of I:64.

Furthermore,

if the

minimum

capacitance is reduced to 0. 1 pF, the absolute value

of all

capacitors is also reduced. The final capacitor values are given on table

3.4.

Table 3.3. New capacitor values for the SC bandpass filter.

Cs
C2 Cq

C
Table

0.2 pF 2.5 F 2.5 F 0.2 F

Cz

Cs Cs
Croppy(

12.78 F 12.78 F 1.02pF 31.98 F

3.4. Final

capacitor values for the SC bandpass filter.

Co

Cs
Cv

C
Figure

0.1 pF 1.25 pF 1.25 pF 0. 1 F

the implementation

Ci
Cs Cs

6.3 F 6.3 F 0.51 pF

15.99 pF
technique.

Cr,l~

3.8 shows

of the described

1' CQ

1'

C1
CO

C3

72
Vin

Voul

cs

Fig. 3.9. Bandpass filter with additional sampling Irequencyin Cg. (fi' = 'l4. fi andfz'='l~ fz).

36

Fig. 3.9 shows the modified schematic. The filter was simulated in Switcap. Fig. 3.10
shows

a comparison

of

the bandpass

filter when

the capacitive

spread

reduction

technique is used. Since the effective Q is increased by factor 4, the peak gain increases

by the same factor, as can be seen on Fig.

adjusted. For unity gain filters, both
shows the simulated output
CF)

3.10, since

the input capacitance Ct) was not

and Cs must be scaled down properly. Fig.

3.11

of the filter for a 5 mV

input signal at

Khz.

ste it ta

estusqes

st)ter

u nng

tqoo sana)ang

sequent)ca

's, s t"

qtt 0 1

10

Unng one sang)ltng gequency

-10

-10

-30

5(q)

No)
Fmqqqrtto

100)
Fn)

3000

Fig. 3.10. Switcap simulation for the filter.

37

Bandpass Filter
Transient

Response

58m
28m

18m
-48m

78m
78m

48m 1 8m

28m
-58m

32m

time

38m (s )

48m

42m

44m

Fig. 3.11. Simulated time response for the bandpass filter.

D. Voltage Gain Amplifier (VGA)

Another important
amplitude

block is the variable gain amplifier. The VGA accommodates

signal coming from the bandpass

the

of the

filter to cover the complete dynamic

range

of the

ADC and to avoid a reduction in resolution due to a small input signal. For
amplification
'g,. factors in 4 dB steps ar e p ro p osed.. Fi

this application,

3.12

shows the

schematic of the VGA. The VGA is a capacitive amplifier with capacitors

u Cq through

setting the desired gain and conuolled by switches D through H. It is important

for the

VGA to have an offset compensation

due to the finite gain

scheme in order to avoid the introduction

of errors
scheme

of the

amplifier and dc offsets. The offset compensation

Cq and

works as follows: during phase 2, the input capacitors

C7 sample

the offset
and the

voltage while C6 holds the output; during phase

I, the

polarity

of C7 is reversed

38

measured

stored offset voltage

is subtracted

from the input voltage plus the offset

voltage [18].The capacitor values are given in table 3.5.

C6

C3

J
1

c7

Vin

C1
vout

Ct

Fig. 3.12. Variable gain amplifier.

Table

3.5. Capacitor
0.34 pF 0.2 F 05 F 1.241 F 0.2 F

values for the VGA.

Cr
Cg Cy

C6

Ct~&

0.34 pF 0315 F 0792 F 034 F 4.268 F

39

E.

Operational AmpiiTier (Opamp)

This section deals with the design

of the

opamp. The specifications to be met by the

opamp are based on the features required by the filter because this is the block with more
stringent constrains.

In order to determine the minimum

gain

of the
I

opamp, consider the follovnng:

P
where

(3 7)

s is

the maximum

accuracy error permissible,

P is

the feedback factor equal to

0.5 and A is the opamp dc gain. For an error of I'/w we have that the minimum dc gain
should be 200.

The gain-bandwidth
as follows:

product GBW is determined

by the maximum

sampling

frequency

GBW &10

f,

(3.8)

Then, for a 32 kHz sampling frequency, the minimum GWB should be 320 kHz.

The load capacitor is estimated adding all the capacitors that will be connected at the
output

of the

opamp in each clock cycle, which will be at most 10 pF.

Form the previous discussion, we can set the design specifications for the opamp:

A, & 200 (46 dB).

GBW
&

~ ~

I MHz.

Ct = 10pF.

40

Fig. 3.13 shows the schematic of the opamp. It consists of a differential pair (Mq-Mz) and
three current mirrors
(Mq-Ms) with a cascode output

stage (M6c-Msq). The design

procedure is described in appendix

B. The

final transistor sizes are given in table

3.6.

Voo

M,

M4

M4

M4

Ib

M4c

Msc

M, 4

M4

~ss
Figure

3.13. Opamp

schematic.

41

Table 3.6. Sizes for the opamp transistors.

Trdrrtsistor

8'(pm)
5, 52

L(~)
1.2 1.2 1.2
1.2 1.2

Mn Ms

13.2

3.86
MsrMsrsMa Mdc

4.8
4.8

3.86
1.316

Mn Mg, Mac Mn Mitt

1.62

2.63

3.3

F.

Analog-to-Digital

Converter

Even though this block is not being implemented

on this chip and an external ADC will

that

be used, it is important to discuss some issues about its design. An implementation

is fast enough, compact and provides enough resolution is presented.

For this purpose, an algorithmic

converter is shown in Fig.
approximation

ADC can be used [19-20]. A block diagram of the

structure works in a similar way as the successive-

3.14. This

converter, but in this case, the remaining

voltage is doubled instead

of

being halved, and the reference voltage is unchanged. time and a moderate circuit complexity.

This provides a quick conversion

Vm

Track
aod Hold

V,

Comparator

Senal
Output

V,

Va

~vm

/2

Fig. 3.14. Block diagram of the algorithmic A/D converter.

42

The conversion is made as follows: first, the input signal is sampled by a track and hold
circuit and then passed to a comparator.

If the

comparator input signal, V, is larger than

the reference voltage V, f, the corresponding

Depending on the value assigned to this bit,
subtracted

bit is set to 1, otherwise,

it is set to 0.

a voltage V,s,/2 is added (if the bit is 0) or

(if the

bit is

I) to

V, . This process is repeated until the desired number

of bits
3.15,

is obtained. As we can see, this converter requires small area because it reuses the same
circuitry to perform
the conversion.

The whole process is summanzed

in Fig.

where the flow graph for the algorithmic approach is presented.

Qs~.

V&=v, to
Vot

) [ Btt=1
/2) ,

V=2(V-V

V=2(V+V

j2)

I=i+i

No

i&N

Vo.

Stop

Fig. 3.15. Flow graph for the algorithmic approach.

One of the most cntical blocks in this architecture

introduced by this block should be minimized

is the multiplier

by two. The error

in order to reduce errors in the final result input and output capacitors will give us

of the

conversion. As we know, the ratio

of the

43

the gain, but because

of the

nature

of the fabrication process, a mismatch in their sizes

can be generated. Therefore, we need to find a way to reduce the error introduced by this possible mismatch.

A common source

of error

is the offset generated by the opamp due to its finite gain and

transistor mismatches. The use

this error.

of techniques

using switched capacitors help us to reduce

The architecture used in the multiplier by two is shown in Fig. 3.16(a) [21].It consists of
an opamp, two capacitors and seven switches. The circuit works as follows: This circuit

requires seven different phases, which are shown in Fig.

3.16(b). In the first period,

the

input voltage is sampled in Ci as well as the input offset voltage; in the second one, the

charged stored in Ci is transferred

to Cz. In the third period, the input is sampled again

in the previous stage. Finally, in the
in Ci and are present

and Cz is floating, so it holds the charge transferred

fourth penod, the charges from Ci and Cz are combined

at the

output. As we can see, the final value

of the

multiplication

does not depend on the

capacitor matching, but in the number of integrations

configuration

made. Fig.

3.17 shows

the circuit

for each phase.

In the next chapter, simulation and experimental

system
vtdll

results for each block and the complete

be discussed.

44

CI

v. ~

J
V

(a)

(b)

Fig. 3.16. (a) Schematic of the multiplier by two. (b) Phases.

aX
a

C
b

Vinn

J
Vout

Vfn n

Vout

Phase

a
I&

C
b

Vtn n

VinW
Vout

J
Vout

Phase 3

Phase 4

Fig. 3. 17. Multipher by two: circuit configuratton

for each phase.

46

B.

Sinewave Generator

As stated in the previous chapter, the purpose

of this block

is to generate the stimuli to

results

be applied to the system under test. Figure 4.2 shows the simulated
sinewave generator wtth a 500 mV reference voltage. Since the amplitude

for the
output

of the

waveform

is proportional

to V, f, it can be adjusted to provide the proper amplitude.

Table 4. 1 shows the simulated and measured results for the spectrum at fa 2 f0, and 3 f0

for a reference voltage of + 50 mV and an output frequency

of 1 kHz.

688m

8.M

6Mm

Fig. 4.2. Simulated output of the sinewave generator.

Table 4. 1. Simulated and experimental

results for the harmonic components

of the

sinewave generator for Vf=50 mV.

Simulated

-74.61 dBc -64.02 dBc -90.29 dBc -59.08 dBc

3feasured - 66.31 dBc -51.09 dBc -70.92 dBc -53.24 dBc

Figure 4.3 shows the transient response

signal for three different

of the

sinewave generator. This plot shows the

reference voltages: +200 mV, +100 mV and +50 mV. The

kHz

oscillating frequency is

%+V/8v.

ir

I t I

t
1

3
I

I-W

4'

t *M-+-

"I""4-,

I I

t
i
t

4
I I

---kf

t
I
f

'I

Betet 88
tttRCE

&)2
Bffstt

Taaet NBSB N

8:
A

Cht Beeetrun

1,088 d8

08tr

/dt's

.10
d8

-100
dBJt

8'tg 'tt

0 Ht

Btedt 10 kdt

ete: IPHS-82

faetex 6$83P.

N
1

000,

Ht

-89 888

88tt/Nt

dde/BB

-180

49

The rms value for the 200 mV~ input signal is given by:
V, (rms)

Vp

= 200m V = 141.42m

V,

(4.1)

From Fig. 4.5, the noise power measured (in dBm) in the bandwidth of interest is given by:

P = 59.26+10

log(BW)

(4.2)

where BW is the filter bandwidth at 1 kHz, which is 6 Hz. Then:

P= 59.26+10 log(6) = 59.26+ 7.78 = 51.47 dBm

The rms power is given by:

(4 3)

51.47dBm =10 log[ ll

normalizing
to a 50

(P

= 7.55n W, m gJJ P,

(4 4)

D resistor:

V,

= JP, 0=~7, 55 10' (50i=614"10'

(4.5)

The dynamic range is given by:

DB =20

log,

141.42m V, " * =47.247dB 6.14x10 'V,

(4.6)

Table 4.2 shows a summary of these measurements.

50

Table 4.2 Sinewave generator measurements

summary.

Spec
D3
cise
ynamic range
aximum input

Value
51 dB (Fig. 4.4)

47 dBc at
kHz (Fig. 4.5) 7.25 dB

00 mVp

eltage

C. Bandpass Filter
As discussed before, the most critial block of the system is the bandpass filter. A very

precise center frequency

characterization

and high

quahty

factor are required

to provide a reliable
and are

of the

device under test. Some

of this

specs were measured

discussed on this section.

Fig. 4.6

shows the filter transfer function. The sampling

frequency

is 32 kHZ (1 kHz

center trequency)

and the sampling

f'requency

for C0 is 8 kHz (see Fig. 3.9). The

measured quality factor is around 380.

4tH 8P~Z'f&Z
RACK

Tice.

fZ". N PN

keepensa Sg.F~m kit"

003.$$

Hg

4t

'

Af)V

52

Fig. 4.8 shows the filter peak gain measured from

the limited GBW of the opamp.

kHz to 9 kHz. It can be seen that it

follows an almost constant value up to 8 kHz; after this value, the error increases due to

If a higher

frequency operation is desired, then the GBW

of the

opamp should be increased. In Fig.

4.9 the quality factor of the filter from I kHz

to 9 kHz is shown. The value moves between 380 and 420, but this is mainly due to
measurement

errors. A behavior similar to the one achieved in Fig. 4.8 is expected.

39 5

38 5

nl

38

'o
r

375
37 36 5

u-

35 5 1000

2000

3000

4000

500D

60DO

TDOD

800D

9000

Center frnquencyfo

fHz)

Fig. 4.8. Gain for the bandpass filter.

560
540 520

500
ty

490

rr 460

440
4

420

400

380 360 1000

2000

3000

4000 5000 6000 Centerfrequencyfo)Ht)

TDOO

8000

900D

Fig. 4.9 Quality factor for the bandpass filter.

ate:

08-38HZ,

Vice'. 84

% PN

-t55 ' .d@N'

C&at er '

YRRCK'

R'

IHr HRHHHz

CHR

Irttt Hzrkzr

IC

/div

118

', I IHI HHMtrHz

Czniart

HHz

55

(4.11)

The signal to noise ratio is given by:

SNR

=20 log
of these

" III 322x10-'V

results.

',

=84. 17dB

(4. 12)

Table 4.3 shows a summary

Table 4.3 Bandpass filter measurements

summary.

Spec

Value

-75 dB (Fig. 4. 10)

cise

1'
uxituutu iuput

13.228 ltVrms Fig. 4. 1 I)

84 dB

302.6 Vp
1

altage
requeucy rauge
kHz

9 kHz

D. Voltage Gain Amplifier (VGA)

The VGA is used aAer the signal has been filtered by the bandpass
gain steps
filter. In this case,

of 4 dB each

are used. Fig.

4. 12 shows the response of the VGA for 5

signal

different gains: 0, 8 12, 16 and 20 dB when a sinusoidal

amplitude

of

kHz and +80 mV

is applied. Fig. 4. 13 shows the error between

the ideal and the measured

values. It can be noted that the obtained results have a gain error below 0.25 dB.

Y w-~-*"

-s.f

+w

T
I

RACE

Rg

888/HX

-RS

$2

PS8

8 AS 8

Hx

-137 817 de

Hz

ORHQR

18
/III
CIR Y

!
.

818PI IC .RHR

CHAPTER V

CONCLUSIONS

Integrated circuits are becoming more complex as the featured size decreases. This trend

allows us to implement more functions on a single chip, making them more prone to fail.
Usually, each analog circuit requires a "custom made" testing circuit. Then, the need of
finding a umversal test technique for analog circuits is a must.

This work deals with some of the many problems that analog testing engineers find very

often. Some of the goals to achieve are to use an external digital tester instead

of the

analog or mixed-signal tester to reduce the test nme as well as facilitate the test program
generation. An important
issue to consider is the silicon area used for the testing circuit,

since it should not represent a large area overhead for the whole circuit. Also, the testing

circuit should not interfere with the DUT performance

when it is working

in normal

mode.

With these purposes in mind, an on-chip spectrum/vector

analyzer for built-in testing

of

analog ICs has been proposed. The idea behind this work is based on the most popular
test techniques: spectrum and network analyzers. Using this approach there is not need
to reconfigure the DUT. Since one
the use

of the

most critical issues to solve is synchronization,

a must, where a high accuracy and robustness

of switched capacitor techniques is

can be achieved and the synchronization

between all the blocks is ensured.

In order to probe the main ideas

of this

work, several blocks were designed: a sinewave

generator, a high-g bandpass filter and a voltage gam amplifier (VGA). An analog-todigital converter can be added, but it is not included in this system. All
use switched-capacitor
techniques to ensure synchronization.

of these blocks

59

The required features for the sinewave generator included a dynamic range larger than
45 dB, center frequency and amplitude programmabihty
all the other blocks. The sinusoidal as well as synchronization
with

signal is obtained by using 16 samples

of an

ideal

sinewave and since its amplitude is set by a reference voltage and can provide the proper
dynamic range for the DUT, the input VGA was removed. The proposed architecture

requires a very simple digital logic to control the step sizes of the sinusoidal signal and

since it requires one operational amplifier only, a very compact implementation

results.

The bandpass filter was the block with more constrains. Since a high quality factor and a
very precise center frequency are a must, special care has to be taken in its design. The

first issue was solving using a predistorted

bilinear transformation;

The high quality

factor yield to a very high capacitive spread, but this can be reduced by using a different
sampling
frequency

(fin) for the capacitor that controls the Q of the filter: in order to
the equivalent

keep the same time constant,

resistance

is increased,

reducing

the

capacitor spread by the same factor (n).

The voltage gain amplifier is used to provide a proper dynamic range to the ADC, as
well as to avoid a reduction in resolution due to small input signals. For this purpose, a

variable gain amplifier with six gain steps of 4 dB each (from zero to 20 dB) is used. The
structure
used is offset and gain compensated

in order to reduce the introduction

of

errors due to the dc offset and finite gain of the opamp. The gain is set externally

according to the desired level.

The complete system was fabricated through the MOSIS service, using the AMI 0.5 )im

CMOS process. The silicon required

for the on-chip spectrum/vector

analyzer

was

750pmx550tim. Experimental results has been presented and summarized

in Chapter

III.

In summary,

a compact on-chip spectrum/vector

analyzer using SC techniques

has been

proposed, where the signal generation

is made using the digital clock and a frequency

60

synthesizer.

Magnitude

and phase characterization

and harmonic distortion

of the DUT
used,
full

can

be

measured.

Since

switched-capacitor

techniques

are

being

synchronization

of the

system is achieved and the precision obtained can be as low as

61

REFERENCES

[I] G.W. Roberts,

"Metrics, Techniques

and New Developments

in Mixed-Signal

Testing", Tutorial presented

at the International

Test Conference

1999, IEEE

Computer Society, Atlantic City, N. J., September 26-October

I, 1999.
Testing:
An

[2] G.W. Roberts,

Innoduction",

"Metric

and

Techniques

of Mixed-Signal

presented

in the Analog and Mixed-Signal

Testing Short Course,

Texas A&M University, College Station, November 13-17, 2000.

[3] A.

Rueda, "Analog and

Mixed-Signal

Testing", presented

in the Analog and

College Station,

Mixed-Signa! Testing Short Course, Texas A&M University,

Tx., November 13-17, 2000.

[4] B. Provost, "Design Methodologyfor Mixed-Signal AC BIST and ADC SelfCahbration" Ph. D. Dissertation, Texas A&M University, May 2002.

[5] B. Dufort, G.W.

Roberts, "On-Chip Analog Signal Generator for Mixed-Signal

Built-in-Self Test", Proceedings of the IEEE 1998, Custom Integrated Circuits

Conference, Santa Clara, California, USA. ,

1998.
Mountreux,

[6] J. M.

Byrd,

F. Caspers,

"Spectrum and Network Analyzers", Joint US-CERV-

Japan-Russia
Switzerland,

Particle Accelerators School on Beam Measurement,

11-20 May 1998.

[7] J.

Cowles and

B. Gilbert, "A

Cahbrated

RF/IF Monolithic Vector Analyzer",

2001 IEEE MTT-S Microwave Symposium Digest, Vol. 3, Phoenix, Arizona, pp.

2163-2161, 2001.

[8] L. T. Lin,
Monolithic

FL Tseng, D. Cox,

S. S. Viglione, D. P. Conrad

and

R. G. Runge, "A
State Circuits,

Audio Spectrum Analyzer",

IEEE Journal of Solid

Vol. SC-18, No.

I, pp. 40-45, February 1983.

Nakayama,

[9) Y. Kuraishi, K.
Channel

Z. Miyadera and T. Okamura, "A Single-Ship 20Switched-Capacitor

Speech Specmim Analyzer Using a Multiplexed

Filter Bank",

IEEE Journal of Solid State Circuits, Vol. SC-19, No. 6, pp. 964-

970, December 1984.

62

[10]J. S.

Chang,

Y.C. Tong, "A Micropower-Compatible

Time Multiplexed

SC

Speech Spectrum Analyzer Design",

IEEE Journal of Solid State Circuits, Vol.

RF Vector Analyzer Based on
on

28, No. I, pp. 40-48, January 1993.

[11]R. Courteau, T. K.
Synchronous
Measurement,

Bose, "A High-Precision

Sampling",

IEEE Transactions

Instrumentation

and

Vol. 43, No. 2, pp. 306-310, April 1994.

Company,
Everett, WA. ,

[12] HP

3588A Getting Started Guide, Hewlett-Packard

March

1990.
Short Time Founer Transform
Department
Spectruni Analyzer:
A

[13]L.

Chan, A Continuous

Project Report, Texas A&M University,

October

of Electrical

Engineering,

1995.
Chiappano,

[14]G. Boarin, G.
Implementation

F.

Maloberti,

S.

Napolitano,

M. Porta, "VLSI

of the

Metering Signal Generator for Switching System Analog

Terminations",

IEEE, Personal collection of M. G. Mendez Rivers, 1990.

[15]J.

Silva-Martinez,

E. Sanchez-Sinencio,

"Excess Phase-Jitter

Cancellation

Method
Systems,

for SC Relaxation

Oscillators", IEEE Transactions

on Circuits

and

Vol. CAS-34, No. 6, pp. 695-700, June 1987.

[16]H.C.

Patangia,

B.

Zenone,

"A Programmable
the 37th Midwest

Switched-Capacitor
Symposium

Sinewave

Generator",
Systems,

Proceedings

of

on Circuits

and

IEEE, Vol, 1, pp. 165-168, 1994.

G. Torelli, E, Sanchez-Sinencio,
Sampled

[17]J. L. Ausin, J. F. Duque-Carrillo,

"Penodical
Nonuniform

F. Malobern.
Circuits",

Individually

Switched-Capacitor

ISCAS 2000-IEEE International

Switzerland,

Symposium

on Circuits and Systems, Geneva,

pp. 449-452, May 2000.

Area-Efficient Approach to Realizing Very

[18]S. Nagaraj, "A Parasitic-Insensitive

large Time Constants

in Switched-Capacitor

Circuits", IEEE Transactions

on

Circuits and Systems, Vol.

36, No. 9,pp. 1210-1216, September 1989.

63

W. [19]P.

Li, M.

J.

Chin,

P. R.

Gray and

R. Castello, "A Ratio Independent

Technique", IEEE Journal

Algorithmic

Analog-to-Digital

Conversion

of Sohd

State Circuits, Vol. 19, pp. 828-836, December 1984.

[20]R. H.

McCharles,

V.A. Saletore, W. C. Black Jr. and D. A. Hodges, "An

Converter",

Algorithmic

Analog-to-Digital

IEEE International

Solid State

Circuits Conference, Philadelphia,

February 1975.

[21]A. Johns, K. Martin,

New York,

Analog Integrated Circuit Design, John Wiley& Sons Inc. ,

NY, 1997.

64

APPENDIX
A. Bandpass Filter Design
In Chapter III we discussed the filter architecture

to be used. A second order bandpass

approximation

filter

using

swtiched-capacitors

and

a bilinear

is proposed.

The

specifications to be met are the following:

~ ~

f, =1kHz
f, = 32 kHz g =50
HD3
m (T, = 31.25x10-6 s. )

~
~

( -42 dB
of a bandpass
filter is given by:

The charactenstic transfer function

I')
s +
where ra, is given by

s+co
(A. 1)

ra.

=2

rr

f, =2

rr

(1000)=628318x10' rad(sec

(A. 2)

In order to simplify the calculations, we will use the previous equation in the following

form:

H(s) =

s'+a s+b

(A. 3)

65

where a

and b are

given by:

a=

' = 628318 10' = 125.6637061 50 g

'

rad / sec

(A. 4)
b = m,

=(6.28318x10') = 39.478x10'rad/sec
of
the filter can be found with the

In the other side, we know that the bandwidth

following equation:

(7=

BW

' mBW=

'= 6.28318 x10' 50

ai,
Q

= 125.6637 rad /sec = 20Hz

(A. 5)

As we know, a very precise aproximation is needed in order to obtain the desired center
frequency;
hence the bilineal transformation

is used. The transfer

function

in the z-

domain for this case, is obtained using the following equation:

2 'I S=

'

I+z'

(A.6)

After some algebraic manipulation,

we end up with the following result:

-2

H(z) =2

T.

b. T' 2

T+4

'+

2 b

T 8 z

'+

T'+2

a T+4

(A7)

Now, we

will apply

the prewarping

for the bilinear transformation

as follows

66

For the

central frequency

of 1 kHz

and a sampling frequency

of 32 KHz:

CrP

31.25 x10 ,

tan

( 6.28318x10'
2

31.25x10 '
(A. 9)

= 6.30345 x10'rad/sec =1.0032252 Hz

And the new values

of the

constants a and b are:

a = 126.0689963

b = 39.73347x106

Substituting

the values

of

a and b in the z-domain

transfer

function and aAer some

algebra, we obtain:

H(c) = 6.419x10

'.
z

' 1.8596

'

+1.01284

(A. 10)

The previous transfer function is compared with the block diagram of the switchedcapacitors
implementation
in order

to obtain

the capacitor

values

required.

The

implementation

of

the circuit and the block diagram

is given in figure A. l and A.2

respectively.

67

c
2
C
2

V,,

Fig. A. l. Switched-capacitor bandpass filter.

C
C,

z'
i-z-'

Cz

=' C, i

C,
V,

z' C, i

C, C,

i-z-'

C, C,

Fig. A. 2. Block diagram for the switched-capacitor

bandpass filter.

The transfer function

of the

block diagram is:

68

" (-'):::((-'-I)
And after some algebra:
C4 C5
r

C,

1-z'

C, C,

1-z'

(A. 1 1)

Co

C4 C5

Co

H(z)

C, C3

Ci

Ci C3

C,

(A. 12)

z'+
or

'

"

z'+

1+

(Co 'Ci

Co 'C~

H(z)
4

(A. 13)

By comparing both the block diagram and the filter transfer functions, we can easily find
the required values for the capacitors. The obtained values summarized

on table

3.1 are

calculated form the following relationships:

C, C,
C4 C,

and

C,

=C,

C, =C4

(A. 14)

The final results are given in Chapter III section

B.

69

B.

Operational Amplifier (Opamp)

The operational amplifier is a common element is all the block of the system proposed in
this work.

The specs to comply are:

~ ~ ~

3=200 (46 dB).

GBW=I MHz.
Cr = 10 pF.

Figure

Bl

shows the schematic

of the opamp. It consists of a differential pair

and three

current mirrors with cascode stage output. The design procedure is carried out next.

M4

M4

M4

Ib

M4c

Msc

Mio

M,

M4

Figure

B.l. Opamp

schematic.

The parameters for the AMI 0.5 pm process are:

70

V,

=0.79V
=0,93 V
A/V

Vip

~
~

K= 114.6x10
K~

= 38x10 A/V

First, we need to know what is the minimum

properly.

required bias current so the opamp works

1'4' Visas
t,

'

CL

(B.1)

where Vqu is fixed to 50 mV because we are using a cascode structure and we need to
ensure there is enough room to keep all the transistors in the saturation region. t, is the

time require to ensure a proper charging and discharging

we find that the minimum
current required is around

of Cz. After some calculations,

iiA . Hence, we can fix this

0.720

current to a higher value in order to get more gain. A bias current

of 8 liA

can be used.

The

required

for the differential pair in order to charge the capacitive load in 4.r is

given by:

gmci

= 16*C,

(B.2)

With this equation, we can easily find the sizes of transistors

M&

and

Mi. Using:

L,

ID

(B.3)

71

For transistors Ms and

Mq, we

fix Vq, and calculate the transconductance

using:

"34

Is

Vdsof3, 4

(B 4)

and the sizes of transistors M3 and M~. Using:

L,

2 K ID

(B.S)

For a mirronng current of 1 in Ms and M6.

(B.6)

The cascode transistors Mi c and M6i- have the same sizes as M5 and M6. The gain of the opamp is related to the minimum
by:

length

of transistor M6

which is given

1x10 ' 3
6

ID

(B.7)

g~i Vs

Even though the Early Voltage V,~ does not have an exact value, it gives a good
approach to a good value for this transistor length.

For M5

and Mrs

72

Finally, for transistors M9 and Mns we fix

gmz4

Vd, , and

calculate the transconductance

using:

2. ID
Vaoa4

(B.9)

and the sizes of transistors M9 and Mns Using:

L,

K.io

(B.10)

The final transistor sizes are given on table B.I

Table

B.l. Sizes for the

5.52

opamp transistors.

Transistor
Mn Mt
M3, M4

8'(Ian)
13.2

L(tom)

1.2 1.2

3.86
3.86
1.316
2.63

4.8 4.8

Ms, MiGMa Msc

1.2
1.2 1.2

Mz Mg, Msc
My, Mts

1.62

3.3

73

C.

Abbreviations

and Acronyms

Error

ADC:
Ave

Analog-to-Digital

Converter

DC gain
Built-in self testing
Load capacitance

BIST:
Cr. r

clkr

Clock
Digital-to Analog Converter
Desig for testability

DAC:

DFTr
DUT:

Device under test

Center frequency
Sampling frequency

for

GBP't

Gain-Bandwidth

product

HD3:

Third harmonic distortion

IC:

Integrated circuit
Intermediate
frequency

IF:
LO:

Local oscillator
Least significant bit
Operational amplifier

LSB:
Opampt

Programmable
Quality factor

Logic Array

74

R88'r
RFr
ROM:
STr
THDr
VCOr

Resolution bandwidth Radio frequency

Read-Only Memory
Sweeping time

Total harmonic distortion

Voltage controlled oscillator Voltage gain amplifier

VGA:
V.e'er

Reference voltage

75

VITA

Marcia Gisela Mendez Rivers was born in Irapuato, Guanajuato

received the

Mexico in 1972. She

B.E. degree

in electronics Irom the Universidad

in the Instituto

de Guanajuato, Mexico and

the M. S. degree

in Electronics

Nacional

de Astrofisica,

Optics y

Electronics (INAOE) in 1996 and 1998 respectively.

electrical engineering
from Texas A&M University

She received the M. S. degree in

in the Analog and Mixed Signal

Center in 2002. She is working towards her Ph. D. degree in Electronics in the Instituto
Nacional de Astrofisica, Optics y Electronics. During her studies at INAOE she worked

on clock recovery circuits. Her current

capacitors
systems.

interests

are analog

testing

and switched-

Her permanent

address

is Otono

772, Las Reynas,

Irapuato,

Guanajuato, Mexico, 33660.