You are on page 1of 72

CHAPTER 1

1.1 INTRODUCTION:
Testing and simulation are important in the system behavior. The main objective of the simulation is to verify whether the design meets the specification. On many occasion the specification itself must be tested to determine if it meets the requirements. In a large project it is often necessary to test the whole system or of it before any design can take place. This testing allows the designers to learn about system and make necessary design decisions. The main aim of the project is to monitor the reception of the desired antenna signal at the receivers using a software program which links these devices through a switching network. The antenna multi-coupler block is built up with control card (comprising of watchdog timer, 8751 controller, RS-232 interface and keyboard & display), a driver module, front-end circuit (consisting of amplifier, power Combiner, dividers) By this, the desired antenna signal is obtained from one of the four antennas at all receivers enabling many users to operate on same signal simultaneously. SPDT) and a switching circuit (consisting of power

CHAPTER 2
2.1 PROJECT DESCRIPTION:
The objective our project work is to make available the user, required signal either by means of front panel keys or by remote control operations. The antenna switching unit helps us to achieve this objective. Antenna switching unit is an intelligent micro controller equipment that can be controlled by using front panel keys or remotely. And operates between the frequency range of 20-1000MHZ.it provides optimum coupling between the three different V/UHF antenna inputs and a BITE (Built in Test Equipment) source input to nine input, U/VHF receivers. The signals from all three antenna inputs or BITE source can be routed to all of the nine outputs. Selection of antenna or BITE can be done either by front panel switches or by remote operations.

The inputs if the antenna switching units are: 1. Directional antenna. 2. Two-OMNI directional antennas. 3. Built in Test Equipment. The outputs of the antenna switching unit are 9 Receivers. Sub-systems of Antenna Switching Unit: The unit contains three functional blocks and one power supply assembly They are: 1. Front End Circuit. 2. Switching Circuit and Driver Module. 3. Control Card. 4. AC Power supply module.

2.2 SUB SYSTEM DESCRIPTION: 2.2.1 FRONT END CIRCUIT:


It has four inputs and two outputs. The inputs of this module are connected to rear panel RF inputs of the unit. Out of four inputs one is Directional antenna signals of frequency range 201000MHZ respectively. Fourth is BITE source signal of frequency range 20-1000MHZ. The three antenna input signals are applied via SPDT switches to respective filters in antenna connection mode signals pass through these switches and are filtered. The output of 20MHZ HPF is amplified and then given to one of the ports of switching circuit modules. The output of 20-100MHZ BPF and 100MHZ HPF are combined, amplified and given to one of the ports of SPDT switch. The other input to the SPDT is the BITE signal. The switch decides BITE or OMNI antenna selection. The switch output is amplified and given to remaining input of switching circuit module.

Figure 2.1 Front end circuit

2.2.2 SWITCHING CIRCUIT:


This circuit has two inputs and nine outputs. The signals that are fed to the outputs are subjected to power division 1-9 separately. The divided signals are taken to output ports through SP2T switches. Each SP2T is given the divided signals of both inputs. These switches decide the selection of one of the two signals that are fed through the module. The selection of the input signal depends on the control signals generated by the micro controller and driver module. Each output port has independent selection facility. Outputs of switches are connected to the rear panel RF output connections. Signal can be isolated from undesired signal from the port and by at least 20db.

2.2.3 CONTROL CARD:


The control card uses 87C51micro controller and generates all necessary controls for unit operation. For RS232C interface it follows SAMIP protocol. The protocol provides checksum error checking and ACK/NACK handshake. The message received from remote interface is compared with valid message codes and if it matches with the library codes, then it is processed. The TTL outputs are then connected to the input of the switching circuit. The control card performs the following functions. 1. Power ON self-test to check hard ware functionality. 2. Accepts commands from front panel switches/remote interface. 3 .Front panel LED status indication of antenna selection. 4. Resets the processor through a watch dog timer if the processor hangs due to software error.

2.2.4 DRIVER MODULE:


The function of this module is to drive RF switches of the front end and switching circuit. It consists of SWD119 and quad drivers that are specially designed for driving RF switches. These drivers take TTL signals as input and generate negative logic signals as outputs. For logic LOW input, two outputs -5v and 0v are generated and vice versa for logic HIGH. A SPDT RF switch needs one such complimentary pair controls. These are then applied to front end and switching circuits.

2.2.5 AC-DC POWER SUPPLY MODULE:


The function of this module is to segment all necessary DC voltages required for operating different modules of the unit. The input supply can be anything between 90-130 or 200-260 AC 50 HZ. The module is factory set to 230-V AC line filter removes main horn interface. The 9 pin connector of the module is connected to the front panel switch of the unit to switch ON/OFF the AC input of the module. The DC outputs of the module are taken through 25 pins D connector of module.

CHAPTER 3
3.1 CHMOS SINGLE-CHIP 8-BIT MICROCONTROLLER BY USING 87C51: 3.2 FEATURES:
1. Extended Automotive Temperature 2. Range (b40C to a125C Ambient) 3. High Performance CHMOS Process 4. Power Control Modes 5. 4Kbytes On-Chip ROM/EPROM 6. 128 x 8-bit RAM 7. 32 Programmable I/O Lines 8. Two 16-Bit Timer/Counters 9. 5 Interrupt Sources 10. Quick-Pulse EPROM Programming 11. 2-Level Program Memory Lock EPROM 12. Boolean Processor 13. Programmable Serial Port 14. TTL- and CMOS-Compatible Logic Levels 15. 64K External Program Memory Space 16. 64K External Data Memory Space 17. IDLE and POWER DOWN Modes 18. ONCE Mode Facilitates System Testing 19. Available in 12 MHz and 16 MHz Versions 20. Available in PLCC and DIP Packages

3.3 DESCRIPTION
The Philips 80C51/87C51/80C52/87C52 is a high-performance static 80C51 design fabricated with Philips high-density CMOS technology with operation from 2.7 V to 5.5 V. The 8xC51 and 8xC52 contain a 128 8 RAM and 256 8 RAM respectively, 32 I/O lines, three 16-bit counter/timers, a six-source, four-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the device is a low power static design which offers a wide range of operating frequencies down to zero. Two software selectable modes of power reductionidle mode and power-down mode are available. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. Since the design is static, the clock can be stopped without loss of user data and then the execution resumed from the point the clock was stopped.

Table 3.1 Memory Allocation

Table 3.2 87c51 Ordering information

Table 3.3 87c52 Ordering information The MCS 51 CHMOS microcontroller products are fabricated on Intel's reliable CHMOS process and are functionally compatible with the standard MCS 51 HMOS microcontroller products. This technology combines the high speed and density characteristics of HMOS with the low power attributes of CHMOS. This combination expands the effectiveness of the powerful MCS 51 microcontroller architecture and instruction set. Like the MCS 51 CHMOS microcontroller versions, the MCS 51 CHMOS microcontroller products have the following features: 4 Kbytes of EPROM/ROM (87C51/80C51BH respectively); 128 bytes of RAM; 32 I/O lines; two 16-bit timer/counters; a five-source two-level interrupt structure; a full duplex serial port; and on-chip oscillator and clock circuitry. In addition, the MCS 51 CHMOS microcontroller products exhibit low operating power, along with two software selectable modes of reduced activity for further power reduction Idle and Power Down. The Idle mode freezes the CPU while allowing the RAM MCS 51 CHMOS microcontroller products exhibit low operating power, along with two software selectable modes of reduced activity for further power reduction Idle and Power Down., timer/counters, serial port, and interrupt system to continue functioning. The Power Down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative. The 87C51 is the EPROM version of the 80C51BH. It contains 4 Kbytes of on-chip program memory that can be electrically programmed, and can be

erased by exposure to ultraviolet light. The 87C51 EPROM array uses a modified Quick-Pulse Programming algorithm, by which the entire 4 Kbytes array can be programmed in about 12 seconds.

Figure 3.1 MC 51 Microcontrollers Architectural Block Diagram

3.4 80C31BH/80C51BH/87C51 PRODUCT OPTIONS:


Intel's extended and automotive temperature range products are designed to meet the needs of those applications whose operating requirements exceed commercial standards. With the extended temperature range option, operational characteristics are guaranteed over the temperature range of b40C to a85C ambient. For the automotive temperature range option, operational characteristics are guaranteed over the temperature range of b40C to a125C ambient. The automotive and extended temperature versions of the MCS 51 microcontroller product families are available with or without burnin options as listed in Table. As shown in Figure , temperature, burn-in, and package options are identified by a one- or two-letter prefix to the part number.

Figure 3.2 MCS 51 Microcontroller Product Family Nomenclature Example: AN80C51 indicates an automotive temperature range version of the 80C51 in a PLCC package with 4 Kbytes ROM program memory.

Table 3.4 Temperature Options.

Figure 3.3 87c51 logic symbol.

2704193 2704194 Pin (PDIP) Pad (PLCC) *EPROM only **Do not connect reserved pins Figure 3.4 87c51 Pin Connections.

3.5 PIN DESCRIPTION:

VCC: Supply voltage during normal, Idle, and Power Down operations. VSS: Circuit ground. VSS1: VSS1 (EPROM PLCC only) secondary ground. Provided to reduce ground improve power supply by passing. (NOTE) This pin is not a substitute for the VSS pin (pin 22). For ROM and ROMless, pin 1 is reserved do not connect. Port 0: Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink 8 LS TTL inputs. Port 0 pins that have 1s written to them float, and in that state can be used as highimpedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external memory. In this application it uses strong internal pull-ups when emitting 1s. Port 0 also receives the code bytes during EPROM programming, and outputs the code bytes during program verification. External pull-ups are required during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL, on the datasheet) because of the internal pull-ups. Port 1 also receives the low-order address bytes during EPROM programming and program verification. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. inputs, Port 2 pins that are externally being pulled low will source current (IIL, on the data sheet) because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external Program memory and during accesses to external Data Memory that use 16-bit address (MOVX @DPTR). In this application it uses strong internal pull-ups when emitting 1s.During accesses to external Data Memory that use 8-bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives some control signals and the high-order address bits during EPROM programming and program verification. bounce and

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL, on the datasheet) because of the pull-ups. Port 3 also serves the functions of various special features of the MCS 51 microcontroller family, as listed below:

Table 3.5 port 3 description Port 3 also receives some control signals for EPROM programming and program verification. RESET: Reset input. A logic high on this pin for two machine cycles while the oscillator is running resets the device. An internal pull down resistor permits a power-on reset to be generated using only an external capacitor to VCC.

ALE/PROG (EPROM Only): Address Latch Enable output signal for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG) during EPROM programming. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory.

PSEN: Program Store Enable is the Read strobe to External Program Memory. When the 87C51/80C51BH is executing from Internal Program Memory, PSEN is inactive (high). When the device is executing code from External Program Memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to External Data Memory. EA/VPP: External Access enable. EA must be strapped to VSS in order to enable the 87C51/80C51BH to fetch code from External Program Memory locations starting at 0000H up to 0FFFFH. [Note, however, that if either of the Lock Bits is programmed, the logic level at EA is internally latched during reset.] (EPROM only.) EA must be strapped to VCC for internal program execution. VPP (EPROM Only): This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming .

2704195 Figure 3.5. Using the On-Chip Oscillator

Figure 3.6 External Oscillator

Table 3.6 Pin Description

Table 3.7 Special Function Registers

NOTE:

Unused register bits that are not defined should not be set by the users program. If violated, the device could function incorrectly. * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. Reserved bits. 1. Reset value depends on reset source. 2. LPEP Low Power EPROM operation (OTP/EPROM only)

3.6 OSCILLATOR CHARACTERISTICS:


XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 4. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected, as shown in Figure 5. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the Datasheet must be observed.

3.6.1 IDLE MODE:


In Idle Mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the Special Functions Registers remain unchanged during this mode. The Idle Mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when Idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

3.6.2 POWER DOWN MODE:


In the Power Down mode the oscillator is stopped, and the instruction that invokes Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated. The only exit from Power Down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before VCC is restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize.

Table 3.8. Status of the External Pins during Idle and Power Down.

3.6.3 DESIGN CONSIDERATIONS:


At power on, the voltage on VCC and RST must come up at the same time for a proper start-up. Before entering the Power Down mode the contents of the Carry Bit and B.7 must be equal. When the Idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. Onchip hardware inhibits access to internal RAM in this event, but access to the port pins in not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. An external oscillator may encounter as much as a 100 pF load at XTAL1 when it starts up. This is due to interaction between the amplifier and its feedback capacitance. Once the

external signal meets the VIL and VIH specifications the capacitance will not exceed 20 pF. For EPROM versions exposure to light when the device is in operation may cause logic errors. For this reason, it is suggested that an opaque label be placed over the window when the die is exposed to ambient light.

3.6.4 PROGRAM MEMORY LOCK (EPROM Only):


The 87C51 contains two program memory lock schemes: Encrypted Verify and Lock Bits. Encrypted Verify: The 87C51 implements a 32- byte EPROM array that can be programmed by the customer, and which can then be used to encrypt the program code bytes during EPROM verification. The EPROM verification procedure is performed as usual, except that each code byte comes out logically X-NORed with one of the 32 key bytes. The key bytes are gone through in sequence. Therefore, to read the ROM code, one has to know the 32 key bytes in their proper sequence. Lock Bits: Also on the chip are two Lock Bits which can be left un programmed (U) or can be programmed (P) to obtain the following additional features: When Lock Bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly.

Table 3.9 Lock Bits

ONCE MODE:
The ONCE (``on-circuit emulation'') mode facilitates testing and debugging of systems using the 87C51 without the 87C51 having to be removed from the circuit. The ONCE mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 87C51 is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when a normal reset is applied.

Programmable Clock-Out:

A 50% duty cycle clock can be programmed to come out on P1.0. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed: 1. To input the external clock for Timer/Counter 2, or 2. To output a 50% duty cycle clock ranging from 61 Hz to 4 MHz at a 16 MHz operating frequency. To configure the Timer/Counter 2 as a clock generator, bit C/T2 (in T2CON) must be cleared and bit T20E in T2MOD must be set. Bit TR2 (T2CON.2) also must be set to start the timer. The ClockOut frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L) as shown in this

Where:

(RCAP2H,RCAP2L) = the content of RCAP2H and RCAP2L taken as a 16-bit

unsigned integer. In the Clock-Out mode Timer 2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer 2 as a baud rate generator and a clock generator simultaneously. Note, however, that the baud-rate and the Clock-Out frequency will be the same.

TIMER 2 OPERATION Timer 2:


Timer 2 is a 16-bit Timer/Counter which can operate as either an event timer or an event counter, as selected by C/T2* in the special function register T2CON (see Figure 1). Timer 2 has three operating modes: Capture, Auto-reload (up or down counting) ,and Baud Rate Generator, which are selected by bits in the T2CON as shown in Table 3.

Capture Mode:
In the capture mode there are two options which are selected by bit EXEN2 in T2CON. If EXEN2=0, then timer 2 is a 16-bit timer or counter (as selected by C/T2* in T2CON) which, upon overflowing sets bit TF2, the timer 2 overflow bit. This bit can be used to generate an interrupt (by enabling the Timer 2 interrupt bit in the IE register). If EXEN2= 1, Timer 2 operates as described above, but with the added feature that a 1- to -0 transition at external input T2EX causes the current value in the Timer 2 registers, TL2 and TH2, to be captured into registers RCAP2L and RCAP2H, respectively. In addition, the transition at T2EX causes bit EXF2 in 2CON to be set, and EXF2 like TF2 can generate an interrupt which vectors to the same location as Timer 2 overflow interrupt. he Timer 2 interrupt service routine can interrogate TF2 and EXF2 o determine which event caused the interrupt). The capture mode is illustrated in Figure 2 (There is no reload value for TL2 and TH2 in

this mode. Even when a capture event occurs from T2EX, the counter keeps on counting T2EX pin transitions or osc/12 pulses.).

Auto-Reload Mode (Up or Down Counter):


In the 16-bit auto-reload mode, Timer 2 can be configured (as either a timer or counter (C/T2* in T2CON)) then programmed to count up or down. The counting direction is determined by bit DCEN (Down Counter Enable) which is located in the T2MOD register (see Figure 3). When reset is applied the DCEN=0 which means Timer 2 will default to counting up. If DCEN bit is set, Timer 2 can count up or down depending on the value of the T2EX pin. Figure 4 shows Timer 2 which will count up automatically since DCEN=0. In this mode there are two options selected by bit EXEN2 in T2CON register. If EXEN2=0, then Timer 2 counts up to 0FFFFH and sets the TF2 (Overflow Flag) bit upon overflow. This causes the Timer 2 registers to be reloaded with the 16-bit value in RCAP2L and RCAP2H. The values in RCAP2L and RCAP2H are preset by software means. If EXEN2=1, then a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at input T2EX. This transition also sets the EXF2 bit. The Timer 2 interrupt, if enabled, can be generated when either TF2 or EXF2 are 1. In Figure 5 DCEN=1 which enables Timer 2 to count up or down. This mode allows pin T2EX to control the direction of count. When a logic 1 is applied at pin T2EX Timer 2 will count up. Timer 2 will overflow at 0FFFFH and set the TF2 flag, which can then generate an interrupt, if the interrupt is enabled. This timer overflow also causes the 16bit value in RCAP2L and RCAP2H to be reloaded into the timer registers TL2 and TH2. When logic 0 is applied at pin T2EX this causes Timer 2 to count down. The timer will underflow when TL2 and TH2 become equal to he value stored in RCAP2L and RCAP2H. Timer 2 underflow sets he TF2 flag and causes 0FFFFH to be reloaded into the timer registers TL2 and TH2. he external flag EXF2 toggles when Timer 2 underflows or overflows. This EXF2 bit can be used as a 17th bit of resolution if needed. The EXF2 flag does not generate an interrupt in this mode of operation.

Table 3.10 Timer 2 Operating Modes

EXTERNAL PROGRAM MEMORY READ CYCLE:

Figure 3.7 EXTERNAL PROGRAM MEMORY READ CYCLE

EXTERNAL DATA MEMORY READ CYCLE:

Figure 3.8 EXTERNAL DATA MEMORY READ CYCLE

EXTERNAL DATA MEMORY WRITE CYCLE:

Figure 3.9EXTERNAL DATA MEMORY WRITE CYCLE

EPROM PROGRAMMING AND VERIFICATION WAVEFORMS:

Figure 3.10 EPROM PROGRAMMING AND VERIFICATION WAVEFORMS

3.7 DATASHEET REVISION SUMMARY:


The following are the key differences between this datasheet and the -006 version: 1. The ``preliminary'' status was removed and replaced with production status (no label). 2. Trademark was updated. The following are the key differences between the -005 and the -006 version of the datasheet: 1. Preliminary notice added to Title page. 2. Figure 3 Pin Connections the NC** pins are now Reserved** pins. 3. Figure 3 Pin Connections RST pin is now RESET pin. 4. RST pin description is now RESET pin description. 5. Figure 4 the capacitor values have been removed. 6. CERDIP part reference in the D.C. Characteristics section has been removed. 7. ICC Max characteristics have been corrected to reflect test program conditions.

8. TAVIV and TRLDV formulas changed to correlate 12 MHz timings. The following are the key differences between the -004 and the -005 version of this datasheet: 1. Removed references to burn-in options in Table 1 and added explanation of burn-in offered. Removed references to commercial temperatures. 2. Deleted reference to ``b1'' designation 16 MHz. 3. Differentiated VCC for ROM/ROMless and EPROM. The following are the key differences between the -002 and the -003 version of this datasheet: 1. Changed the title to 80C31BH/80C51BH/87C51 CHMOS Single-Chip 8-Bit 2. Added the pin count for each package version in Figure 2. 3. Removed references to burn-in options in Table 1. 4. Added external oscillator start-up design considerations. The following are the key differences between the -002 and the -001 version of the 80C51BH datasheet: 1. Maximum IOL per I/O pin added. 2. Note 7 on Maximum Current Specifications added to DC Characters tics. 3. Datasheet Revision Summary added Microcontroller.

CHAPTER 4
4.1 DRIVER MODULE AND SWITCHING CIRCUIT: 4.1.1 Driver module:
The function of this module is to drive RF switches of the front end and switching circuit. it consist of SWD119 quad drivers that are designed for driving RF switches. The drivers take TTL signals as inputs and generative negative logic low inputs, two outputs. For logic low inputs, two output -5v and 0v are generated and vice versa for logic high. An SPDT RF switch needs on such complimentary pair controls. These controls are then applied to front end switching circuits. The driver module receive TTL inputs from the micro controller and then generate a pair of negative logic signals that are used as the controller inputs for the switching.

4.1.2 SWD 119(Quad Driver):


Thus works a driver for GaAs FET switches in attenuators.

Features:
1. High speed CMOS technology 2. Quad channel 3. Positive voltage control 4. Low power dissipation

4.1.3 DESCRIPTION:
The SWD119 is a quad channel driver used to translate TTL inputs to gate voltages for GaAs FET microwave switches High speed analog CMOS technology is utilized to achieve low power dissipation at moderate to high speeds encompassing most Microwave switching application. For an input C the output are^, B, for logic low input two outputs -5v and 0v are generated and vice versa for logic high.

Figure 4.1 Quad Channel

TRUTH TABLE:
(1=-4.5v, 0=0v) C 0 1 A 1 0 B 0 1

Table 4.1 Quad Channel

4.2 SWITCHING CIRCUIT:


The circuit has two inputs and nine outputs the signals that are fed to the Inputs are subjected to 1-9 power division separately. The divided signals are taken to output ports through SPT switches. Each SPDT is given the divided signals of both inputs. These switches decide the selection of one of the two signals that are fed to the Module the selection of the input signal depends on the control signals generated By the micro controller and driver module. Each port has independent selection facility. Outputs of the switches are connected to the rare panel RF output connectors. Signals can be isolated from undesired signal from other ports by at least 20dB. DS 323 (Three way power divider): Feature: Frequency range : 25-1000MHZ

Insertion loss Isolation VSWR Impedance Max power rating

: 0.4db :35db :1.2:1 :50ohm :0.05watt

Figure 4.2 Switch

DS 323 IS A10-pin IC with pin 3 input & pin 6,8,10 are out puts the power available on the 3outputs equal

4.2.1 SWD 338(SPDT Switches):


It is SPDT Switch with 8-pins There are 2RF inputs(RF1,RF2) & 1-output (RF c)

Figure 4.3 Switch The Switches takes 2-control inputs A,B

TRUTH TABLE:

Table 4.2 Switch

CHAPTER 5
5.1 TESTING: 5.1.1 Test Equipment used:

The following is the test equipment used in the performance evolution / trouble shooting and maintenance routine of the unit

Instrument Digital volume

specification Range: 0-400v AC & DC, 05 amp Display:9 digits

recommended Philips PM D718 RMS multi meter or equip. valiant

Oscilloscope

Sensitivity: 5mv/div i/p impudence:50 o/p 104 to 0db

Hp or equivalent

Spectrum analyze

Frequency 10-1000 MHz i/p impudence:50 sensitivity 105 dbm 10khz

Hp

Table 5.1 Test Equipment

5.2 Testing procedure:


In case testing is required after fault diagnosis and repair the following test is done. Gain and frequency coverage test

Gain and frequency coverage test:


Specification: 7+ /-3 dB frequency range 20-600MHZ 3+/-3 dB For frequency range 600-1000 MHZ

Test procedure:
1. The output of the signal generator is connected to one of the input of the unit under test and any of the output of the unit unmask test is connected to spectrum analyze 2. Set the signal generator and spectrum as: Signal generator settings: 1. Frequency 2. RF level 3. Modulation Spectrum analyzes setting 1. Frequency 2. RF level 3. Span Test frequency 0dBM 5-10 M Hz Test Frequency -40 dBM RF On off

3. Note the output level on the spectrum analyzes the output level should be

-37dV + / -3 dbm for range 20-600MHZ

Flow Chart

CONCLUSION:
This project on micro controller based antenna switching unit Thus allows us to access different signals from various antennas at various receivers. Our software program provides the required link between micro controllers 87c51 the switching network. A signal can thus be made available to many users by front panel or by remote control operation.

BIBLOGRAPHY www.google.com www.ieee.com www.wikepedia.com

Programming and Customizing The AVR Microcontroller

by Dhananjay V. Gadre 8051 Micro Controller Architecture by Ahalya Advanced Microprocessor Interfacing by A.K.Rai

You might also like