National Institute of Applied Sciences Department of Electrical & Computer Engineering

MicroWind
An Introduction to micro-electronics for Windows 95

Version 1.0

Etienne Sicard

Unpacking Your package for MICROWIND contains the following items: The User's Manual (the present book) The diskettes containing the software, running in Windows 95 environment

The User's manual contains information on how to operate the program and how to execute the commands. It also contains explanations for a set of 30 micro-electronics projects and suggested activities. System Requirements Your computer system should have a PC configuration including the following features: A minimum memory of 8 Mb 640x480, 256 colors (a 800x600 resolution is recommended) Windows 95/NT

How to Install the Software The installation of the software on the hard-disk is recommended. To install the programs on the hard-disk, perform the following step-by-step procedure: Select Start -> Execute command under Windows 95, Insert the diskette into drive a: Type a :install and press This command creates a directory named microwind on the hard-disk. Consequently all the files of the diskette will be copied into this microwind directory.

About the Single License The single license authorizes you to use one copy of the software and includes one copy of the documentation. You may use the copy of the software and the documentation on no more than one personal computer at a time. You are allowed to make one archival copy of the software for your personal use. You may not transfer, sell, or distribute the software. You cannot give copies of the software or of the documentation to anyone. ISBN 2-87649-017-X Edited by INSA Toulouse, Av de Rangueil 31077 Toulouse Cedex 4 - FRANCE 2

About the Site License The site license authorizes you to use ten copies of the software and includes one copy of the documentation. For each computer when operating the program simultaneously one more than one computer an authorized copy of the program is required for each of them You can make archival copies of the software. You may not transfer, sell, or distribute the software. You cannot give copies of the software or the documentation to any person.

About the author ETIENNE SICARD was born in Paris, France, in June 1961. He received a B.S degree in 1984 and a PhD in Electrical Engineering in 1987 both from the University of Toulouse. He was granted a Monbusho scholarship and stayed 18 months at the University of Osaka, Japan. Previously a professor of electronics in the department of physics, at the University of Balearic Islands, Spain, E. Sicard is currently an associate professor at the INSA Electronic Engineering School of Toulouse. His research interests include several aspects of CAD tools for the design of integrated circuits including crosstalk fault analysis, electromagnetic compatibility, the design of micro-systems and of educational software. Copyright 1998 Etienne Sicard INSA-DGEI Av de Rangueil 31077 TOULOUSE Cedex 4, FRANCE Tel : +33.561.55.98.42 Fax: +33.561.55.98.00 e-mail: etienne@dge.insa-tlse.fr web information : http ://www.insa-tlse.fr/~etienne
o o Windows 95 is a trade mark of MICROSOFT CORPORATION. IBM PC is a trademark of INTERNATIONAL BUSINESS MACHINE CORP.

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Contents

Software Installation Introduction License 1. Tutorial on MOS devices The Mos Model 1 The MOS Model 3 Tutorial on Level 3 Parameters 2. Design of a CMOS Inverter Simulation Parametric Analysis Basic Gates Compiling the NAND Gate 3-Input OR The XOR gate Complex Gates Arithmetic Gates Half-Adder Full Adder Comparator Latches & Memories RS Latch D Latch RAM Memory RAM 4x4 bit

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6. Other Projects 4 Bit Adder Multiplier 2x2 bits Two-Bit Counter Wide Range Amplifier Interface with PSPICE Analog/Digital Converter Digital/Analog converter Input/Output Pad, Pad Ring Design Rules Program Operation List of Commands Quick Reference Sheet Instructor's Guide References 62 62 64 66 68 70 71 74 76 78 82 92 93 116 121 123

7. 8. 9. 10. 11. 12.

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Introduction

The present book is a guide to using the Microwind educational software on a PC computer. The MICROWIND program allows the student to design and simulate an integrated circuit. The package itself contains a library of common logic and analog ICs to view and simulate. MICROWIND includes all the commands for a mask editor as well as new original tools never gathered before in a single module. You can gain access to Circuit Simulation by pressing one single key. The electric extraction of your circuit is automatically performed and the analog simulator produces voltage and current curves immediately. A specific command displays the characteristics of pMOS and nMOS, where the size of the device and the process parameters can be very easily changed. Altering the MOS model parameters and, then, seeing the effects on the Vds and Ids curves constitutes a good interactive tutorial on devices. The Process Simulator shows the layout in a vertical perspective, as when fabrication has been completed. This feature is a significant aid to supplement the descriptions of fabrication found in most textbooks. The Logic Cell Compiler is a particularly sophisticated tool enabling the automatic design of a CMOS circuit corresponding to your logic description in VERILOG. The DSCH software, which is a user-friendly schematic editor and a logic simulator presented in a companion manual, is used to generate this Verilog description. The cell is created in compliance with the environment, design rules and fabrication specifications. A set of CMOS processes ranging from 1.2m down to state-of-the-art 0.25m are proposed. 6

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The chapters of this manual have been summarized below. Chapters One through Six present a tutorial on micro-electronics and IC design. Chapter One is dedicated to the simulation of the single MOS device, with details on the device modelling. Chapter Two presents the CMOS Inverter, Chapter Three the basic logic gates, Chapter Four the arithmetic functions. The latches and memories are detailed in Chapter Five. As for Chapter, it deals with various projects such as a counter, a multiplier, a CMOS analog amplifier, the Analog/Digital and Digital/Analog converter principles and a RAM memory. The detailed explanation of the design rules is in Chapter Seven. The program operation and the details of all commands are given in Chapter Eight and Nine. A Quick reference sheet, the complete list of files and the instructor guide are reported at the end of the present manual. The major updates of MICROWIND compared to the DOS version concern the support of advanced technologies, improvements in editing commands, the possibility to handle very complex designs and the VERILOG compilation from high-level description into layout. The new software, DSCH, concerning logic editing and simulation is now part of the package.

License
Please note that MICROWIND is a licensed software, that has been licensed in France by Langage et Informatique Inc, Toulouse, and by INSA in all other countries. The single license authorizes you to use one copy of the software and includes one copy of the documentation. The site license authorizes you to use ten copies of the software and includes one copy of the documentation. An authorized copy of the program is required for each one of the computer operating the program simultaneously. You may not transfer, sell, or distribute the software. MICROWIND is recommended by EURO-PRACTICE, the American Society for Engineering Education (ASEE), and supported by the National Comity for MicroElectronics Education (CNFM).

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1. Tutorial on MOS Devices

To use the MICROWIND program use the following procedure: Go to the directory in which the software has been copied (The default directory is MICROWIND) Double-click on the MicroWind icon

The MICROWIND display window is shown in Figure 1. It includes four main windows: the main menu, the layout display window, the icon menu and the layer palette. The cursor appears in the middle of the layout window and is controlled by using the mouse. The layout window features a grid that represents the current scale of the drawing, scaled in lambda () units and in micron. The lambda unit is fixed to half of the minimum available lithography of the technology. The default technology is a 0.8 m technology, consequently lambda is 0.4 m.

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Fig. 1. The MICROWIND window as it appears at the initialization stage..

The MOS device

The MOS symbols are reported below. The n-channel MOS is built using polysilicon as the gate material and N+ diffusion to build the source and drain. The p-channel MOS is built using polysilicon as the gate material and P+ diffusion to build the source and drain.

nMOS

pMOS

Manual Design
By using the following procedure, you can create a manual design of the n-channel MOS. The default icon is the drawing icon shown above. It permits box editing. The display window is empty. The palette is located in the lower right corner of the screen. A red color indicates the current layer. Initially the selected layer in the palette is polysilicon. The two first steps are illustrated in Figure 2. 9

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Fix the first corner of the box with the mouse. While keeping the mouse button pressed, move the mouse to the opposite corner of the box.

Release the button. This creates a box in polysilicon layer as shown in Figure 2. The box width should not be inferior to 2 , which is the minimum width of the polysilicon box.

Fig. 2. Creating a polysilicon box.

Change the current layer into N+ diffusion by a click on the palette of the Diffusion N+ button. Make sure that the red layer is now the N+ Diffusion. Draw a n-diffusion box at the bottom of the drawing as in Figure 3. N-diffusion boxes are represented in green. The intersection between diffusion and polysilicon creates the channel of the nMOS device.

Fig. 3. Creating the N-channel MOS transistor

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Process Simulation

Click on this icon to access process simulation. The cross-section is given by a click of the mouse at the first point and the release of the mouse at the second point. In the example below (Figure 4), three nodes appear in the cross-section of the n-channel MOS device: the gate (red), the left diffusion called source (green) and the right diffusion called drain (green), over a substrate (gray). The gate is isolated by a thin oxide called the gate oxide. Various steps of oxidation have lead to a thick oxide on the top of the gate.

Fig. 4. The cross-section of the nMOS devices.

The physical properties of the source and of the drain are exactly the same. Theoretically, the source is the origin of channel impurities. In the case of this nMOS device, the channel impurities are the electrons. Therefore, the source is the diffusion area with the lowest voltage. The polysilicon gate floats over the channel, and splits the diffusion into 2 zones, the source and the drain. The gate controls the current flow from the drain to the source, both ways. A high voltage on the gate attracts electrons below the gate, creates an electron channel and enables current to flow. A low voltage disables the channel.

Mos Characteristics

Click on the MOS characteristics icon. The screen shown in Figure 5 appears. It represents the Id/Vd simulation of the nMOS device.

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Fig. 5. N-Channel MOS characteristics.

The MOS size (width and length of the channel situated at the intersection of the polysilicon gate and the diffusion) has a strong influence on the value of the current. In Figure 5, the MOS width is 12.8m and the length is 1.2m. Click on OK to return to the editor. A high gate voltage (Vg =5.0) corresponds to the highest Id/Vd curve. For Vg=0, no current flows. The maximum current is obtained for Vg=5.0V, Vd=5.0V, with Vs=0.0. The MOS parameters correspond to SPICE Level 3. You can alter the value of the parameters, or even access to Level 1. You may also skip to PMOS. You may as well add some measurements to fit the simulation. Finally, you can simulate devices with other sizes in the proposed list.

Add Properties for Simulation

Properties must be added to the layout to activate the MOS device. The most convenient way to operate the MOS is to apply a clock to the gate, another to the source and to observe the drain. The summary of available properties is reported below.

VDD property VSS property Clock property Node visible Pulse property

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Apply a clock to the drain. Click on the Clock icon, click on the left diffusion. The Clock menu appears (See below). Change the name into drain and click on OK. A default clock with 3 ns period is generated. The Clock property is sent to the node and appears at the right hand side of the desired location with the name drain .

Fig. 6. The clock menu.

Apply a clock to the gate. Click on the Clock icon and then, click on the polysilicon gate. The clock menu appears again. Change the name into gate and click on OK to apply a clock with 6 ns period.

Watch the output: Click on the Visible icon and then, click on the right diffusion. The window below appears. Click OK. The Visible property is then sent to the node. The associated text s1 is in italic. The wave form of this node will appear at the next simulation.

Fig. 7. The visible node menu.

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Save before Simulation

Click on File in the main menu. Move the cursor to Save as ... and click on it. A new window appears, into which you enter the design name. Type, for example, myMos. Use the keyboard for this and press . Then click on OK. After a confirmation question, the design is saved under that filename.

IMPORTANT : Always save BEFORE any simulation !

Analog Simulation
Click on Simulate on the main menu. The timing diagrams of the inverter appear, as shown in Figure 8.

Fig. 8. Analog simulation of the MOS device.

When the gate is at zero, no channel exists so the node s1 is disconnected from the drain. When the gate is on, the source copies the drain. It can be observed that the nMOS device drives well at zero but at the high voltage. The final value is 4.2V, that is VDD minus the threshold voltage. Click on More in order to perform more simulations. Click on Stop to return to the editor. 14

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The MOS Model 1

For the evaluation of the current Ids between the drain and the source as a function of Vd,Vg and Vs, you may use the old but nevertheless simple MODEL 1 described below. The model 1 is accurate for channel length of more than 10m. CUT-OFF MODE. Vgs<0 Ids = 0

LINEAR MODE. Vds<Vgs-Vt, W Vds2 Ids = KP L ((Vgs-Vt)Vds- 2 )) SATURATED MODE. Vds>Vgs-Vt, W Ids = KP/2 L (Vgs-Vt)2

In those formulas, W is the MOS channel width, L is the MOS channel length. VTO is the threshold voltage. The parameter KP is evaluated by the following formula: n is the mobility of electrons, p the mobility of holes, and TOX the gate oxide thickness. KP(n) = n 0 S / TOX KP(p) = p 0 S / TOX where (0.8m technology) n = 510 V.cm-2 r (SiO2)= 3.9 TOX = 150 nm p = 270 V.cm-2 0 = 8.85 e -14 Farad/cm

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When dealing with sub-micron technology, the model 1 is 200-300% higher than the measurements, as shown above for the prediction of a 20x0.8m n-channel MOS with KP computed according to 0.8m oxide thickness.

The MOS Model 3

For the evaluation of the current Ids as a function of Vd,Vg and Vs between Drain and Source, we commonly use the following equations, close from the SPICE model 3 formulations. The formulations are derived from the model 1 and take into account a set of physical limitations in a semi-empirical way. CUT-OFF MODE. Vgs<0 Ids = 0 NORMAL MODE. Vgs>Von Ids = Keff with von = 1.2 vth vth = VTO + GAMMA( PHI vb vde = min ( vds, vdsat) vdsat = vc + vsat vsat = vgs-vth LEFF vc = VMAX 0.06 LEFF = L - 2 LD

Vde W (1+KAPPA vds) Vde ((Vgs-vth))) LEFF 2

PHI )

vc2 vsat 2

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Keff =

KP (1+ THETA(vgs - vth))

SUB-THRESHOLD MODE. Vgs<Von vds is replaced by von in the above equations. Ids = Ids(von,vds) e

q(vgs - von) nkT

In those formulas, W corresponds to the MOS channel width, L to the MOS channel length and VTO to the threshold voltage. The KP parameter is evaluated by the following formula in which : n is the mobility of electrons, p the mobility of holes, and TOX the gate oxide thickness. KP(n) = n 0 S / TOX KP(p) = p 0 S / TOX where (0.8 technology) n = 510 V.cm-2 r (SiO2)= 3.9 TOX = 150 nm n=2 k = 1.381e-23 T = 300 K q = 1.6e-19 Temperature effects : n = n0 (T-300) e(-1.5) p = p0 (T-300) e(-1.5) vt = vt0-0.002(T-300) p = 270 V.cm-2 0 = 8.85 e -14 Farad/cm

Tutorial on SPICE Level 3 Parameters

Click on the MOS characteristics icon. The screen displays the Id/Vd simulation of the nMOS device. You can change the MOS parameter values directly on the screen and see 17

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the effect on the MOS simulation. Notice that KP includes the values of TOX (thin-oxide thickness) and of U0 (the carrier mobility) as described in the previous chapter. Fitting the model with measurements Click on Add Measurement. The program scans the current directory and displays the list of measurement files with and appendix called ".MES". Choose Es207_n20x20.MES. It corresponds to the measurements performed on a real MOS device with size W=20 m, L=20 m, fabricated by ATMEL ES2 in their 0.8 m technology (ES208.RUL). You should always start with measurements for a device with a very large width and length. The second order effects are reduced in such devices. The measured data is added to the drawing, as shown in the Figure 9.

Fig. 9. The measured data file is added to the simulation (Es207_20x20.MES file).

The principles for fitting the simulation with the measurements are described below. Click on Id vs. Vg. The curve shown in Figure 10 is used to fit VTO and Decrease VTO down to 0.7 in order to shift the curves to the right, and increase GAMMA up to 0.65 to adjust the set of curves. The measurement step for vbulk is 1.0V while the simulation step is 0.5 V in the figure.

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Fig. 10. The Id/Vg to find VTO and fit GAMMA (Es207_20x20.MES file).

Click on Id vs. Vd. Increase THETA to bend the curve in order to find a compromise. Although not satisfactory, the result is quite correct.

Fig. 10. Fitting the model with the measured data file (Es207_20x20.MES file).

Now load a new measurement such as Es207_N20x0,8.mes. Click on Id vs. Vg Increase LD in order to fit the slope in the Id/Vg curve.

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Fig. 11. Small channel MOS measurement (Es207_20x0,8.MES file).

Click on Id vs. Vd. Adjust VMAX to fit the transition point between the linear and the saturated region according to the measurement. Next, adjust KAPPA to adapt the positive slope in the saturated region.

Fig. 11. Small channel MOS measurement (Es207_20x0,8.MES file).

Click on Id(log)/Vg. Verify that the slope is correct in sub-threshold mode. If not you can adjust the slope using NSS. Notice that the measurement limit is in the order of the nA. This is why no reliable data is available below 10-9 A (Figure 12).

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Fig. 12. Small channel MOS measurement in the sub-threshold region (Es207_20x0,8.MES file).

The PMOS Transistor

The p-channel transistor simulation features the same functions as the n-channel device. Click on pMOS in the menu. The software switches to the p-channel MOS simulation, as shown in Figure 13. Note that the pMOS gives only half of the maximum current given by the nMOS with the same device size.

Fig. 13. Simulation of the p-channel MOS.

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3. Design of a CMOS Inverter

This chapter is dedicated to the layout design of a simple CMOS inverter. You will learn how to draw manually all the elements of the cell (i.e. boxes, layers, text, and properties). You will use the design tools quite intensively.

The CMOS Inverter

The CMOS inverter includes 2 transistors. One is a n-channel transistor, the other a pchannel transistor. The device symbols are reported below. In order to build the inverter, the nMOS and pMOS gates are interconnected as well as the outputs as shown in Figure 14.

nMOS

pMOS Device symbols

NPN

Vdd

Vss (Ground)

Input

Output

Input

Output

Inverter Symbol

InverterPrinciples

Fig. 14. The schematic diagram of the CMOS inverter with one nMOS at the bottom and one pMOS at the top.

Manual Design
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Using the following procedure, you can create a manual design of the inverter. The default icon is the drawing icon shown above. It allows box editing. The display window is empty. The palette is located in the lower right corner of the screen. A red color indicates the current layer. Initially the selected layer in the palette is polysilicon. The two first steps are illustrated in Figure 15. Fix the first corner of the box with the mouse. While keeping the mouse button pressed, move the mouse. to the opposite corner of the box. Release the button. This creates a box in polysilicon layer as shown in Figure 24. The box width should not be lower than 2 , which is the minimum width of the polysilicon box.

Fig. 15. Creating a polysilicon box.

Now, draw two more boxes as in Figure 16. Try to keep close to the shape and size of the example.

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Fig. 16. Creating three polysilicon boxes.

Change the current layer into N+ diffusion by a click in the palette on the Diffusion N+ button. Be sure that the red layer is now the N+ Diffusion. Draw a n-diffusion box at the bottom of the drawing as in Figure 17. N-diffusion boxes are represented in green. The intersection between the N+ diffusion and the polysilicon creates the channel of the MOS device.

Fig. 17. Creating the N-channel and P-Channel devices.

Change the current layer into P+ diffusion by a click in the palette on the button P+ Diffusion. Draw a p-diffusion box at the top of the drawing as in Figure 29. N-diffusion boxes are represented in green. The intersection between the P+ diffusion and the polysilicon creates the channel of the pMOS device. 24

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Change the current layer into N Well by a click on the corresponding button in the palette. Draw a well all around the p+ diffusion, as in Figure 18. Use keyboard arrows (up key) to view the upper part of the layout.

Fig. 18. Creating the well for the P-Channel Device.

Process Simulation

Click on this icon to access process simulation . The cross-section is given by a click on the mouse at the first point and the release of the mouse at the second point. In the example below (Figure 19), the cross-section of the n-channel MOS device appears on the left, and the cross-section of the p-channel MOS device on the right.

Fig. 19. The cross-section of the nMOS and pMOS devices.

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Contacts and Metal Interconnects

The diffusion areas must be joined using a metal layer. The metal layer is isolated from the diffusions by a thick silicon dioxide SiO2 layer. The contact layer is used to drill a hole in the oxide in order to join the metal and the diffusions. You could draw the contact box manually by selecting the layer Contact and drawing a 2 x 2 box. A fast solution is to use the predefined macros at the top of the palette. Various contacts built according to design rules are proposed.
Contact diffn/metal Contact poly/metal Contact diffp/metal Contact via/metal

Fig. 20. The contact macros.

Choose the diffn/metal contact icon in the palette. The contact outline will appear. Fix the contact inside the n+ diffusion area. Click again on the diffn/metal contact and place it at the upper corner of the n-well box. This contact is used to polarize the well at VDD. The diffusion N+ in the nwell makes an ohmic contact and prepares for the VDD polarization using metal layers. Finally, click on the diffp/metal icon and fix the contact inside the p+ diffusion area. Select the metal layer in the palette. Draw a metal bridge between the n+ and p+ contacts. The CMOS inverter layout is almost completed (Figure 21). The remaining task is to define where the supply, the ground, the input and the output are.

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Fig. 21. The metal bridge and the inverter are completed.

Add Properties for Simulation

Properties must be added to the layout to fix the ground, the supply, the input and the outputs. The summary of available properties is reported below.

VDD property VSS property Clock property Node visible Pulse property

For the inverter example, we must assign the upper p-diffusion to a VDD power supply, and the lower n-diffusion box to a VSS ground voltage. We also need to specify a clock as the input for the IN node and have a look at the output OUT.

Stuck at Vdd: Click on the Vdd icon and click on the upper p-diffusion box. The Vdd property is sent to the node. 27

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Also click in the N-Well region inside which the pMOS is located. The NWell must always be at VDD voltage to keep the pMOS junctions inverted. Hold at Vss: Click on the Vss icon, click on the lower n-diffusion box. The Vss property is sent to the node. Apply a clock to node IN: Click on the Clock icon and on the polysilicon gate. The Clock menu appears (See below). Click on OK. A default clock with 3 ns period is generated. The Clock property is sent to the node and appears at the right hand side of the desired location with the name clock1 .

Fig. 22. The clock menu.

Watch the output: Click on the Visible icon and then, on the metal bridge. The window below appears. Click OK. The Visible property is sent to the node. The associated text s1 is in italic. The chronogram of this node will appear in the next simulation.

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Analog Simulation
IMPORTANT : Always save BEFORE simulation ! Click on File in the main menu. Move the cursor to Save as ... and click on it. A new window appears, into which you are to enter the design name. Type, for example, MYINV. Use the keyboard for this and press . Then click on OK. After a confirmation question, the design is saved under that filename.

Click on Simulate in the main menu. The timing diagrams of the inverter appear, as shown in Figure 23. Click on More in order to perform more simulations. Click on Stop to return to the editor. The gate delay is computed at VDD/2, that is 2.5 V, between the signal selected in the Start Node list and the signal selected with the Stop Node list.

Fig. 23. Analog simulation of the CMOS inverter. The output has the opposite value of the clock input.

Click on Voltage & Currents to see both currents and voltages (Figure 24). The current peaks can be seen in the upper window. All voltages are reported in the lower window. The current scale can be adjusted using a predefined list of values. Some current is consumed at VDD supply, mainly when the output of the inverter rises to VDD. Some current is consumed at VSS, mainly when the output goes down to zero.

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Click on Voltage vs. Voltage to see the DC transfer characteristics of the inverter (Figure 24-bottom). The commutation point of the inverter Vc is the input voltage for which the output is close to VDD/2. In the case of Figure 24, Vc is around 1.8 V. Click on Back to Editor to return to the editor.

Fig. 24. Current consumption of the CMOS inverter (top) and DC characteristics of the CMOS inverter(bottom).

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Is your layout correct ?

Click on the above icon to answer the question. The Design Rule Checker (DRC) scans the design and verifies a set of design rules. The errors are highlighted in the display window, with an appropriate message giving the nature of the error. Details about the position and type of error(s) appear on the screen. Only an error-free layout can be sent to fabrication. See Chapter 8 for more details about the design rules and some graphical examples which will help you to understand the origin of the error.

Parametric Analysis of the Inverter

Click on Analysis -> Parametric Analysis. Click on the output node of the inverter in the layout. The window below appears. The parametric analyzer allows you to investigate easily the influence of various parameters on the inverter delay.

Fig. 25. The parametric analyzer

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Select the Delay in the Measurement menu. Select power-supply in the Parameter choice. Click on Start Analysis . An iterative procedure conducts simulations and extracts the delay from the simulation for each value of VDD power supply as defined in the Range menu. The result in Fig. 25 shows that the gate delay decreases rapidly with the power supply.

Fig. 26. Investigation of the VDD supply effect on the power consumption (top), and the effect of the output capacitance load on the delay (bottom).

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Other possible investigations concern the frequency and dissipation. The temperature, the node capacitance and the voltage supply are parameters worth of interest are. Fig 26 gives an account of the increase of the power consumption with the VDD supply. Fig 26 also points out (bottom) the delay increase with the output capacitance load. In order to obtain this curve, you should select the Node Capacitance in the parameter list first, and then modify the items From , To and Step according to Fig. 26. Once those modifications have been made, you can start the analysis. As expected, the gate delay increases rapidly along with the output capacitance.

Save & Quit

Click on F2 or File -> Save. The design is saved under the current name. The MSK appendix is automatically added to the users filename. To leave MICROWIND, click on File->Leave Microwind in the main menu.

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4. Basic Gates

The Nand Gate

The truth-table and the schematic diagram of the CMOS NAND gate with 2 inputs are shown in Figure 26. The NAND gate consists of two nMOS in series connected to two pMOS in parallel. NAND 2 inputs A B OUT 0 0 1 0 1 1 1 0 1 1 1 0

A A Output B NAND Symbol B A

B Output

NAND design
Fig. 26. The truth table and schematic diagram of the CMOS NAND gate design.

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Compiling the Nand Gate

You may load the NAND gate design using the command File -> Read->NAND.MSK. You may also draw the NAND gate manually for the Inverter gate. An alternative solution is to use the logic editor to generate the verilog description of the NAND gate, and to compile this verilog description into layout. In this case, complete the following procedure: Add the NAND symbol, two buttons and one lamp in the logic editor DSCH. Add interconnects and verify the logic behavior of the cell.

In DSCH, Click on File -> Create Verilog File , and click on Save . The Verilog text is example.txt .

In Microwind, Click on Compile->Compile Verilog File. Select example.txt in the appropriate directory. The result is reported in Figure 27. 35

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Fig. 27. A NAND cell created by the CMOS compiler.

Simulation of the NAND Gate

The compiler has already fixed the position of VDD power supply and the ground VSS. The texts A, B, and S have already been fixed to the layout.

Make the node visible Add a Clock

Click on the Clock icon

and click inside the polysilicon box of the gate A.

The clock window appears. Click on OK to assign the default clock parameters to A. Now, click inside the polysilicon box of the gate B. A new clock window appears. Click on OK to assign the new clock parameters to B. Notice that the clock period has been automatically multiplied by two in order to scan all logic input combinations. 36

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Click on the Visible icon and on the output node S.

Click on Simulate. The timing diagrams appear as shown in Figure 28. The rise time is faster because of the pMOS devices in parallel.

Fig. 28. Simulation of the NAND gate.

The 3-Input OR Gate

The truth-table and the schematic diagram of the three-input OR gate are shown in Figure 29. You may use the DSCH logic editor again to design a schematic diagram of the OR gate, generate a Verilog description, and compile the text file in Microwind. As can be seen in the schematic diagram and in the compiled results, the gate is the sum of a NOR3 gate and an inverter. In CMOS, the Negative gates (NAND, NOR, INV) are faster and simpler than the non-negative gates (AND, OR, Buffer).

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Once the cell has been compiled, add one clock to each input (A, B and C). Add the visible property to the output out. Then click on Simulate.
OR 3 Inputs A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

C 0 1 0 1 0 1 0 1

Or3 0 1 1 1 1 1 1 1

A B Output

B C OR Symbol C Nor3 A B C Output

OR gate design

Fig. 29. The truth table, design and schematic diagram of the NOR3 gate (NOR3.MSK).

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Fig. 30. Simulation of the OR gate with 3 inputs (OR3.MSK).

The XOR Gate

The truth-table and the schematic diagram of the CMOS XOR gate are shown in Figure 46. No simple implementation is possible, even if many different solutions can be given. The proposed solution consists of a transmission-gate implementation of the operator.
XOR 2 inputs A B 0 0 0 1 1 0 1 1

OUT 0 1 1 0

A Output B XOR Symbol A N1 A XOR B B

XOR gate design

Fig. 31. The truth table and schematic diagram of the XOR gate.

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The truth table of the XOR can be read as follow: IF B=0, OUT=A, IF B=1, OUT = Inv(A). The principle of the circuit presented in Figure 31 is to enable the A signal to flow to node N1 if B=1 and to enable the Inv(A) signal to flow to node N1 if B=0. The node OUT inverts N1, so that we can find the XOR operator. Notice that the nMOS and pMOS devices situated in the middle of the gate serve as pass transistors. The file is called XOR.MSK and is ready for simulation. Click on Simulate in the main menu. Dont forget to check the chronogram values. You may also use DSCH to create the cell, generate the Verilog description and compile the resulting text. In Microwind, the Verilog compiler is able to construct the XOR cell as reported in Figure 32.

Fig. 32. The layout design of the XOR gate (XOR.MSK).

SIMULATION. Add clock properties to the inputs A and B, a visible property to the output and verify the truth-table of the XOR gate (Figure 32). You may also add a visible property to the nxor intermediate node which serves as an input of the second inverter. See how the signal is altered by Vtn (when the nMOS is ON) and Vtp (when the pMOS is ON). Fortunately, the inverter regenerates the signal.

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Fig. 33. Simulation of the XOR gate (XOR.MSK).

Complex Gates
The one-line complex gate compiler is able to generate the CMOS layout corresponding to any description based on the operators AND and OR, also called complex gates. In the equation, the first parameter is the output name. In the present case that name is s. The sign '=' is obligatory. The '/' sign corresponds to the operation NOT and can be used only right after the '=' sign. The parenthesis '(' ')' are used to build the function, where '.' is the AND operator and '+' is the OR operator.

The complex gate compiler produces compact cells with higher performances in terms of spacing and speed than NAND/NOR based conventional logic circuits. 41

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Fig. 34. A compiled complex gate (CARRY cell)

COMPILER SYNTAX CELL Inverter NAND gate AND gate 3 Input OR 3 Input NAND AND-OR Gate CARRY Cell

FORMULA out=/in n=/(a.b) s=(a.b) s=a+b+c out=/(a.b.c) cgate=a.(b+c) cout=(a.b)+(cin.(a+b))

TRANSISTOR SIZE. The default device size is given by the design rules. You may change the nMOS and pMOS width in the option menu before clicking on COMPILE. IMPLEMENTATION. The p-channel transistors are located at the top of the n-channel transistor net. If the '/' operator has not been specified after the '=' sign, an inverter is added at the right hand side of the compiled cell. That is why an AND gate is compiled as a NAND gate followed by an inverter.

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4. Arithmetic Gates

Half-Adder Gate
The Half-Adder gate truth-table and schematic diagram are shown in Figure 34. The SUM function is made with an XOR gate, the Carry function is a simple AND gate. Load the layout design of the Half-Adder through the F3 (eq. to File -> Read) and HADD.MSK sequence.

HALF ADDER A 0 0 1 1 B 0 1 0 1 SUM 0 1 1 0 CARRY 0 0 0 1

Fig. 34. Truth table and schematic diagram of the half-adder gate (HADD.MSK).

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FULL CUSTOM LAYOUT. You may create the layout of the half-adder fully by hand using the XOR gate first by inserting the AND gate layout (Command File -> Insert AND2.MSK , or Compile carry=A.B ). Then draw the interconnects between gates. Use the polysilicon layer for short connections only, because of the high resistance of this material. Use metal as much as you can, and Poly/Metal, Diff/Metal contact macros situated in the upper part of the Palette menu to link the layers together. VERILOG COMPILING. You may use DSCH to create the schematic diagram ; verify the latter with buttons and lamps and generate the Verilog text by using the command File > Create Verilog File . Without using DSCH, you may alternatively use a text editor (NotePad or WordPad), and enter the following VERILOG text.

Fig. 35. VERILOG description of the half-adder gate (Hadd.txt)

Click on the command File -> Compile -> Compile Verilog File. Select the text file created just before by a simple text editor.

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Fig. 36. Load the VERILOG description of the half-adder gate (Hadd.txt)

Click on Compile. When the compiling is complete, click on OK. The result is shown below. The XOR gate is routed on the left and the AND gate is routed on the right.

Fig. 37. Compiling of the VERILOG description of the half-adder gate (Hadd.txt)

Now, add two clocks inside label A and B , then add an eye on Carry and Sum . Click on Simulate in the main menu. The timing diagrams appear and you should verify the truth table of the half-adder. Click on Stop to return to the editor.

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Fig. 38. Simulation of the half-adder (HADD.MSK).

Full-Adder Gate
The truth table and schematic diagram for the full-adder are shown in Figure 39. The SUM is made with two XOR gates and the CARRY is a complex gate, as shown below.
FULL ADDER A B 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1

C 0 1 0 1 0 1 0 1

SUM 0 1 1 0 1 0 0 1

CARRY 0 0 0 1 0 1 1 1

Fig. 39. The truth table and schematic diagram of a full-adder (FADD.MSK file).

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You may edit the schematic diagram of the full adder using DSCH. Verify the circuit behavior and generate its corresponding Verilog description. The VERILOG description of the Full-adder is given below (fadd.txt):
module fulladd(sum,carry,a,b,c); input a,b,c; output sum,carry; // internal node wire sum1; xor xor1(sum1,a,b); xor xor2(sum,sum1,c); and and1(c1,a,b); and and2(c2,b,c); and and3(c3,a,c); or or1(carry,c1,c2,c3); endmodule

Click on the command File -> Compile -> Compile Verilog File. Select the text file fadd.txt shown above. Click on Compile, and on OK at the end of the compilation. In Figure 40, the XOR gates are at the left side of the design while the complex gate is at the right side of the cell. The simulation of the full-Adder is conducted as follow. First, add a clock on labels A , B and C . For clock A , enlarge the value of the clock in order to slow down the chronogram. The cell is complex and cannot react very rapidly. Do not hesitate to zoom in some parts of the layout to be sure to add the property to the desired label. Then add an eye to carry and sum . The result is given in Figure 41.

Fig. 40. Compiling of a full-adder described in VERILOG.

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Fig. 41. Simulation of a full-adder (File FADD.MSK).

Comparator
The truth table and the schematic diagram of the comparator are given below. The A=B equality represents an XNOR gate, and A>B, A<B are operators obtained by using inverters and AND gates.
COMPARATOR A B A>B 0 0 0 0 1 0 1 0 1 1 1 0

A<B 0 1 0 0

A=B 1 0 0 1

Fig. 42. The truth table and schematic diagram of the comparator (COMP.SCH).

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Using DSCH, the logic circuit of the comparator is designed and verified at logic level. Then the conversion into Verilog is invoked (File -> Make verilog File). Microwind compiles the verilog text into layout. The layout and simulation of the comparator is given in Figure 43. The XNOR gate is located at the left side of the design. The inverter and NOR gates are at the right side. After the initialization, A=B rises to 1. The clocks A and B produce the combinations 00,01,10 and 11. Notice the small glitch on A>B at t=12 ns. This glitch is not a design error. On the contrary, it shows that during the transition of A and B the situation A>B occurs and that the cell is fast enough to react.

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MICROWIND 1.0 Fig. 43. Simulation of a comparator (COMP.MSK file).

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5. Latches and Memories

RS Latch
The RS Latch is made up of two interconnected NAND gates. The Reset and Set inputs are active low. The memory state corresponds to Reset=Set=1. The combination Reset=Set=0 should not be used.
RS LATCH R S 0 0 0 1 1 0 1 1

Q X 0 1 Q

nQ X 1 0 nQ

Reset nQ

Q Set

Fig. 44. The truth table and schematic diagram of a RS latch made from 2 NAND gates (RS.MSK).

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DESIGN. You can use the VERILOG compiler for the creation of the RS latch with cell declarations as follow. See rs.txt text file.

Fig. 45. The design of a RS latch made from 2 NAND gates (RS.MSK).

SIMULATION. Assign a negative pulse to R. The pulse icon is one of the simulation icons and is shown below. Select this icon, then click near the Reset label. The pulse parameter window appears. The default pulse is positive. Invert the voltage cursors situated on the left of the window in order to program a negative pulse.

Pulse property

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Assign another negative pulse to Set. The pulse is automatically delayed from the previous pulse assigned to Reset. Click on Simulate in the main menu. The timing diagrams appear as reported in Figure 46. The simulation steps are the following: Inputs R and S are fixed to 1. The latch is in a memory state. A negative pulse is applied to R. The latch output Q goes to a level of 0. A short time after, a negative pulse is applied to S. The latch output Q goes to 1.

Fig. 46. The simulation of a RS latch (RS.MSK).

D Latch
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The truth table and schematic diagram of the static D latch, also called Static D-Flip-Flop, are shown in Figure 47. The data input D is transferred to the output if the clock input is at level 1. When the clock returns to level 0, the latch keeps its last value.
D LATCH D H 0 0 1 0 0 1 1 1

Q Q Q 0 1

nQ nQ nQ 1 0

D Q H

nQ

Fig. 47. The truth table and schematic diagram of a D Latch (File DLATCH.MSK).

MANUAL DESIGN. Use the one line compiler to create successively one inverter nd=/d, and two complex gates which include the AND/NOR cells using the syntax Q=/(nQ+(nd.h)) and nQ=/(Q+(d.h). Build the interconnections and run the Design Rule Checker. Assign a clock to H and a clock to D. VERILOG COMPILING. Compile the cells using the following description file dlatch.txt . Otherwise you can load a design of the D-latch using the commands File -> Read-> DLATCH.MSK (Figure 48).

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Fig. 48. The design of a D-latch (DlatchLevel.MSK).

SIMULATION. Click on Simulate of the main menu. The timing diagrams appear as reported in Figure 49. The simulation steps are listed below : The clock H is at level 0 so that the latch can be in a memory state. The input D changes. Nothing changes in the output. The clock H goes to level 1. The output Q copies the input D. The clock H goes back to level 0. The output Q keeps its last value.

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MICROWIND 1.0 Fig. 49. The simulation of a D-latch (DLatchLevel.MSK).

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RAM Memory
The schematic diagram of the static memory cell used in High Capacity Static RAMs is given in Figure 50. The circuit consists of 2 cross-coupled inverters and two nMOS pass transistors. The cell has been designed to be duplicated in X and Y in order to create a large array of cells. Usual sizes for Megabit SRAM memories are 256 x 256 cells or higher. The selection line Sel concerns all the cells of one row. The lines Data and nData concern all the cells of one column.
Data Data

Memory

Select
Fig. 50. The schematic diagram of the static RAM cell (RAM.MSK).

The RAM layout is given in Figure 64. Click on File -> Read -> RAM.MSK to read it. The Data and nData signals are made with metal and cross the cell from top to bottom. This allows easy matrix-style duplication of the RAM cell.

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Fig. 51. The layout of the static RAM cell (RAM.MSK).

WRITE CYCLE. Values 1 or 0 must be placed on Data, and the data inverted value on nData. Then the line Sel goes to 1. The two-inverter latch takes the Data value. When returning to 0, the RAM is in a memory state. READ CYCLE. In order to read the cell, the line Sel must be asserted. The RAM value propagates to Data, and its inverted value propagates to nData. SIMULATION. The simulation parameters correspond to the write cycle in the RAM. The simulation steps are as follows : . Mem reaches 1, nMem 0 (unpredicatable value). Data gets to value 1 and nData to value 0. Sel is asserted. The memory cell reaches stays at 1. Data gets to a value of 0 and nData gets to a value of 1. Sel is still asserted. The memory cell gets 0. Sel is inactive. The RAM is in a memory state.

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Fig. 52. Write cycle for the static RAM cell (RAM.MSK).

Complete RAM 4x4 Bit

You can duplicate the RAM cell into a 4x4 bit array using the command Edit -> Duplicate XY. Select the whole RAM cell and a new window appears. Enter the value 4 for X and 4 for Y into the menu. Click on Generate . The result is shown below.

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Fig. 53. Duplicating the RAM Cell in X and Y

The column decoder is based on the following schematic diagram. One line is asserted while all the other lines are at zero. In this circuit one line was picked out from a choice of four lines. Using AND gates would be an easy solution, but in order to save the inverter, we chose NOR gates with inverted inputs.

Fig. 54 - a. A line selection circuit

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Fig. 54- b . A line selection layout and its corresponding simulation (RamLineSelect.MSK)

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The NOR gate height should be adjusted to that of the RAM cell height. When making the final assembly between blocks, the command Edit -> Move Area is very important. This command helps to move a selected block with a lambda step. The row decoder is based on the same principles as those of the line decoder. The major modification is that the data flows both ways, that is firstly from the cell to the read circuit (Read cycle) and secondly from the write circuit to the cell (Write cycle). Fig. 55 proposes an architecture for this. The n-channel MOS device is used as a switch controlled by the column selection. When the n-channel MOS is on and Write is asserted, the data issued from DataIn is amplified by the buffer, flows from the bottom to the top and reaches the memory. If Write is off, the 3-state inverter is in high impedance, which allows one to read the information.

Fig. 55. Row selection and Read/Write circuit (RamRow.MSK)

The final layout of the RAM 4x4 is proposed in Fig. 56. The simulation proposes the read and write cycles at a specific RAM cell address.

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Fig. 56. RAM 4x4 layout and simulation (Ram44.MSK)

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The simulation of Fig. 56 can be described as follows. A [00] fixed line selection selects the upper line, that way sel0 is asserted while all others are at 0. The memory cells mem00 and mem01 do not reach the same initial state : mem00 gets to 0 and mem01 is at 1. When DataIn is at zero, writing a zero has no effect on Mem00. But when the column selection changes, DataIn=0 is copied to Mem01. When DataIn rises to 1 (t=10ns), and when write is 1, the memory cells change from 0 to 1. It is interesting to point out that the memory cell fights against the logic value before surrending and changing its internal state.

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6. Other Projects

This section expounds some typical layout projects and presents the general design principles for the layout of each project. The latter are ready-to-simulate items. They can be simulated in any technology, from 1.2m to 0.12m. Below is how to proceed : Click Read->Filename, Select the filename, Click Simulate.

Notice that most of those layouts are complex and require a significant amount of time for extraction and for simulation.

Four-Bit Adder
This circuit include one half-adder and three full-adders (See Figure 57). The result of each stage propagates to the next one, from the top to the bottom. The circuit allows a four-bit addition between two numbers A3,A2,A1,A0 and B3,B2,B1,B0. Figure 58 details the fourbit adder layout, and Figure 59 shows the corresponding simulation.
4 BIT Adder (ADD4.MSK) NODE DESCRIPTION A3,A2,A1,A0 First number B3,B2,B1,B0 Second number S3,S2,S1,S0 Result

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S0

S1

S2

S3

S4

A0 B0

A1 B1

A2 B2

A3 B3

Half adder

Full adder

Full adder

Full adder

Fig. 57. Schematic diagram of the four-bit adder (ADD4.MSK).

Fig. 58. Design of the four-bit adder (ADD4.MSK).

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Fig. 59. Simulation of the four-bit adder (ADD4.MSK).

2x 2 Bit Multiplier
The multiplier cell is made up of a full-adder cell and a NAND gate. The cell is built for an iterative implementation, and a 2x2bit multiplication is proposed. The circuit multiplies input A (2 bits) with input B (2 bits) which produces a result P, as detailed in Figure 60. The circuit design is complex and the simulation takes a lot of time. The multiplier layout is shown in Figure 61. In the simulation of Figure 62, the multiplication time is 5nS in the worst case.

MULTIPLIER 2x2 BITS NODE DESCRIPTION A0,A1 Digital Input A B0,B1 Digital Input B S0 Bit 0 result of the multiplication A x B S1 Bit 1 S2 Bit 2 S3 Bit 3

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0 0 A1 P0

0 P1 P3 P2

Fig. 60. Truth table and schematic diagram of the 2x2 bit multiplier (MUL22.MSK).

Fig. 61. Design of the 2x2 bit multiplier (MUL22.MSK).

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Fig. 62. Simulation of the 2x2 bit multiplier (MUL22.MSK).

Two-Bit Counter
The one-bit counter is a static register controlled by a single clock H. Its schematic diagram is shown in Figure 63. In order to build a two-bit counter we used two counter cells that we have interconnected as follows: the clock of the second stage is the output of the first one. The clocks H and nH changes the state of C0 at each rising edge. The clock C0 changes the state of C1 at each rising edge. The outputs C0 and C1 make a 2-bit counter. The layout is reported in Fig. 64 and its corresponding simulation is shown in Figure 65. Two-Bit Counter NODE DESCRIPTION H First stage clock nH Inverted clock H P1 Internal register node of stage 1 C0 First counter output nC0 Inverted clock C0 P2 Internal register node of stage 2 C1 Second counter output nC1 Inverted clock C1

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H Div 2

H Clock Divider

H One Stage

H div 2 One Stage

H div 4

Fig. 63. Schematic diagram of the 2-bit counter (DivFreq.MSK).

Fig. 64. Design of the 2-bit counter (DivFreq.MSK).

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Fig. 65. Simulation of the 2-bit counter (DivFreq.MSK).

Wide-Range Amplifier
The wide-range amplifier is built using a voltage comparator and a power output stage. Its schematic diagram is reported in Fig. 66. The difference between V+ and V- is amplified and it produces a result, codified : Vout. The gain near 2.5V is more than 1,000. Use the Voltage vs. Voltage simulator mode to get the transfer characteristics Vout/V+. The input range is around 0.5Vto 4.0V. You can easily build a follower by designing an extra connection from Vout to V-. This layout is shown in Figure 66. The output stage is not strong enough to be able to drive large loads such as output pads.
WIDE RANGE AMPLIFIER NODE DESCRIPTION V+ Positive analog input VNegativeanalog input Vbias Bias voltage Vout Analog output

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Current Mirror

A + B Vbias Amplifier Symbol Vbias Output stage Output Vout VV+

Differential pair Wide Range Amplifier

Fig. 65. Node description and schematic diagram of the analog amplifier (AMPLI2.MSK).

. Fig. 66 Design of the analog amplifier (AMPLI2.MSK).

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Fig. 67. Transient simulation of the analog amplifier (AMPLI2.MSK) connected as a follower

Fig. 68. DC Simulation of the analog amplifier (AMPLI2.MSK) in follower mode, using voltage vs. Voltage mode.

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Interface with PSPICE

The simulation of the transient and DC characteristics of the amplifier can be performed using Microwind. Unfortunately the AC response cannot be computed. The command File -> Make Spice File converts the design into a PSPICE compatible description based on MOS devices and parasitic capacitances (Fig. 69).

Fig. 69. Generation of the file AMPLI2.CIR compatible with SPICE

Figure 69 depicts the interface window. The left part of the window details the list of MOS devices with their associated width and length in lambda unit. The right part lists the contents of the PSPICE compatible file, "AMPLI2.CIR" generated from the electrical extraction of the layout AMPLI2.MSK . To obtain the AC response of the amplifier, the AMPLI2.CIR source file must be modified as follows: an AC source must be declared (Choose the input V+ and add "AC 1 0"), and the .TRAN mode must be replaced by .AC DEC 10 1K 100MEG for example (AC analysis, 10 points/decade, from 1KHz to 100MHz). Run PSPICE and see the result. The DB mode is drawn using the command VDB(output node) in the PLOT command "Add Trace".

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Analog-Digital Converter
The analog-digital converter converts an analog value Vin into a two-bit digital value called A0,A1. The flash converter uses three converters and a coding logic to produce A0 and A1 (Figure 70). A very complex logic circuit and 255 comparators would be used for an ADC eight-bit flash. The polysilicon has a high resistance (50 per square) and can be used as a resistor network (Left of Figure 71), which generates intermediate voltage references used by the voltage comparators located in the middle. The resistance symbol is inserted in the layout to indicate to the simulator that an equivalent resistance must be taken into account for the analog simulation. Open-loop amplifiers are used as voltage comparators. The comparisons address the decoding logic situated to the right and that provides correct A0 and A1 coding.
ANALOG/DIGITAL CONVERTER NODE DESCRIPTION V Analog input C0 Result of comparison with 1.25V C1 Result of comparison with 2.5V C2 Result of comparison with 3.75V A1 Digital output A0 Digital output

5V

Vin

3.75V Poly resistor 2.5V

Amplifer used as comparator + C1 Coding Logic A0 C2 A1

1.25V

+ C0

0V

Fig. 70. Node description and schematic diagram of the analog-digital converter (ADC.MSK).

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Fig. 71. Design of the analog-digital converter (ADC.MSK).

Fig. 72. Simulation of the analog-digital converter (ADC.MSK).

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In the simulation shown in Figure 72, the comparators C0 and C1 work well but the comparator C2 is used in the upper limit of the voltage input range. The generation of combinations 00,01 and 10 is correct. The generation of 11 is slow.

Digital-Analog Converter
The digital-analog converter converts a digital three-bit input (A0,A1,A2) into an analog value Data. The polysilicon resistive net gives intermediate voltage references which flow to the output via a transmission gate net. The resistance symbol is inserted in the layout to indicate to the simulator that an equivalent resistance must be taken into account for the analog simulation. The schematic diagram is shown in Figure 73. The layout of the digital-analog converter is shown in Figure 74.
DIGITAL ANALOG CONVERTER NODE DESCRIPTION Ai nAi Vout Input Ai Inverted input Ai Analog output

5V

4.375V Poly resistor 3.75V

3.125V

2.5V Data 1.875V

1.25V

0.625V

0V A2 A1 nA1 nA2

A0

nA0

Fig. 73. Node description and schematic diagram of the digital-analog converter (DAC.MSK).

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Fig. 74. Design of the digital-analog converter (DAC.MSK)

Fig. 75. Simulation of the digital-analog converter (DAC.MSK).

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The simulation of the DAC (Fig. 75) shows a regular increase of the output voltage Vout with the input combinations, from 000 (0V) to 111 (4.375V). Each input change provokes a capacitance network charge and discharge.

Input-Output Pad Interfacing

We give here some details about input-output pad interfacing. The basic bonding pad size is 100x100m. The pad consists of a sandwich of metal2, via and metal1 layers. For advanced technologies, all metal layers are stacked on the top of each other. Use the process simulator to verify that the passivation oxide has been removed from over the pad, so that a gold connection can be fixed upon it. The input-output pad contains one input stage with a polysilicon resistor and two protection diodes. The output stage contains a chain of inverters. The last stage is a 3-state inverter so that the buffer can be turned off.
INPUT/OUTPUT PAD NODE DESCRIPTION Vout Digital output value EN Enable digital output nEN Inverted Enable digital output Data Pad input value

nEn

Data Out

PAD

En Input Resistor Data In

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Fig. 76. Design of an input-output pad (PAD.MSK)

Pad Ring

Click on the chip library icon and click on Pads. The window reported in Fig. 77 appears. Select the size 100x100 m which enables the pad ring options. A pad ring with 3 pads in X and 3 pads in Y is generated by a click on Generate Pad. In that case, a set of pads is added to your circuit. The VSS pad is situated at the bottom, and the VDD pad at the top with the associated power rings.

Fig. 77. Pads added to generate a pad ring around the chip.

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Figure 78 displays an example of circuit with its input-output pads and interconnects. The chip contains a pad ring of 28 input/outputs (CHIP.MSK file).

Fig. 78. A complete chip with I/O pads and internal logic and analog cells (CHIP.MSK)

ESD Protections The input pad includes some voltage boosting and under voltage protections linked with problems of electrostatic discharge (ESD). Such protections are required as the oxide of the gate connected to the input could be destroyed by over voltage. One of the most simple ESD protection is made up of a set of two diodes and a resistance (Fig. 79). One diode handles the negative voltage flowing inside the circuit (N+/P substrate), the other diode (P+/N well) handles the positive voltage. The layout of the N+/P_Substrate diode includes a simple N+ diffusion in the P- substrate (the cathode K), surrounded by P+ contacts which polarize the P- substrate (the anode A). The current starts flowing between A and K if the voltage is roughly over 0.6V. In the reverse mode, the current is very small, in the order of some pico-Ampere. The polarization of the P- substrate is usually 0V. The diode N+/P- will be on if the voltage of the N+ region is less than -0.6V. 79

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Fig. 79. Detail of the Input protection used against electrostatic discharge (CHIP.MSK)

One simple way to add a diode in the layout is to click on the cell library icon, then click on the Contacts menu and to assert the options : Diffp/Metal and Diff N+ on Nwell . This creates a P+/Nwell diode with its appropriate contacts (Fig. 80).

Fig. 80 -a : Create a diode based on a Diffp/Metal contact in nwell

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Fig. 8- b :. Create a diode for I/O pad protections

Path between Pads and Cells

Draw a path

The path command considers the easy editing of a path in one layer only (Fig. 81). The path width can be changed, as well as the alignment to the routing grid. A set of contacts can also be placed at both ends of the path. This command is very useful for VDD and VSS supply drawing and single layer interconnects.

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Fig. 81. The path menu and a path example

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7. Design Rules

This section gives information about the design rules used by Microwind. You will find all the design rule values common to all CMOS processes. All those rules, as well as process parameters and analog simulation parameters are detailed here. The evolution of the integrated circuit technology resides mainly in the reduction of the feature size, also called lithography . As the chart below (Fig. 82) shows, in 1986, the minimum feature size was around 1.2m. Ten years later, the lithography had been downsized to 0.25m. For year 2000, the lithography around 0.12m is expected for leading edge products such as high-performance micro-processors.
Lithography Lambda (m) Year Metal layers Power Supply (V) 1.2m 0.8m 0.6m 0.35m 0.25m 0.18m 0.12m 0.6 0.4 0.30 0.2 0.15 0.1 0.07 1986 1988 1992 1994 1996 1998 2000 2 2 3 5 6 6 6 5.0 5.0 3.3 3.3 2.5 1.9 1.5 250 200 120 75 65 50 40 0.8 0.7 0.6 0.5 0.45 0.40 0.30 Oxide (A) Threshold (V) Typical Microwind

gate delay design rule file (pico-sec) 840 800 410 360 260 250 240 ams12.rul es208.rul ams06.rul cmos035.rul cmos025.rul cmos018.rul cmos012.rul

Fig. 82 : Technological trends for MOS devices

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As can be noticed, the number of metal layers used for interconnects has been continuously increasing in the course of the past ten years while the power supply decreased due to the reduction of the MOS gate oxide thickness, and thus the lower oxide breakdown voltage. The MOS threshold voltage was also significantly reduced. The overall consequence of this technology scale down is the gate delay decrease leading to higher operating frequencies, although the rapid reduction of the power supply slows down the gain in terms of performances. Some details about the size and electrical properties of the interconnects are reported in Fig. 83. The metal pitch is following the lithography, but the interconnect thickness is not reduced with the same trend. The cross-section of the interconnect is reduced, leading to a higher resistance per length unit. Starting at 0.18m, one could replace aluminum by copper due to the lower resistivity of the latter and its much greater ability to drive high currents.
Technology Metal layers Lower metal Pitch (m) 1.2m 0.7m 0.5m 0.35m 0.25m 0.18m 0.12m 2 2 3 5 6 6 7 1.8 1.2 0.75 0.6 0.45 0.3 0.22 Upper metal Pitch (m) 2.4 1.6 1.25 1.2 0.9 0.6 0.5 Thickness metal (m) 1.2 1.1 1.0 1.0 0.9 0.8 0.7 Static Interconnect Microwind file

Resistance Materials (ohm/sq) 0.025 0.025 0.04 0.05 0.06 0.07 0.08 Alu, Sio2 Alu, Sio2 Alu, SiO2 Tu, Alu, SiO2 Tu, Alu, Sio2 Tu, Cu, SiO2 Tu, Cu, SiO2 cmos12.rul cmos07.rul cmos05.rul cmos035.rul cmos025.rul cmos018.rul cmos012.rul

Fig. 83 : Technological trends for interconnects

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Design Rules
The software can handle various technologies. The process parameters are stored in files with the appendix '.RUL'. The default technology corresponds to the ATMEL-ES2 2-metal 0.8m CMOS process. The default file is ES208.RUL. To select a foundry, click on File -> Select Foundry and choose the appropriate technology in the list. N-Well

r101 nwell

r102 nwell p substrate

r101 r102 Diffusion r201 r202 r203 r204

Minimum well size : 12 Between wells : 12

Minimum diffusion size : 4 Between two diffusions : 4 Extra well after diffusion : 6 Between diffusion and well : 6

r203

P+ diff

r202

P+ diff

r201 r204

nwell

N+ diff

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Polysilicon r301 r302 r303 r304 r305 r306 r307 Polysilicon width : 2 Polysilicon gate on diff n+ : 2 Polysilicon gate on diff p+ : 2 Between two polysilicons : 3 Poly v.s other diff diffusion : 2 Diffusion after polysilicon : 4 Extension of Poly after diff : 2

r305

P+diff r302 r306 nwell

r301

r304

r306 N+diff r307

Contact r401 r402 r403 r404 r405 Contact width : 2 Between two contacts : 3 Extra metal over contact:2 Extra poly over contact: 2 Extra diff over contact: 2

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r403 r402

metal r401 r405 contact r404

N+diff

poly

Metal 1 r501 r502 Metal width : 3 Between two metals : 3

r501

metal

r502

metal

Via r601 r602 r603 r604 r605 Via width : 3 Between two Via: 3 Between Via and contact: 3 Extra metal over via: 2 Extra metal 2 over via: 2
r604 r602 via r601 r603 contact

metal2

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Metal 2 r701 r702 Metal width: 5 Between two metal2 : 5

r701

metal2

r702

metal2

Via 2 r801 r802 r803 r804 Metal 3 r901 r902 Metal3 width: 6 Between two metal3s : 5 Via2 width : 3 Between two Via2s: 4 Between Via2 and via : 4 Extra metal2 & metal 3 over via2: 3

Via 3 ra01 ra02 ra03 ra04 Via3 width : 4 Between two Via3s : 6 Between Via3 and via2 : 6 Extra metal4 and metal3 over via3: 6

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Metal 4 rb01 rb02 Metal4 width: 10 Between two metal4s: 22

Via 4 rc01 rc02 rc03 rc04 Via4 width : 4 Between two Via4s : 6 Between Via4 and Via3 : 6 Extra metal4 & metal 5 over via4: 6
rc04 rc02 via4 rc01 rc03 Via3 metal5 & metal4

Metal 5 rd01 rd02 Metal 5 width: 10 Between two metal5s : 22

rd01

metal 5

rd02

metal 5

Pads rp01 rp02 rp03 rp04 rp05 Pad width: 100 m (lambda conversion depending on the technology) Between two pads 100 m Opening in passivation v.s via : 5m Opening in passivation v.s metals: 5m Between pad and unrelated active area : 20 m

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rp03 PAD rp02

rp01

Parasistic Capacitors
Each deposited layer is separated from the substrate by a SiO2 oxide and generated by a parasitic capacitor. The unit is the aF/m2 (atto = 10-18 ). Polysilicon, Metal and Metal2 generate parasitic capacitors. Diffused layers generate junction capacitors (N+/P-, P+/N). The list of capacitances handled by MICROWIND is given below. The name correspond to the code name used in ES208.RUL.
NAME CMEBody CMEPoly CM2Body CM3Body CM4Body CM5Body CM2Poly CM2Metal CPOOxyde CPOBody CDNDiffp CDPDiffn CLDn CLDp DESCRIPTION Metal on thick oxide to substrate Metal on polysilicon Metal2 on thick oxide Metal3 on thick oxide Metal4 on thick oxide Metal5 on thick oxide Metal2 on polysilicon Metal 2 on metal Poly gate Poly on field oxide Junction diode Diffn in p-well, surface Junction diode Diffp in n-well,surface Junction diode Diffn in p-well, lineic Junction diode Diffp in n-well, lineic VALUE 17 aF/m2 50 13 15 13 10 25 45 1500 60 420 350 260 aF/m 310 aF/m

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Design Rule File

An example of design rule file ES208.RUL (ATMEL-ES2 0.8m technology) is given below.
MICROWIND v1.00 * * Rule file for * Atmel ES2 0.7m * CMOS 2-metal * * 23 Fev 97 by Etienne Sicard * Modified : 6-Jun-97 Res,thick,GDS2, CIF * : 9-Jun-97 Metal,metal2 capas * * NAME Atmel-ES2 0.7m - 2 Metal * lambda = 0.4 (Lambda is set to half the gate size) metalLayers = 2 (Number of metal layers : 5) * * Design rules associated to each layer * * Well (1) r101 = 10 (well width) r102 = 10 (well spacing) * * Diffusion (12,14) * r201 = 4 (diffusion width) r202 = 4 (diffusion spacing) r203 = 6 (border of nwell on diffp) r204 = 6 (nwell to next diffn) r205 = 5 (diffn to diffp) * Poly (11) r301 = 2 (poly width) r302 = 2 (ngate width) r303 = 2 (pgate width) r304 = 3 (poly spacing) r305 = 1 (spacing poly and unrelated diff) r306 = 4 (width of drain and source diff) r307 = 2 (extra gate poly) * Contact (16) r401 = 2 (contact width) r402 = 3 (contact spacing) r403 = 2 (metal border for contact) r404 = 2 (poly border for contact) r405 = 2 (diff border for contact) * Metal (17) r501 = 3 (metal width) r502 = 3 (metal spacing) * Via (18) r601 = 3 (Via width) r602 = 3 (Spacing) r603 = 3 (To unrelated contact) r604 = 2 (border of metal&metal2) * metal 2 (19) r701 = 3 (Metal 2 width) r702 = 3 (spacing) * * Pads (Passiv is 20) * rp01 = 278 (Pad width) rp02 = 278 (Pad spacing) rp03 = 13 (Border of Via for passivation ) rp04 = 13 (Border of metals) rp05 = 63 (to unrelated active areas) * * * Thickness of layers * thpoly = 0.7 hepoly = 0.5 thme = 0.8 heme = 1.1 thm2 = 1.2 hem2 = 2.0 thpass = 1.0 hepass = 3.0 thnit = 0.5 henit = 4.0 * * Resistance (ohm / square) * repo = 25 reme = 0.075 rem2 = 0.040 * * Parasitic capacitances * cpoOxyde = 2300 (Surface capacitance Poly/Thin oxyde aF/m2) cpobody = 53 (Poly/Body) cmebody = 44 cmelineic = 12 (aF/m) cmepoly = 52 cm2body = 56 cm2lineic = 10 (aF/m) cm2poly = 44 cm2metal = 84 * * Crosstalk * cmextk = 50 (Lineic capacitance for crosstalk coupling in aF/m) cm2xtk = 80 (C is computed using Cx=cmextk*l/spacing) * * Junction capacitances * cdnpwell = 520 (n+/psub) cdpnwell = 600 (p+/nwell) cnwell = 100 (nwell/psub) cpwell = 100 (pwell/nsub) cldn = 310 (Lineic capacitance N+/P- aF/m) cldp = 820 (Idem for P+/N-) * * Nmos Model 3 parameters * NMOS l3vto = 0.8 l3vmax = 130e3 l3gamma = 0.4 l3theta = 0.2 l3kappa = 0.01 l3phi = 0.7 l3ld = -0.05 l3kp = 135e-6 l3nss = 0.07 * * Pmos Model 3 * PMOS l3vto = -1.1 l3vmax = 100e3 l3gamma = 0.4 l3theta = 0.2 l3kappa = 0.01 l3phi = 0.7 l3ld = -0.05 l3kp = 47e-6 l3nss = 0.07 * * MicroWind simulation parameters * deltaT = 4.0e-12 (Minimum simulation interval dT) vdd = 5.0 temperature = 27 * * CIF&GDS2

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* MicroWind name, Cif name, Gds2 n, overetch for final translation * cif nwell CNWI 1 0.0 cif aarea CTOX 2 1.0 cif poly CPOL 11 0.0 cif diffn CNPI 12 1.0 cif diffp CPPI 14 1.0 cif contact CCON 16 0.1 cif metal CME1 17 0.0 cif via CVIA 18 -0.1 cif metal2 CME2 19 0.0 cif passiv CPAS 20 0.0 cif text text 0 0.0 * * End atmel-ES2 0.7m *

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8. Program Operation

Getting Started
To get your MICROWIND program started, use the following procedure: Insert the MICROWIND diskette into drive a: Under Windows 95/NT, click on Start -> Execute Type a :install and press Create a shortcut to the executable file Microwind and double click on it to start the software

The software runs only on Windows 95 or Windows NT. NOTICE : The command line may include two parameters : 1. The First parameter is the default mask file loaded at initialization 2. The Second parameter is the design rule file loaded at initialization Example : The command microwind fadd ams06.rul executes MICROWIND with a default mask file fadd.MSK and the rule file ams06.RUL .

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9. Commands

Copy Click on the Copy icon. Move the cursor to the design window, and delimit the active area with the mouse. Consequently, all the graphics included in this area are copied. The external shape of the copied elements appear. Fix those copied elements at the desired location by a click on the mouse. Click on Undo to cancel the copy command.

Cut Click on the Cut icon. Move the cursor to the design window, and delimit the active area with the mouse. Consequently, all the graphics included in this area are erased. Click on Undo to fix those elements back into the design. A layer is protected from erasing if you remove the tick in the palette twice. In the palette, an empty square to the right of the layer indicates a protected layer. A layer is unprotected from erasing if you select it again in the palette. A tick in the square to the right of the layer indicates an unprotected layer. One box only can be erased by a click inside that box when the cut command is active. The box is then erased.

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See Move to move one box or a group of boxes. See Stretch to stretch a box. Cif Out MICROWIND converts the MSK layout into CIF using a specific interface. The CIF file can be exported to various industrial software. The screen is shown below. The right table gives the correspondence between MICROWIND layers and CIF layers, the number of boxes in the layout and the corresponding over-etch. The over-etch is used to modify the final size of the CIF boxes in order to fit the exact design rules. Click on Convert to CIF to start conversion. Some parts of the result appear in the left window.

Compile one Line The cell compiler is a specific tool designed for the automatic creation of CMOS cells from logic description. Click on Compile -> Compile One Line. The menu below appears. The default equation corresponds to a 3 input NOR gate. If need one can use the keyboard in order to modify the equation and then click on Compile. The gate is compiled and its corresponding layout is generated.

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The first item of the one-line syntax corresponds to the output name. The latter is followed by the sign = , the optional sign not / , and by the list of input names separated by the operators AND . or OR . . If need be, parenthesis can be added. The input and output names are 8 character strings maximum. The table below shows different examples of cell formulas : COMPILER SYNTAX CELL Inverter NAND gate AND gate 3 Input OR 3 Input NAND AND-OR Gate CARRY Cell

FORMULA out=/in n=/(a.b) s=(a.b) s=a+b+c out=/(a.b.c) cgate=a.(b+c) cout=(a.b)+(cin.(a+b))

TRANSISTOR SIZE. The default device size is given by the design rules. You may change the nMOS and pMOS width in the option menu before clicking on PILE. IMPLEMENTATION. The p-channel transistors are located on the top of the n-channel transistor net. If some layout already exists near those icons, the cell origin is moved to the right until enough free space is found. If the '/' operator has not been specified after the '=' sign, an inverter is added at the right hand side of the compiled cell. That is why an AND gate is compiled as a NAND gate followed by an inverter. Compile a VERILOG description The cell compiler can handle layout generations from a primitive-based VERILOG description text into a layout form automatically. Click on Compile -> Compile Verilog File. Select a VERILOG text file and click on OK. For instance, the microwind directory contains the HADD.TXT file which corresponds to the description of a half-adder.

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The menu below appears. If need be modify the transistor sizing and click on Compile. The VERILOG text is compiled into a set of basic gates and its corresponding layout is generated.

Design Rule Checker

The design rule checker (DRC) scans all the design and verifies that all the minimum design rules are respected. Click on the icon above or on Analysis ->Design Rule Checker to run the DRC. The errors are highlighted in the display window, with an appropriate message giving the nature of the error. Details about the position and type of the errors appear on the screen.

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Draw a Box

The Draw Box icon is the default icon. It creates a box in the selected layer. The default layer is Poly. If the Draw Box icon is not selected, click on it. Then, move the cursor to the display window and fix the first corner of the box with a press of the mouse. Keep pressed and drag the mouse to the opposite corner of the box. Release the mouse and see how the box is created. The active layer is selected in the palette. The red color indicates the active layer. The tick specifies that all boxes using the layer can be erased, stretched or copied. Removing the tick protects the layer. Duplicate XY

The command Duplicate XY is very useful to generate an array of identical cells such as RAM cells for example. Click on Edit -> Duplicate XY, include the elements to duplicate in an area defined by the mouse, and the following screen appears. In both X and Y, the default multiplication factor is x 2. You may adjust the space between cells. By default, the cells touch each other.

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Extract Options The extraction options are detailed in the menu below. The default extraction includes the removal of redundant boxes (Purge) and the removal of overlaps (Merge). The fast extraction does not handle Purge nor Merge operations. The MOS level can be chosen between level 1 and 3. See chapter 2 for more details about those models. Other options concern the computation of lateral capacitances and vertical crosstalk capacitances.

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Floating Node Click on Analysis -> Floating Nodes to scan the layout and detect nodes that might be floating. The navigator gives the list of the floating nodes in the Navigator menu. Click on the corresponding name to locate it in the drawing. A floating node is an interconnect not connected to a diffusion. Floating gates are listed even if they include a clock or pulse property.

Foundry Click on File -> Select Foundry. The list of available processes appears. The default design rule file is written in bold characters. Various technologies are available from 1.2 down to 0.12 m. Click on the rule file name and the software reconfigures itself in order to adapt to the new process. Hardcopy Click on File ->Print Layout to transfer the graphical contents of the screen to the printer. You can make a copy of the window into the clipboard in order to import the screen into your favorite text editor by pressing <Alt>+<Print Screen>. In the text editor or in the graphic editor, simply click on Edit ->Paste We recommend that you switch to monochrome mode first by invoking the function File -> Monochrom/Color. In that case the layout will be drawn in a white background color using gray levels and patterns. Library

The library contains a set of predefined layout macros such as contacts, devices and pads. Those cells are built according to design rules, and contain size parameters. To invoke the cell library click on the above icon.

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CONTACTS. Contacts such as polysilicon/metal, n-diffusion/metal, p-diffusion/metal and metal/metal2 metal2/Metal3,(etc..) can be obtained here. You may also repeat a number of contacts in X and Y. You may also generate a polarization seal around the contact to create a pad diode protection for example. Click on Generate Contact. The outline of the latter appears. Then click on the mouse to set this outline in the appropriate place.

MOS. This macro generates either a n-channel or a p-channel transistor. The parameters of the cell are the channel length (default value is given by the design rules), its width, and the number of gates. Once those parameters are defined, the device outline appears. Click on the mouse to place it in the appropriate place.

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PADS. It is possible to add various items such as a single pad, a test pad (usually 30x30 m), or even a set of pads all around and to the layout using the VDD and VSS power rings. In the last case (adding more than one pad), give the number of pads each side of the chip and if need be modify the width of the VDD and VSS tracks.

ROUTING. This command is used to rout interconnects in one metal layer (metal 1 by default) for horizontal tracks and in another metal layer (metal2 by default) for vertical tracks. The appropriate contact is generated automatically. This command is very useful for cell routing using two different metal layers.

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PATH. This command is similar to the ROUTING command but it considers only one layer. The path width can be changed, as well as the alignment to the routing grid. A set of contacts can also be placed at both ends of the path. This command is very useful for VDD and VSS supply drawing and single layer interconnects.

BUS. This command generates a set of parallel lines with user-defined layer, width and spacing. This command is useful to build the final routing of a chip.

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Measure distance : See ruler

MOS device

Click on the icon. The Id/Vd curve of the default MOS (W=20m, L=L minimum) appears. You can skip to Id/Vg mode to highlight the threshold voltage, or to Id(log)/Vg to see the sub-threshold behavior. You may add measurements by selecting a .MES file then skip from NMOS to PMOS and select the size of the device in the lower menu. Two models can be used : MOS Model 1 (Berkeley Spice) MOS Model 3 (Simplified version of Berkeley Spice) The effects of the changing of the model parameters can be seen directly on the screen by a click on the little arrows which change the parameter values. Also, the vertical scale can be altered, as well as some configuration parameters.

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Measurements Click on View->Measurements to load some measurements together with the simulations in the I/V window proposed above. This command is a short cut to the button Add Measurement of the MOS characteristics window.

Move a Box

To move one box, click on the above icon. Using the mouse, create an area which includes the box. Then, drag the mouse to the new location and release the mouse. As a result, the box has been moved the new place. Repeat the same in order to move a set of boxes. To protect a layer from moving , click in the rectangle the palette that is situated on the right side of the layer. This will remove the tick. File -> New Click on File-> New in order to restart the software with an empty screen. The current design should be saved before asserting this command, as all the graphic information will be physically removed from the computer memory. No Undo is available to disable the New command. File -> Open Click on the icon . In the list, double-click on the file to load. .MSK is the default extension that corresponds to the layout files. The CIF files .CIF can also be loaded. The appropriate conversion program transforms the input CIF into MSK format. File -> Insert The command File -> Insert is used to add a MSK file to the existing files. The inserted layout is fixed at the right lower side of the existing layout. The current file name remains unchanged.

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File -> Statistics The command File -> Statistics provides some information about the current technology, the percentage of memory used by the layout and the size of the layout plus its detailed contents. If the layout has previously been extracted or if you click extract now , the number of devices and nodes will be updated.

View Node

Click on the icon above or onView -> View Node. Then, click in the desired box in the layout. After an extraction procedure has been carried out, you will see that all the boxes connected to that node. In the case of a large layout, the command may take time. The associated parasitic capacitance and the list of text labels added to the selected boxes are also displayed in a specific window. Click <Escape> or View -> Unselect All to unselect the layout.

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View Interconnect The command View -> View Interconnect performs an electrical extraction of the metal and polysilicon boxes connected to the desired point. Compared to View Node, this command works faster but does not consider diffused layers that can extend the node interconnect network. The command gives the list of connected text labels. Click on <Escape> or on View -> Unselect All to unselect the layout. Palette

The palette is located on the right side of the screen. A little tick indicates the current layer. The selected layer by default is a polysilicon (PO). The list of layers is given below.

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If you remove the tick on the right side of the layer, the layer is switched to protected mode. The Cut, Stretch and Copy commands no longer affect that layer. If the tick is present, the layer is unprotected.

View -> Process Aspect

Click on the above icon to access process simulation. A mouse-operated line is given and embodies the cross section. The arrows can be used to move the cross-section to the right or to the left in the X axis, and forward and backward in the Y axis.

Pspice File Click on File -> Pspice File to translate your design into a PSPICE compatible description. The circuit extractor included in the software generates the equivalent circuit diagram of the layout and a spice compatible netlist ready to be simulated. You may select the model you will be using for simulation. The choice lies between model 1 and model 3. 109

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The SPICE description includes the list of n-channel and p-channel transistors and their associated width & length extracted from the layout. The text file also details the node names, parasitic capacitances, and device models. The SPICE filename corresponds to the current filename with the appendix .CIR. Leave Microwind Click on File -> Leave Microwind in the main menu. If you have made a design or if you have modified some data, you will be asked to save it. After confirmation, you can return to Windows.

Open Click on File -> Open in the main menu. The list of layout description files appears. Click inside the file name to load it. Parametric Analysis Before running the parametric analysis, you should run a simulation first. Select the desired output node on which the delay measurement or frequency measurement is performed, then click on Analysis -> Parametric Analysis. Click on a cell output node in the layout. The window below appears. The parametric analyzer allows you to easily investigate the influence of various parameters on the cell performance. 110

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In the parameter menu, you may investigate the influence of temperature, power supply or that of a node capacitance. In the measurement menu you may choose to monitor the rise and fall delay, the power consumption, or the frequency. Click on Start Analysis . An iterative procedure will conduct simulations and extract the relevant parameters. The result below shows the evolution of the cell delay when its output node capacitance has been changed. Notice that for high capacitance values, the cell response is very slow. The input clock parameters should be consequently be adjusted in order to fit with low speeds.

Rotate and Flip To apply a rotation or a flip to one part of the design, click on Edit -> Rotate or on Flip <>. Delimit the active area of the boxes in the layout so that it can be modified using the mouse. Save Click on File -> Save to save the layout with its current name. The default name is EXAMPLE.MSK .

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Save As A new window appears, into which you are to enter the design name. Use the keyboard and type the desired file name. Press Save . Your design is now registered within the .MSK appendix.

Ruler The ruler gives the vertical and horizontal measurements directly on the screen in lambda and in micron. The ruler is simply erased by the command View -> View Same or by a press of <ESC>.

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Search Text The most convenient way to find a text in the layout is to invoke Edit -> Search text. The list of text labels appears in the navigator menu. If you click on the desired text, the screen is redrawn so that the text label is at the center of the window, with two lines drawing a cross at the text location. Its properties appear in the navigator menu.

Click on Hide to close the navigator window. Click on Extract to add the electrical properties of the selected text if the layout has not been previously extracted. NOTE : In the case of a very long text list, select the first letter of the text at hand, press that letter on the keyboard. This will automatically effect and alphabetic research and the selector will move to the first label starting with the selected letter. Simulate

The above icon or the command Simulate -> Start Simulation both give access to the automatic extraction and analog simulation of the layout.

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Simulation Icons The simulation icons add properties to the nodes. Properties are applied to the electric nodes of the circuit in order to serve as simulation guides. You must specify which node is assigned to which voltage before starting the analog simulation.

VDD property VSS property Clock property Node visible Pulse property

VDD & VSS. The node is pushed to the power supply voltage (usually 5V) icon Vdd, and pulled to the ground 0V with icon Vss. CLOCK. When a node becomes a clock, the parameters of the latter are divided as follows : rise time, level one, fall time, and level zero. All values are expressed in nansecond (ns). If you ask for a second clock, the period will be multiplied by two. You may alter level 0 and level 1 using the keyboard. To generate a clock starting from VDD instead of VSS, click on Invert L/H. Use Period * 2 to multiply the clock period by two. Use Period /2 to divide the clock period by two.

PULSE. The positive impulse appears after a given delay, gets a rise time, then stays at level one for an other delay, and drops to zero with a fall time. If you ask for an other impulse , the initial delay is increased. The negative impulse can be obtained by inverting the voltage values of levels one and zero.

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VISIBLE NODE. Click on

and click on the existing text in the layout to make the

chronograms of the node appear. Initially, all nodes are invisible, but the clocks and impulse nodes are subsequently made visible.

Text Use this icon to fix a text to one box or location in the design. That text illustrates the layout and should be used as much as possible for each significant node such as inputs and outputs. Click on the icon, click the desired location in the layout, enter the text using the keyboard and press . The text is fixed in the appropriate place. Simulation Menu The simulation menu contains a list of buttons which give access to simulation parameters. The list of options is detailed below.

Select the node from which the delay counter is started at each crossing of VDD/2 The delay counter is stopped at each crossing of VDD/2 and the delay is drawn The minimum and maximum voltage of the selected node are displayed. At each period of the selected node, the frequency is displayed More simulation Restart simulation from time 0 Select the time scale within a list in the menu

Select the time interval between two simulation steps. Stop simulation. A second click and you are back to the editor

NOTE : You can modify the minimum simulation step t, but it may be dangerous. If you increase t the simulation speed improves but the numerical error may lead to unstable simulations. If you decrease t, the simulation speed is decreased too but the numerical precision is improved. The risk of computing divergence is reduced. 115

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Voltage vs. time

Click on Voltage vs Time to obtain the transient analysis of all visible signals. The delay between the selected start node and selected stop node is computed at VDD/2. You can change the selected start node in the node list, in the right upper menu of the window. You can do the same for the selected stop node.

Voltage and Currents

Click on Voltage and Currents so as to make all voltage curves appear in the lower window, and the VDD, the VSS and the desired MOS currents appear in the upper window. In that mode, the dissipated power within the simulation is also displayed.

Voltage vs. Voltage

Click on Voltage vs. Voltage to obtain transfer characteristics between the X-axis selected node and the Y-axis selected node. Initially the start node is the first clock or pulse of the node list, and the stop node is the first varying node. You can change the X axis and Y axis nodes in the selection menu This mode is useful for the computing of the Inverter characteristics and for the exhibiting of the commutation point. It also allows the operational amplifier to draw the DC response and to check up the gain. Finally, it is also useful for the Schmitt trigger to see the hysteresis phenomenon. The first simulation computes the value of the stop node for start node varying from 0 to VDD. The second click on Simulate computes the same for start node varying from VDD to 0.

Stretch & Move To increase the size of one box, click on the Resize Icon. Then click on the border of the box. Drag the mouse to the new location and release the mouse. The box is resized. 116

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If you define an area which includes some boxes or text, you are in move mode. The elements disappear, and are replaced by their bonding box. Click on the new location to move those elements. Text Some text can be added to any box inside the design. The text is automatically propagated to the electrical node attached to it. To add some text to a particular place, proceed as follows: Click on the icon Set the text location with the mouse. A dialog box appears Enter the text and press OK. The text is set in the drawing . Then click inside the existing text. The old

A text can be modified as follows: click on text appears. Modify it and click on OK. Undo

Do not take into account the last editing command. It is possible to undo the commands Cut, Paste, Copy, Move, Stretch, Edit and Compile. Unselect All

Click on View -> Unselect All (or <ESC>) to unselect the layout. This command is useful to draw the layout back into its default colors after commands such as View Interconnect or View Node which highlight one single node. View All

Click View -> View All to fit the screen with all the graphical elements currently on display.

Zoom In & Out

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Those icons perform Zoom In and Zoom Out. When zooming in, the area determined by the mouse will be enlarged to fit the display window. When zooming out, the area determined by the mouse will contain the display window. If you click once, a zoom is performed at the desired location. Click Ctrl+A for View All , and Ctrl+o for zoom out.

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10. Quick Reference Sheet

FILE MENU
Reset the program and start with a clean screen Read a layout data file Insert a layout in the current layout Translates the layout into CIF Save the layout Switch to monochrom/Color mode Access to the list of foundries (*.RUL) Layout properties : number of box, devices, size Quit Microwind and returns to Windows 95

Extract the electrical circuit and translates into SPICE

Print the layout

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VIEW MENU

Unselect all layers and redraw the layout Fit the window with all the edited layout Redraw the screen

Zoom In, Zoom out the layout window Access to the measured I/V

Protect all layers from modifications Extract the electrical node starting at the cursor location Extract the node propagating on metal interconnects

View the 2D crosssection of the layout

SIMULATE MENU

Extract the electrical circuit an run the simulation Access to the single MOS characteristics in DC, model parameters and measurements Select MOS model, gain access to parameters

Access to the SPICE model and some extraction options : layout cleaning, handle lateral coupling ... Extract the electrical network and make a SPICE file

Remove redundant boxes, clean the data base

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ANALYSIS MENU

Verifies the layout and highlight the design rule violations Gives the list of nodes not connected to diffusion layers Shows the navigator menu Computes the effects of VDD, t, capacitance on delay, freq, etc...

PALETTE (

)
Contact diffn/metal Contact poly/metal MOS generator Pad Contact diffp/metal Contact via/metal Unprotect all layers Routing

Select the current layer

Protect/unprotect the layer from delete & stretch

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LIST OF ICONS See Page Open a layout file MSK Save the layout file in MSK format Draw a box using the selected layer of the palette Delete boxes or text. Copy boxes or text Stretch or move elements Zoom In Zoom Out View all the drawing

Extract and view the electrical node pointed by the cursor Extract and simulate the circuit Measure the distance in lambda and micron between two points 2D vertical aspect of the device Design rule checking of the circuit. Errors are notified in the layout. Add a text to the layout. The text may include simulation properties. Chip library of contacts, MOS, metal path, 2-metal routing, pads, etc... View the palette Static MOS characteristics

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LIST OF FILES

PROGRAM MICROWIND.EXE *.RUL *.MSK *.MES *.CIR *.TXT *.RUL

DESCRIPTION Layout Editor and Simulator Design rule files Layout files MOS I/V Measurements Spice compatible files Verilog text inputs The MICROWIND program reads the rule file to update the simulator parameters (Vt, K,VDD, etc...), the design rules and parasitic capacitor values. A detailed description of the .RUL file is reported at the end of Chapter 8. The MICROWIND software creates data files with the appendix .MSK. Those files are simple text files containing the list of boxes and layers, and the list of text declarations. The 3D module can simulate the fabrication process of any .MSK file. The MICROWIND program generates a SPICE compatible description file when the command File -> Make SPICE File is invoked. For example, if the current file is MYTEST.MSK, a text file MYTEST.CIR is generated and contains the list of transistors, capacitors and voltage sources corresponding to the drawing, in SPICE compatible format.

*.MSK

*.CIR

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11. Instructor's Guide

TUTORIAL ON MOS (1H) The Microwind program may be used for a beginning electronics class to design a single MOS, to add clocks and see how the MOS device is turned on or off. Students should have time to look both at the cross-section of the transistor and the I/V characteristics. Possible questions to ask students include the following: Give an approximation of the threshold voltage. It should be 0.75V. Find the maximum current Ids available. It should be around 1mA. Modify the width (4-> 8) and find the new Ids maximum. It should be twice as wide as the previous one, because of the law Ids=W/L (...). Modify the temperature. It is not obvious that a lower temperature makes the device run faster. Many students tend to think the opposite way. Switch to the simulation of the p-channel MOS. Point out the problem of the reduced mobility (n=500 cm/V.s, p=250 cm/V.s). DESIGN OF CMOS CELLS (16H) It will take about 16 hours to cover the design and simulations of an inverter, a logic gate, a complex gate, an arithmetic circuit, an amplifier and a converter. This program allows students to design and simulate an IC.

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Although a very user-friendly and highly intuitive program, students should nevertheless learn its basis with an instructor. Three-four hour sessions should be sufficient to learn about this package and use it. We recommend the following procedure: Conduct a step by step manual design of the inverter as shown in Chapter 3. This provides the student with a good introduction to the basic commands such as: Draw a Box Erase one Box Change a layer Add text Add VDD, VSS or a CLOCK Simulate Write

Simulate your inverter. Minor problems may occur if the VDD and VSS buses are not correctly polarized. Make a ring-oscillator and observe the resulting frequency. Use the DSCH logic editor to design a schematic diagram. Verify its logic behavior. Click on Make Verilog File and save the file. Then compile the VERILOG text file using the Microwind command Compile Verilog . Add clock properties and verify the correct analog behavior of the cell.

Conduct arithmetic, latch or analog cell projects or projects such as: Schmitt Trigger Multiplier Follower Shift register Oscillator Memory cell

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Notes

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