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Acknowledgements
These slides are the result of the work of the following members of the NuSMV team: Alessandro Cimatti Marco Pistore Marco Roveri Roberto Sebastiani For comments or questions, please contact: Marco Pistore (pistore@dit.unitn.it) Marco Roveri (roveri@irst.itc.it) For information on the NuSMV model checker: http://nusmv.irst.itc.it/
Introduction
Formal Verication
The design and implementation correct software (and hardware) is a difcult task. In some domains, errors are both difcult to detect using standard testing techniques and very expensive: Intel Pentium bug long list of space missions failed due to software problems ... In these domains, Formal Verication techniques are of help: the correctness of the (software or hardware) system mathematically proven. We concentrate on a specic Formal Verication technique, namely Model Checking.
Model Checking
Basic procedure: describe the system as Finite State Model (a Kripke model in our case). express properties in Temporal Logic. formal V&V by automatic exhaustive search over the state space. Drawback: State space explosion. Expressiveness hard to deal with parametrized systems. Industrial Success: From academics to industry in a decade. Powerful debugging capabilities. Easier to integrate within industrial development cycle.
Model Checker
q no! p p finite-state model q counterexample
Plan
Today: Symbolic Model Checking Models for Reactive Systems: Kripke Structures Properties of Reactive Systems: CTL, LTL Symbolic Model Checking Techniques: BDD-based and SAT-based techniques
Next Monday: The NuSMV Model Checker The NuSMV Open Source project The SMV language
T1, N2 turn=1
N1, T2 turn=2
C1, N2 turn=1
T1, T2 turn=1
T1, T2 turn=2
N1, C2 turn=2
C1, T2 turn=1
T1, C2 turn=2
User 1
User 2
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p q
4 3 p
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N1, T2 turn=2
T1, T2 turn=1
T1, T2 turn=2
N1, C2 turn=2
N1, N2 turn=0
C1, T2 turn=1
T1, C2 turn=2
T1, N2 turn=1
N1, T2 turn=2
T1, N2 turn=1
C1, N2 turn=1
T1, T2 turn=1
T1, T2 turn=2
N1, C2 turn=2
C1, N2 turn=1
T1, T2 turn=1
C1, T2 turn=1
T1, C2 turn=2
C1, T2 turn=1
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Synchronous Composition
Components evolve in parallel. At each time instant, every component performs a transition.
x=0
x=1
synchronous composition
x=0 y=a
x=1 y=a
y=a
y=b
x=0 y=b
x=1 y=b
Typical example: sequential hardware circuits. Synchronous composition is the default in NuSMV.
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Asynchronous Composition
Interleaving of evolution of components. At each time instant, one component is selected to perform a transition.
x=0 y=a asynchronous composition x=1 y=a
x=0
x=1
y=a
y=b
x=0 y=b
x=1 y=b
Typical example: communication protocols. Asynchronous composition can be represented with NuSMV processes.
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p p p
p p p
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Temporal Logics
Express properties of Reactive Systems nonterminating behaviours, without explicit reference to time. Linear Time Temporal Logic (LTL) intepreted over each path of the Kripke structure linear model of time temporal operators Computation Tree Logic (CTL) intepreted over computation tree of Kripke model branching model of time temporal operators plus path quantiers
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!done
done
done
!done
!done
!done
.....
!done done done done done !done !done
!done
done
done
done
done
done
done
!done
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LTL
finally P
globally P
FP
GP
next P
P until q
XP
IIT Delhi - India, Feb 6, 2004
PUq
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LTL: Examples
Safety: it never happens that a train arrives and the bar is up G(train-arrives bar-up) Liveness: if input, then eventually output G(input F output) Fairness: innitely often send G F send Strong fairness: innitely often send implies innitely often recv. G F send G F recv
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Example: Safety
N1, N2 turn=0
T1, N2 turn=1
N1, T2 turn=2
C1, N2 turn=1
T1, T2 turn=1
T1, T2 turn=2
N1, C2 turn=2
C1, T2 turn=1
T1, C2 turn=2
User 1
User 2
YES
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Example: Liveness
N1, N2 turn=0
T1, N2 turn=1
N1, T2 turn=2
C1, N2 turn=1
T1, T2 turn=1
T1, T2 turn=2
N1, C2 turn=2
C1, T2 turn=1
T1, C2 turn=2
User 1
User 2
Does F C1 hold?
NO
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Example: Liveness
N1, N2 turn=0
T1, N2 turn=1
N1, T2 turn=2
C1, N2 turn=1
T1, T2 turn=1
T1, T2 turn=2
N1, C2 turn=2
C1, T2 turn=1
T1, C2 turn=2
User 1
User 2
YES
25
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CTL
finally P globally P next P P until q
AF P
AG P
AX P
A[ P U q ]
EF P
EG P
EX P
E[ P U q ]
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CTL
Dualities: AGp AF p AXp Progressions: AF p EF p AGp EGp p AX AF p p EX EF p p AX AGp p EX EGp EF p EGp EX p
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Example: Safety
N1, N2 turn=0
T1, N2 turn=1
N1, T2 turn=2
C1, N2 turn=1
T1, T2 turn=1
T1, T2 turn=2
N1, C2 turn=2
C1, T2 turn=1
T1, C2 turn=2
User 1
User 2
YES
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Example: Liveness
N1, N2 turn=0
T1, N2 turn=1
N1, T2 turn=2
C1, N2 turn=1
T1, T2 turn=1
T1, T2 turn=2
N1, C2 turn=2
C1, T2 turn=1
T1, C2 turn=2
User 1
User 2
YES
30
Example: Liveness
N1, N2 turn=0
T1, N2 turn=1
N1, T2 turn=2
C1, N2 turn=1
T1, T2 turn=1
T1, T2 turn=2
N1, C2 turn=2
C1, T2 turn=1
T1, C2 turn=2
User 1
User 2
NO
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Example: Non-Blocking
N1, N2 turn=0
T1, N2 turn=1
N1, T2 turn=2
C1, N2 turn=1
T1, T2 turn=1
T1, T2 turn=2
N1, C2 turn=2
C1, T2 turn=1
T1, C2 turn=2
User 1
User 2
YES
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Model Checking
Model Checking is a formal verication technique where... ...the system is represented as Finite State Machine p
1
q
4 3 p 2
CTL:
...the model checking algorithm checks whether all the executions of the model satisfy the formula.
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35
p q
4 3 p
Idea: construct the set of states where the formula holds proceeding bottom-up on the structure of the formula q, AFq, p, p AF q, AG(p AF q)
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p q
p q
4 3 p
4 3 p
"q"
"AF q"
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"p"
1
p q
4 3 p
2 1
p q
4 1
2 3 p
4 3 p
"AF q"
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p q
The set of states where the formula holds is empty! Counterexample reconstruction is based on the intermediate sets.
39
40
41
p q
4 3 p
p
No counter-example found.
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p q
4 3 p
p
No counter-example found.
43
p q
4 3 p
p
No counter-example found.
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p q
4 3 p
2 1 2 3 4
p
1
q
2
p
3 4
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[[F p]]k =
i=0
p(si )
p
s0
= Gp
p
s1
k k
p
sk1
p
sk
[[G p]]k =
i=0
T (sk , si )
i=0
p(si )
p
s0
p
s1
p
sk1
p
sk
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T1, N2 turn=1
N1, T2 turn=2
C1, N2 turn=1
T1, T2 turn=1
T1, T2 turn=2
N1, C2 turn=2
C1, T2 turn=1
T1, C2 turn=2
User 1
User 2
YES
48
T1, N2 turn=1
N1, T2 turn=2
C1, N2 turn=1
T1, T2 turn=1
T1, T2 turn=2
N1, C2 turn=2
C1, T2 turn=1
T1, C2 turn=2
NO
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p q
4 3 p
Fair path: at least one state for each fi occurs an innite number of times Fair state: a state from which at least one fair path originates
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N1, N2 turn=0
T1, N2 turn=1
N1, T2 turn=2
C1, N2 turn=1
T1, T2 turn=1
T1, T2 turn=2
N1, C2 turn=2
C1, T2 turn=1
T1, C2 turn=2
not C2 not C1
YES
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