NTE2114 Integrated Circuit MOS, Static 4K RAM, 300ns

Description: The NTE2114 1024word 4bit static random access memory is fabricated using Nchannel silicon gate technology. All internal circuits are fully static and therefore require no clocks or refreshing for operation. The data is read out nondestructively and has the same polarity as the input data. Common input/output pins are provided. The separate chip select input (CS) allows easy memory expansion by ORtying individual devices to a data bus. Features D All Inputs and Outputs Directly TTL Compatible D Static Operation: No Clocks or Refreshing Required D Low Power: 225mW Typ D High Speed: Down to 300ns Access Time D TRISTATE Output for Bus interface D Common Data In and Data Out Pins D Single 5V Supply D Standard 18Lead DIP Package Absolute Maximum Ratings: Voltage at Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5V to +7V Power Dissipation, PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W Storage Temperature Range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to +150C Lead Temperature (During Soldering, 10sec), TL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300C Recommended Operating Conditions: Parameter Supply Voltage Ambient temperature Symbol VCC TA Test Conditions Min 4.75 0 Max 5.25 +70 Units V C

DC Electrical Characteristics: (TA = 0 to +70, VCC = 5V 5% unless otherwise specified) Parameter Symbol Test Conditions Min Max Units Logical 1 Input Voltage Logical 0 Input Voltage Logical 1 Output Voltage Logical 0 Output Voltage Input Load Current Output Leakage Current Power Supply Current Power Supply Current VIH VIL VOH VOL ILI ILO ICC1 ICC2 IOH = 1.0mA IOL = 2.1mA VIN = 0 to 5.25V VO = 4V to 0.4V, CS = VIH All Inputs = 5.25V, TA = 25C All Inputs = 5.25V, TA = 0C 2.0 0.5 2.4 10 10 VCC 0.8 0.4 10 10 95 100 V V V V A A mA mA

AC Electrical Characteristics: (TA = 0C to +70C, VCC = 5V 5%, Note 2 unless otherwise specified) Parameter Symbol Test Conditions Min Max Units READ CYCLE Read Cycle Time (WE = VIH) Access Time Chip Select to Output Valid Chip Select to Output Active Chip Select to Output TRISTATE Output Hold from Address Change WRITE CYCLE Write Cycle Time Write Pulse Width Write Recovery Time Data SetUp Time Data Hold Time Write Enable to Output TRISTATE Write Enable to Output Valid tWC tWP tWR tDS tDH tWOT tWO 300 150 0 150 0 0 80 100 ns ns ns ns ns ns ns tRC tA tCO tCX tCOT tOHA 300 20 0 10 300 100 80 ns ns ns ns ns ns

Capacitance: (TA = +25C, f = 1 MHZ, Note 3 unless otherwise specified) Parameter Symbol Test Conditions Min Input Capacitance Output Capacitance Note 1: Typical values at TA = +25C. CIN COUT All Inputs VIN = 0V VO = 0V

Max 5 10

Units pF pF

Note 2: All input transitions 10ns.Timing referenced to VIL(MAX) or VIH(MIN) for inputs, 0.8V and 2V for output. For test purposes, input levels should swing between 0V and 3V. Output load = 1 TTL gate and CL = 100 pF. Note 3: This parameter is guaranteed by periodic testing.

Truth Table: CS H L L L WE X L L H I/O HiZ H L DOUT MODE Not Selected Write 1 Write 0 Read

Functional Description: Two pins control the operation of the NTE2114. Chip Select (CS) enables write and read operations and controls TRISTATING of the dataoutput buffer. Write Enable (WE) chooses between READ and WRITE modes and also controls output TRISTATING. The truth table details the states produced by combinations of the CS and WE controls. During READcycle timing, WE is kept high. Independent of CS, any change in address code causes new data to be fetched and brought to the output buffer. CS must be low, however, for the output buffer to be enabled and transfer the data to the output pin. Address access time, tA, is the time required for an address change to produce new data at the output pin, assuming CS has enabled the output buffer prior to data arrival. Chip Selecttooutput delay, tCO, is the time required for CS to enable the output buffer and transfer previously fetched data to the outputpin. Operation with CS continuously held low is permissible. Writing occurs only during the time both CS and WE are low. Minimum write pulse width, tWP, refers to this simultaneous low region. Data setup and hold times are measured with respect to whichever control first rises. Successive write operations may be performed with CS continuously held low. WE then is used to terminate WRITE between address changes. Alternatively, WE may be held low for successive WRITES and CS used for WRITE interruption between address change. In any event, either WE or CS (or both) must be high during address transitions to prevent erroneous WRITE.
Pin Connection Diagram

A6 1 A5 2 A4 3 A3 4 A0 5 A1 6 A2 7 CS 8 GND 9

18 VCC 17 A7 16 A8 15 A9 14 I/O 1 13 I/O 2 12 I/O 3 11 I/O 4 10 WE

10

18 .300 (7.62) .945 (24.0) .260 (6.6)

.160 (4.06) Max

.100 (2.54) .800 (20.32)

.115 (2.92) Min