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Introduction to TM Tanner Tools Pro

Express Training Volume 1 Design Capture and Simulation

About Tanner Research

Tanner EDA --- IC Design Tools

Electronic Design Automation Software & Training

Tanner CES --- Consulting & Engineering Services

Development, IP & Consulting for High Performance ASICs Technology Research for Government and Commercial Sectors. MEMS fab. Low and Medium Volume IC Fabrication, FPGA and Mixed-Signal ASIC Conversion Services
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Tanner Labs --- Advanced Technologies

Manuflex --- Manufacturing Services

Comprehensive Training

Day 1: Front End Design


System Setup & Requirements Begin S-Edit: Schematics, Symbols Application Setup Test-bench, Integration to T-Spice T-Spice Simulation & Analysis Optimization Internal Tables Accuracy, Convergence Control Intro to External Models

Day 3: Layout Verification & SPR


Design Rule Checking Design Rule Setup & Optimize Extract Post-layout Simulation LVS Check, Debug Introduction to T-Cells Place & Route (SPR)

Day 4: Advanced Topics


. How UPI works

Day 2: IC Layout with L-Edit


Polygon, Cell Handcrafting Design Database Components L-Edit Application Setup L-Edit Technology Setup Workgroup Management Tape-out Cross-section Viewing Intro to UPI Intro to T-Cells 3

. Creating Interpreted Macros . Creating T-Cells . Layout composition functions . Creating Compiled Macros

Day 5: Advanced Topics


. Using Visual Studio . Advanced C Review . Debugging Macros . Common & Advanced UPI tasks

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Course Objectives

Establish an overall understanding of IC design using Tanner Tools. Master the basic IC design operations through hands-on exercises. (abridged) Complete an example design from concept to tape-out. (abridged) Get your chip design questions answered.

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Hardware Requirements

Tanner Tools Minimum Requirements


Windows 98/ME/NT/2000/XP Pentium II machine or equivalent 128MB RAM (256MB RAM for DRC) 250MB HD space to install the program (varies with packages) 3 button mouse, or Intellimouse Video card with at least 16MB Pentium III machine or higher with Windows 2000 1GHz or higher 512MB RAM or higher Intellimouse - 2 button mouse with wheel used as 3rd button Latest video card with at least 32 MB (NVIDIA Quadro 2 Pro or Matrox Millennium G400) 1280 x1024 Resolution - True Color (24-bit)
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Tanner Tools Recommended Requirements


Design Concept
The objective in this class is ...to build a trivial circuit
...from concept ... to tape-out on a deadline.

Circuit Design /

A 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

B 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

C 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Z 0 0 0 1 0 0 0 1 0 0 0 1 1 1 1 1

Product" definition

AO22 chip AND-OR logic function. Timing=? Power=? I/O characteristics? Technology: 0.25um n-well CMOS Schedule.
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Design Flow
design concept S-Edit schematic entry T-Spice simulation EDIF/TPR netlist SPR SDL

Librarian / Technologist Tasks Device symbols Subcircuit schematics & symbols T-Spice device models L-Edit application setup technology setup device/gate/block layouts UPI macros cross-section tech setup DRC rule setup Extract rule setup LVS setup plot setup GDSII layer numbers
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polygon layout Cross-section view DRC

Extract LVS plot tape out

Tanner Tools Pro


T-Spice ProTM
Schematic Schematic Editor Editor EDIF VHDL /Verilog
TM S-Edit S-EditTM

TM

High-Performance High-Performance Circuit CircuitSimulator Simulator SPICE

TM T-Spice T-SpiceTM

TM W-Edit W-EditTM

Waveform Waveform Viewer Viewer

L-Edit ProTM
Symbol Schematic Device model Process setup Layout UPI

Layout Layoutvs. vs. Schematic Schematic

LVS LVS

L-Edit VerifyTM
Design DesignRule Rule Checker Checker

Library

Device Device Extractor Extractor

Extract Extract

DRC DRC

GDSII CIF (DXF)

Place Placeand andRoute Route

SPR SPR

Custom Layout Editor Custom Layout Editor Cross Section Viewer


Cross Section Viewer User Programmable Interface User Programmable Interface

TM L-Edit L-EditTM

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S-Edit Schematic Editor

Easy to use

commands & shortcuts like L-Edit

One file for a complete design

portable with T-Spice and W-Edit

Integration

Basic features Limited

capabilities capacity
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Beginning with S-Edit


Opening S-Edit

Circuit Design /

Desktop Shortcut
-or-

Start menu
-or-

double-click on .SDB file Menus


-or-

Commands

Toolbars
-or-

Shortcut Keys

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S-Edit window Regions

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Tanner Tools Help

Adobe Acrobat

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Circuit Design / S-Edit / Hierarchy Schematics contain instances of Modules represented by Symbols

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Circuit Design /

Designs in S-Edit

A .SDB file contains a complete design. The pieces used to construct hierarchical design schematics are known by various equivalent names:

Modules Other common terms: Cells, or Components, or Blocks, or Subcircuits Active (influence the netlist output) Inactive (for Annotation, visual only)

Objects in Schematics and Symbols (slide)


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Symbol and schematic objects diagram S-Edit .SDB Files .SDB Modules schematic
pages info

info

symbol
Active: port Inactive: property line info box polygon circle comment

Active: Inactive: port line wire box label polygon node cap circle instance comment info

Verilog netlist .VLG VHDL netlist .VHD Place & Route .EDN or .TPR
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T-Spice / LVS .SP

EDIF schematic .EDS

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Selections
Selecting Objects

Circuit Design / Schematic /

Selection Tool
F2 shortcut key

Left or Right Mouse button


Suggestion: Use the right mouse button for selecting.

<ctrl>a selects all; <alt>a deselects all.

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Instances

Circuit Design / Schematic /

Placing an instance
i shortcut key Tool button in drawing tools Symbol browser

Instance name vs. module name Automatic Instance names Editing Properties on instances
Ctrl-E shortcut key eyeglasses tool

Inheritance of properties
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Wires
Wires

Circuit Design / Schematic /

Drawing wires
wire spool Tool button F3 shortcut

Node Labels
N Tool button F4 shortcut key

Node Caps
stops global nodes from propagating upward stopsign Tool button F5 shortcut key

Ports
4 Tool buttons F6 shortcut key (repeat F6 to cycle)

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Editing Commands
for wires, lines, shapes

Circuit Design / Schematic /

Move: Middle mouse button Stretch: Middle mouse button on an edge


Flip: h, v shortcut keys Rotate: r shortcut key Copy: <ctrl>c Cut: <ctrl>x Paste: <ctrl>v Duplicate: <ctrl>d
Remembers offset from the previous object.

Undo: <ctrl>z Redo: <ctrl>y Edit Object (properties): <ctrl>e


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Viewing Commands
<Home> key show full view <+> key zooms in <-> key zooms out Arrow keys pan up / down / right / left z zooms to drag box x key exchanges previous view w zooms to selected object <spacebar> redraws the screen

Circuit Design / Schematic /

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Traversing Schematics
File/Open
Multiple files can be open at the same time. Only one module in one file is visible at a time. Multiple S-Edit sessions can be open at once (no paste).

Circuit Design /

Module/Open
Changes the visible (editable) module. Also can change to another open file. Open by selection: select instance, open it: <click>, o, <enter> With nothing selected: toggle between two modules: o, <enter> By name: type the beginning of the module name until unique

o, character, <enter>

Find
f shortcut key Helps traverse up and down the hierarchy.
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Circuit Design / S-Edit / Modules


Symbol (outside)

Schematic (inside)

name:

NAND2

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Symbol Editing

Circuit Design / Symbols /

".SDB" File (Schematic DataBase) (diagram) / Module /Symbol Active objects: Port, Info, Property Operations are like in a Schematic

Symbols have more inactive shapes . Symbols have no wires. Symbols have properties.
? shortcut key toolbar buttons

View switching from schematic to symbol

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Symbol Properties
Inactive objects: (do not influence the netlist)

Circuit Design / Symbols /

Box
<shift>F2 shortcut

Circle
<shift>F3 shortcut

Comment (text)
<shift>F4 shortcut

Polygons
<shift>F5 shortcut (cycles)

Lines (do not make connections)


<shift>F6 shortcut (cycles)

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Circuit Design / Symbols / Symbol Properties Working with Properties


Escape character Newline, tab.

\n, \t

M, NMOS, L=, W=, AS=, AD=, PS=, PD=, [spaces]

Literal text, written to the SPICE file unchanged. Takes the name of the nodes connected to the pins corresponding to the ports named D, G, S and B. The values of the properties named W and L Predefined properties that allow internal information (such as the name of the file, module, page, and instance) to be inserted in the output string. Default values assigned to each property. # - An incremented integer that counts the instances of the module.

%{D}, %{G}, %{S}, %{B}

${W}, ${L}

${Instance}, ${Page}, ${Info}, ${Author}, ${File}, ${Modified}

W=1.2u, L=0.5u, name=${instance}, model=NMOS

M# %{D} %{G} %{S} %{B} ${model} L=${L} W=${W}

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NMOS symbol

origin

Note grid spacing of pins.

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AO22 Symbol
origin Note grid spacing of pins.

2 grids 10 grids
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Circuit Design / Symbols /

Symbol Properties
F7 shortcut to add <ctrl>e to edit

Properties
Some properties are arbitrary (user defined)
examples: L, model, name

Pre-defined property names


SPICE OUTPUT (T-Spice netlist format) SPICE PARAMETER (for hierarchical parameters) TPR OUTPUT (TPR netlist for SPR/BPR) EDIF PRIMITIVE (EDIF netlist for SPR/BPR) PAD (for SPR pad locations) VHDL PRIMITIVE (VHDL netlist for logic simulation)
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NAND2 Schematic

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AO22 Schematic

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Good design practices


Working directory

Circuit Design /

Be aware of it; Keep it pointed to the project directory. Changed by: OPEN FILE, any file system access. Visible & reset by: OPEN FILE, SAVE AS. It is best to match so layout & verification can be done bottom-up. use large text use large snap grid

Hierarchy for layout

Readability

Revision control - in the info form Comments

design notes, truth tables, copy of symbol in schematic Layout instructions, inspection checklist Critical nets, matched devices
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Interface to T-Spice
Testbench (a schematic, or an .sp file)

Circuit Design /

Voltage & Current Sources T-Spice device library (file)


.model .lib .endl

Control card modules, analysis types .Measure

Exporting the schematic Simulation Waveform Cross Probing

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W-Edit Waveform Viewer


Integrated With T-Spice and S-Edit Multiple Window and Chart Viewing Customizable Chart and Trace Display Trace operations

Circuit Design/W-Edit

expression defined traces arithmetic traces

Pan, Zoom, Expand/Collapse Features Spectral Analysis Cursors and Measurements Report Ready Printer Output OLE Document Embedding Default settings
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W-Edit Window Regions

Circuit Design/W-Edit

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Spectral Analysis

Circuit Design/W-Edit

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AO22_tb Test Bench

Source_v_dc

Source_v_bit hightime=50n lowtime=50n set bit pattern

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AO22_tb.SP file

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Waveform Cross Probing

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Waveform Cross Probing

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T-Spice Circuit Simulator


Performance

Circuit Design/T-Spice

High Speed Table Based Simulation User Defined C-language Models Queuing for Batch Simulation HSPICE Compatible Industry Standard Transistor Models (ex. BSIM3v3) User Defined Models Measurement (.measure) Parametric Analysis Fourier Analysis Monte Carlo Analysis Optimization
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Compatibility

Capability

T-Spice Circuit Simulator


Launch from S-Edit Automatic netlist generation Color-coded/Syntax highlighting text editor Command generator tool Click-back to syntax error Run-time waveform display Simulation manager Batch Queue

Circuit Design/T-Spice

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Introduction to T-Spice Window


Launching T-Spice

Circuit Design/T-Spice

Desktop Shortcut Start menu Double-click on .SP file Drag-and-drop any file onto T-Spice shortcut

Simulation History Input Parameters Drag and Drop Editing Tracing syntax errors

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T-Spice Window Regions


Menu bar Toolbars Text Windows

Circuit Design/T-Spice

Simulation Output

Simulation Manager Status Bar


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T-Spice Command Tool

Circuit Design/T-Spice

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T-Spice Header File


Standard T-Spice input file contains initialization commands and options.

Circuit Design/T-Spice

Processed before input netlist

Recommended options to put in header files:


.options echo .options list

$echo all input $list all devices

.options verbose=2 $Verbose printout of runtime information .options search = C:\Tanner\Library $set search path for .lib files

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T-Spice Analysis
Case Sensitivity

Circuit Design/T-Spice

Node and Device names:


Default is case insensitive. .options casesensitive or command line switch

Key words are not case sensitive. DC operating point - .op Transient - .tran DC transfer - .dc AC analysis - .ac
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Analysis Types

Measurements

Circuit Design/T-Spice

Measurement (.measure)
Find-When; Trigger-Target

.measure tran delaytime


+ trig v(1) val=2.5 fall=3 + targ v(2) val=2.5 rise=3

Signal statistics (max, min, avg, pp, rms, etc.)


.measure ac maxgain max vm(out)

Expression evaluation
.param tf= 1E-6 * sin(pi/ 2)

Error function (relative difference between outputs)


.measure tran v1 v2 err v(1) v(2)

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Repeated Simulations
Parameter Sweep (.step / .data / .sweep)

Circuit Design/T-Spice

Model/device parameter Source temperature

.alter Optimization Monte Carlo Analysis

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Internal/External Tables
Internal Tables (vs. Direct models) - charges and currents at device terminals) are computed directly

Circuit Design/T-Spice

Direct mode (turn tables off) .options deftables=0 (default 1=tables on) Table mode by instance or by device tables=1 (1=tables on) Finer table resolution .gridsize MOS 256 256 128 (default is 64, 128, 10) High voltage (default +/- 5 volts) .vrange MOS 15

Generate Table / External Tables - data points are read or interpolated from precomputed tables stored in memory.
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Accuracy

Circuit Design/T-Spice

Table vs. Direct Model Evaluation


Table mode is 1-2 times faster than Direct mode Accuracy is compromised, generally 1%-2% model accuracy May introduce switching behavior for some circuits. Best practice if repeated simulations are done for the same circuit, run once in direct mode, and then in table mode to verify that the accuracy is within acceptable limits

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Convergence Control

Convergence
Visibility

Circuit Design/T-Spice

.options acct verbose=2 .options list - printout detailed information about every element in the netlist

Ramp power supplies


.tran/powerup Source stepping .option minsrcstep

Forcing nodes
.nodeset starts and iterates to an operating point .ic forces the operating point

Iteration limits
.options numnd (DC) numnt (transient) .options extraiterations=X X is an integer, recommended value < 10
z

tells T-Spice to perform extra Newton Raphson solver iterations after convergence has been achieved. Increases accuracy

.options gmin & gmindc


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Accuracy vs. Speed


3 meta-options to control the settings of other options, providing an easy and reliable way to increase the speed/accuracy of simulations.

Circuit Design/T-Spice

Fast - sacrifices accuracy for the sake of speeding up simulations.


Recommended only for very stable circuits.

Accurate - increases accuracy of simulations with some slow-down (about 50%).


Recommended for sign-off/final simulations.

Precise - Maximizes accuracy with large performance degradation.


Recommended for very small circuits or when performing device or transistor characterizations.

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Digital Simulations
Circuits that contain very square linear voltage or current source pulse waveforms, with fast rise and fall times, will greatly benefit from the delta-voltage based timestepping algorithm

Circuit Design/T-Spice

lvltim = 1 : Delta voltage algorithm


Recommended for digital-like circuits.

lvltim = 2 : Charge based algorithm


T-Spice default.

lvltime = 3 : Delta voltage plus time reversal.


Provides increased accuracy over lvltim 1 setting.

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External Models
Purpose of external models

Circuit Design/T-Spice

New or Improved devices Higher level blocks or gates Multiple energy domains, ex. mechanical, thermal (MEMS) compiled or interpreted Unlimited number of terminals User defined model & device parameter names Support for parasitics, internal nodes, noise models User defined small-signal parameters Automatic table generation for speed
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C (or C++) language device models

Model Features

External Models
Writing an external model

Circuit Design/T-Spice

Examples
C:\Tanner\TSpice90\extmod\win32\ resist.c, switch.c, diode.c, mos1.c, vco.c Gate model example

Template file
...\template.c

Using an external model


.model x instance card (like a subcircuit)

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T-Spice Exercise - Simulation


Export NAND2 schematic

Circuit Design/T-Spice

- Use T-Spice Insert Command Tool to Setup Testbench

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T-Spice Exercise - Simulation

Circuit Design/T-Spice

Add voltage supply VDD

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T-Spice Exercise - Simulation


Add input on A

Circuit Design/T-Spice

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T-Spice Exercise - Simulation


Add input on B

Circuit Design/T-Spice

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T-Spice Exercise - Simulation

Circuit Design/T-Spice

Include model file (.lib or .include)

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Add Transient analysis command (.tran)

T-Spice Exercise - Simulation

Circuit Design/T-Spice

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Add print command (.print)

T-Spice Exercise - Simulation

Circuit Design/T-Spice

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Measure the timing difference between input falling edge & output rising edge

T-Spice Exercise - Simulation

Circuit Design/T-Spice

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T-Spice Exercise - Simulation

Circuit Design/T-Spice

Run Simulation View Waveforms in W-Edit. Diff = 0.612 ns

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Circuit Design/T-Spice (Optional)

T-Spice Exercise Optimization

Optimization specifications: - Optimize: the Length of the PMOS transistor - Goal: Minimize the delay so that diff is 0.40 ns instead

of 0.612 ns Optimization Preparation - Change the PMOS length values to variables in the netlist: MP1 OUT IN1 VDD VDD PMOS L='Lp' W=8U MP2 OUT IN2 VDD VDD PMOS L='Lp' W=8U - Define the variables Lp by adding: .param Lp=2u

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Circuit Design/T-Spice

T-Spice Exercise - Optimization

Define the optimization name Define the optimization goal

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Circuit Design/T-Spice

T-Spice Exercise - Optimization

Define the optimization Variables Define the optimization algorithm

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Circuit Design/T-Spice

T-Spice Exercise - Optimization

Insert the optimization statement

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Circuit Design/T-Spice

T-Spice Exercise - Optimization

Run the simulation

Change the optimization goal in the netlist to 0.20 ns and run the simulation again. Is the optimizer able to reach the goal?
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Software Solutions

Express Training Volume 2 Layout Editing and Verification

Introduction to TM Tanner Tools Pro

Design Flow
design concept S-Edit schematic entry T-Spice simulation EDIF/TPR netlist SPR polygon layout Cross-section view DRC Extract LVS plot tape out
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Librarian / Technologist Tasks Device symbols Subcircuit schematics & symbols T-Spice device models L-Edit application setup technology setup device/gate/block layouts UPI macros cross-section tech setup DRC rule setup Extract rule setup LVS setup plot setup GDSII layer numbers
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L-Edit Layout Editor

Full Custom All-Angle Layout Editor


Technology Configurable Fully Hierarchical Design Navigator Customizable Keyboard, Palette, Rulers User and Workgroup configurations Command Line Interface MDI-Layout & Text GDSII, CIF, EPS & DXF support User Properties on objects UPI programmable Cross-section Viewer Advanced Editing Support

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Class Design Project

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L-Edit Colors - Your choice


Traditional style - black background - cross-hatch fills Windows style - white background - solid fills

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Introduction to L-Edit
Launch L-Edit

Layout/

Desktop Shortcut Start menu ".TDB" (Tanner layout Database) File Double-click on .TDB File Open Drag-and-drop onto application or desktop icon Design Navigator CellOpen o hotkey when instance is selected
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Open Files

Open cells

L-Edit Window Regions

Toolbars

Menu bar Locator Layer Palette Aerial View Toolbar Text Windows / Layout Windows Drawing tools Design Navigator

Details button Status Bar Mouse Buttons Bar


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Tanner Tools Help

Previous/next view Find (within document) First/last page Previous/next page

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L-Edit Files
A

file corresponds to an entire design

Layout cells and process information Locked by single editor Data transferred between files via:
copy across (also instance across) File Replace Setup

Data shared between files via:


XREF cells

Files have Info and Properties. An L-Edit file corresponds to a single .TDB file on disk.

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View Operations

Layout/

tab

Mouse Wheel Vertical Pan Shift+Mouse Wheel Horizontal Pan Ctrl+Mouse Wheel Zoom In/Out 96
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Selection
Objects

Layout/

Selecting

Selection Tool
No default shortcut key but you can assign one yourself

Suggestion:
Use the right mouse button for selecting.

ESC will cancel a drawing or editing operation. ESC again switches to the selection tool. <Ctrl+A> selects all <Alt+A> deselects all
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Selection

Layout/

Selecting Objects
Cycling of selections
Continue to click without moving the mouse Watch Status Bar Last select in the cycle is no selection and cycle repeats

Add to Selection

<Shift Right Mouse Button> Watch Mouse Button Bar and cursor pictures

Remove from Selection Select Edge - <Ctrl> Add Edge - <Ctrl+Shift> Remove Edge - <Ctrl+Alt>
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<Alt Right Mouse Button>

Drawing
Drawing Objects:
Pick tool for drawing object type, Pick layer.
Box
z <left mouse drag>

Layout/

Polygons: Orthogonal / 45 / all-angle


z <left click>, <left click>, ,<right click>

Wires: Orthogonal / 45 / all-angle Wires (width)


z <left click>, <left click>, ,<right click>

Circle, Pie wedge, Torus Port Ruler Instance


z tool button or i shortcut z Also drag and drop from the Design Navigator

Cursor indicates drawing mode:


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Selection Mode Drawing Mode


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Ports
Port = region + text

Layout/

The only text construct in L-Edit The region specifies attachment to the drawings.
Rectangle -or- Line -or- Point

Ports are placed on layers


Layer is important

Text is oriented Uses:


Comments Node names Cell boundaries I/O Ports/Pins
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Edit Operations

Layout/

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Draw Operations

Layout/

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Editing
Editing Tools:
Duplicate Ctrl+D Rotate 90 degrees - R Rotate any angles Ctrl+R Flip Horizontal - H Flip Vertical - V Horizontal Slice Shift+- _ Vertical Slice Shift+\ | Nibble Alt+X Merge Boolean/Grow Operation - B Group Ctrl+G Ungroup Ctrl+U Edit Object Ctrl+E Move By - M
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Layout/

Alignment Toolbar MBB


Editing Tools:

Layout/

Selected Objects

Align uses the MBB of the selected objects


Align Left Align Middle Align Right
MBB

Left

Middle

Right Top

Align Top Align Center Align Bottom

Selected Objects

Center

Bottom
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Alignment Toolbar
Editing Tools:

Layout/

Selected Objects

MBB

Align uses the MBB of the selected objects


Horizontal

Distribute Horizontally Distribute Vertically

Vertical

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Alignment Toolbar
Editing Tools:

Layout/

Selected Objects

Align uses the MBB of the selected objects


Horizontal
Aligns to the bottom left corner of the leftmost object

Abutment is the MBB of all objects on the icon layer This is useful for overlapping.

Tile Horizontally Tile Vertically

Aligns to the bottom Vertical left corner of the bottommost object

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Alignment Toolbar
Editing Tools:

Layout/

Selected Objects

Align uses the MBB of the selected objects


2D Array

Sorts objects into rows starting with the bottom leftmost object. If the center of the object is within the objects MBB then they are on the same row. This is useful for odd-even memory arrays and non-simple arrays.

Tile 2-D Array


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Setup Operations

Layout/

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Application Setup
Application setups are the settings common to a user for all designs.

Layout/

Setup application is saved in a personal configuration (also workgroup). Toolbar locations & visibility are included. Status bars visibility is included. Recently used file list is included. No save is required.

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General

L-Edit/Setup/Application/
Non-default values indicated
Paste to Cursor When pasting, objects are attached to the cursor and you can move them around and click to place them. When this is off, the objects get pasted to the center of the screen. Active-push rubberbanding All draw & edit operations are two separate clicks (Start click & end click). When this is off, all draw & edit operations are a single click (Start click, hold button down, release button to end).

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Keyboard

L-Edit/Setup/Application/

Dont forget to press the assign button.

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Mouse

L-Edit/Setup/Application/

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Warnings

L-Edit/Setup/Application/

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UPI

L-Edit/Setup/Application/

Update display When this is off, the screen is not redrawn when a UPI macro is running. This can make some macros run faster. Show warning dialog boxes When this is off, all dialogs are suppressed when a UPI macro is running. This is useful for batch processing.

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Rendering

L-Edit/Setup/Application/
Hide Instance Larger value ) Faster Rendering Cache Instance Larger value ) Faster Rendering Optimal is 250-750 Hide objects Larger value ) Faster Rendering If you have trouble seeing vias, reduce this value or switch this value off when zoomed in and turn on when zoomed out. Redraw Active only ) Faster Rendering Fill / Interrupt / Show design Off ) Faster Rendering May not feel faster See Improving Rendering Performance Application Note for more details.

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Selection

L-Edit/Setup/Application/

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Cell Operations

Layout/

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Design Navigator

Efficiently traverse the design hierarchy

Drag and drop cells into layout from library files, other design files, or current design database Conveniently access cell operations Lock & unlock cells to protect the design from changes
Locked XrefCell
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View Type Collapse All Expand All New Cell Delete Cell Save as Text Show all Cells Find Cell

Design Navigator

View Types
Top Down Date Modified

Bottom Up

DRC Status

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Configuration Management

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Layout Editing Exercise

Layout /

Create a NAND gate layout


Create a PMOS0p96x0p24 cell Create a NMOS0p96x0p24 cell Create a NAND2 cell


Instance two PMOS0p96x0p24 and two NMOS0p96x0p24

Create a AO22 layout

Connect three NAND2 to AO22


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Schematic-Driven Layout

Import SPICE

Hierarchical

Optionally create layout


Devices: T-Cells Instances Floorplanning

Show flylines Find nodes/pins

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Technology Setup
Technology setups are settings which are stored in the design file, and commonly shared with other design files, including:

Layout/

Technology name Units and Grids


internal unit (lambda) micron display unit

Default settings External libraries Layers & Palette Design Rules


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Technology

L-Edit/Setup/Design/
Scaleable lambda-based units

Typical micron-based units

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Grid

L-Edit/Setup/Design/

These are in Micron units.


The display units can be set to a variety of units Microns, Mils, Millimeters, Inches, Centimeters, and Internal Units.

Changing display units does not change the database. It is for viewing only

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Grid

L-Edit/Setup/Design/

0.12 um

0.03 um

Manufacturing grid is used to check for off-grid, snap to grid, and approximating curves. Set this value to the smallest resolution of your foundry.

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Selection

L-Edit/Setup/Design/

Selection range during select operations, only select objects within this range. This is useful when cycling through selections. Edit range Uses the largest of the two values. When the cursor is this close to an objects edge, the middle mouse button will do an edit operation. Farther than this distance and it will be a move operation. Select drawn objects Leaves objects selected after drawn. This is useful when drawing an object and then moving it into place.

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Drawing

L-Edit/Setup/Design/

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Palette

L-Edit/Setup/

Windows style palette

Traditional style palette

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File Operations

Layout/

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Technology Objects Diagram


.TDB file (Cells) grid layers drawing defaults design settings technology setup import/export options DRC rules ledit.ini application settings .GDS GDSII

Ledit.tdb

TTX and RUL will not be supported in v11.

.TTX .RUL

Other .TDB
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L-Edit Technology Propagation

Select technology settings from a .tdb to apply to a new file (FileNew). This can be any .tdb file regardless if it has layout in it or not. Default technology setup

C:\Tanner\LEdit101\ledit.tdb Used when L-Edit is started with the executable & no .tdb file.

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L-Edit Technology Propagation

FileReplace Setup applies complete or partial technology setups to an existing file from a .tdb file (or a .ttx file).

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L-Edit Technology Propagation

File Export Setup writes complete or partial technology setups of an existing file to a .ttx file (text file). TTX format does not support all setup parameters.

Recommend to use .tdb for all technology propagation and not .ttx.

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Import/Export Mask Data


FileImport Mask Data

Layout /

FileExport Mask Data

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Tape-out
GDS

Layout /

GDS file can contain all cells from the TDB, or just a specific cell tree.

CIF: Caltech Interchange Format (ASCII) It is generally a good idea to check for off-grid objects, and self-intersecting polygons before final tape-out.

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Cross-Section Viewer
Viewing the 3rd dimension of layout. Used in layout, documentation, parasitics.

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Cross-Section Viewer
Introduction to process technology

Layout/

The class example technology is 0.25 um CMOS. Use cross-sections to learn the layers & structures 3 operations
gd = Grow / Deposit (color from layer, no shapes) id = Implant / Diffuse (color & shapes from layer) e = Etch (shapes from layer, no color)

.XST Process Definition file

Specify: layer, depth, angle[80], offset (+)[0] Label field is optional.

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L-Edit Cross-Section viewer

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# File: Tech4class.real.xst # Real" version to show correct process order # **************************************************************************************** # L-Edit #Step Layer Name Depth Label [Angle[offset]] Comment #------ ------------------------------------ -------- ---------------------- ------------------------------------gd "ChipSubstrate 2.50 p# 1. Substrate = NOT(NotExists) id "Deep N Well" 1.90 n85 # 2. Deep N-Well Implant id "P Well" 0.95 p85 # 3. P-Well Implant inside Deep N-Well id "N Well" 0.95 n85 # 4. N-Well Implant e "Not Active" 0.40 # 5. Field etch = NOT(Active) gd "Not Active" 0.40 # 6. Field oxide e "Active" 0.40 101 0.05 # 7. Device areas gd 0.05 # 8. Thin Gate oxide e "Not Thin Channel 0.05 # 9. Thin Gate oxide etch = NOT(Active ANDNOT Thick_Active) gd "Thick Active" 0.15 # 10. Thick Gate oxide e "Not Thick Channel" 0.15 # 11. Thick Gate oxide etch = NOT(Active AND Thick_Active) gd "Poly" 0.18 # 12. Polysilicon e "NotPoly" 0.18 80 0.032 # 13. Poly etch = NOT(Poly) id pdiff" 0.15 p+ # 14. P+ Implant = (P Select) id "ndiff" 0.15 n+ # 15. N+ Implant = (N Select) gd 0.32 # 16. Contact Oxide e "Poly Contact 0.32 85 # 17. Poly Contact holes e "Active Contact" 0.32 85 # 18. Active Contact holes gd "Metal1" 0.32 # 19. Metal1 e "Not Metal1" 0.32 # 20. Metal1 etch = NOT(Metal1) gd 1.00 # 21. Metal1 to Metal2 oxide e "Via1" 1.00 85 # 22. Via1 holes gd "Metal2" 1.10 # 23. Metal2 e "Not Metal2" 1.10 # 24. Metal2 etch = NOT(Metal1)

Cross Section Rules File

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Tools Operations

Layout/

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UPI

User Programmable Interface

Purpose: to extend the capabilities of L-Edit

Automate repetitive tasks


User Defined Hot Keys

Add higher level algorithms for construction & verification


Parameterized Layout Generation Batch Verification Advanced Analysis Library of Macros Intellectual Property with password protection

Palettes Pop-up dialogs Interpreted (C) or Compiled (C++)

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UPI macro example

module Contact_module { #include "ldata.h" #include "lupi_usr.h" void Contact_Active_Metal1 ( ) { /********************************************************************/ LCell Cell_Now = LCell_GetVisible ( ); LFile File_Now = LCell_GetFile ( Cell_Now ); LLayer Layer_Active = LLayer_Find ( File_Now, "Active" ); LLayer Layer_Metal1 = LLayer_Find ( File_Now, "Metal1" ); LLayer Layer_ActCnt = LLayer_Find ( File_Now, "ActiveContact" ); LLayer Layer_N_Sel = LLayer_Find ( File_Now, "N Select" ); LPoint Point_Cursor = LCursor_GetPosition ( ); LCoord X, Y; /********************************************************************/ X = Point_Cursor.x; Y = Point_Cursor.y; LBox_New ( Cell_Now, Layer_ActCnt, -1 + X, -1 + Y, 1 + X, 1 + Y ); LBox_New ( Cell_Now, Layer_Metal1, -2 + X, -2 + Y, 2 + X, 2 + Y ); LBox_New ( Cell_Now, Layer_Active, -3 + X, -3 + Y, 3 + X, 3 + Y ); LBox_New ( Cell_Now, Layer_N_Sel , -5 + X, -5 + Y, 5 + X, 5 + Y ); } void cnt_main ( void ) { /********************************************************************/ LMacro_BindToHotKey ( KEY_F1, "Contact, Active-Metal1", "Contact_Active_Metal1" ); } /********************************************************************/ } cnt_main ( );

C:\Tanner\LEdit101\ Samples\UPI\ intrpted\ contact\contact.c

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UPI menu: Tools / Macro


It should only show Place via

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T-Cells

Concept

Layout generation macros that are specific to a design and process. Encapsulated in the TDB file (goes with the file for interpreted T-Cells) When creating a cell in L-Edit, you can make a geometry cell (cell) or parameterized cell with code (T-cell) Type - Boolean, Integer, Float, String, Layer Default Value When generating a new T-Cell, parameter is initialized to this value
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T-Cell Parameters

T-Cells
Terminology

Cell a traditional cell with layout objects T-Cell a cell with layout generation code. The code is executed when a T-Cell is instanced and the resulting cell is what is instanced in the cell Auto-generated cell A generated version of a T-Cell with specific values for each parameter (Normally hidden)

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Using T-Cells
T-Cell: Box Parameter Definition

Auto-Generated Cell: Box_Auto_0.36_0.36

W = 0.36 L = 0.36
Generator Code

Auto-Generated Cell: Box_Auto_2_1

. . box(0,0,L,W) . .

Geometry Cell: Cell1

Instance Parameter Values

Instance Parameter Values

W = 0.36 L = 0.36

W = 2.00 L = 1.00

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Dev-Gen

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Software Solutions

Express Training Volume 3 Layout Verification & SPR

Introduction to TM Tanner Tools Pro

Layers
Drawn

layers or Generated layers layers

Typically correspond to mask layers (plus a few annotation layers) Objects on these layers are automatically created from other objects on other layers Used to specify rendering for required L-Edit elements

Derived

Special

Layers

are used to control rendering


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Special Layers

First mask layer controls the upper-left corner of the layer palette Error layer is used to create error ports from DRC and SPR Cell Outline layer is used to render the outline of cells when Hide Cell Insides is on (also see Icon layer below) Icon layer is used (i) to render cells when Hide Cell Insides and View>Display>Icon is on (if objects are present on the Icon layer), (ii) for abutment boxes in SPR and L-Comp. This is useful for floor planning when cells have to overlap
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General

L-Edit/Setup/Layers/

Create and order layers Assign electrical (and other) properties

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Rendering

L-Edit/Setup/Layers/

Add

Subtract Paint Overwrite Add OR of color indices Subtract Color index AND NOT this colors index
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Derivation

L-Edit/Setup/Layers/

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Derived Layers: Boolean


All derived layers (boolean, select, area, density) are calculated on layers after they have been merged.

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Derived Layers: Boolean


A AND B

A OR B A B NOT A

Order of Operations 1. 2. 3. Grow NOT AND, OR (in order)

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Derived Layers: Area Selection

Example of use: find all contact cuts that are not 0.24 x 0.36 um2
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Derived Layers: Select

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Select: Inside
Inside: Totally contained Poly INSIDE Metal1 NOT Inside

Poly Metal1
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NOT Inside == Outside OR Cut

Select: Outside
Outside: Mutually exclusive Poly OUTSIDE Metal1 NOT Outside

Poly Metal1
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Select: Hole

Select Poly polygons which exactly fill interior holes in Metal1 polygons. Poly HOLE Metal1

Poly Metal1

NOT Hole: Select polygons which do NOT exactly fill interior holes

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Select: Cut
Cut: Poly polygon has nonzero area BOTH inside and outside Metal1 polygon Poly CUT Metal1 NOT Cut: Poly polygon either inside or outside Metal1 polygon

Poly Metal1
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Select: Touch
Touch: Poly polygon shares an edge with Metal1, and is outside Metal1 Poly TOUCH Metal1 NOT Touch

Poly Metal1
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Select: Enclose
Enclose: Poly polygon that completely encloses Metal1 Poly ENCLOSE Metal1 NOT Enclose

Poly Metal1
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Select: Overlap
Overlap: Poly polygon that cuts, touches, encloses or is inside Metal1 NOT Overlap: Poly polygon that is entirely outside Metal1 (does not share edge)

Poly OVERLAP Metal1

Poly Metal1
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Select: Vertex
Vertex: Poly polygons that have a specific number of vertices. Useful for checking non-rectangular contacts or gates.

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Select Speeds

Fastest to Slowest Select Operations


NOT OUTSIDE (OUTSIDE) INTERACT (NOT INTERACT) CUT (NOT CUT) ENCLOSE (NOT ENCLOSE) OVERLAP (NOT OVERLAP) INSIDE (NOT INSIDE) TOUCH (NOT TOUCH) HOLE VERTEX

Slower

SELECTS will not be more than 2x slower than the fastest.


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Select: Density
Density: Sum of the area of Metal1 divided by the area of the cell extent. Layer is merged before calculating area.

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Select: Density
Sum of the area of these polygons divided by the area of this polygon Density: Sum of the all via3 polygons inside of a Pad polygon divided by the area of that polygon.

Sum of the area of these polygons

divided by the area of this polygon

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Generate Layers

Automatically mark intermediate layers marks a layer and all derived layers that it depends on. Layers are in alphabetically order. Clear all generated layers first deletes all geometry on derived layers that are marked to be generated (removes old results).
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DRC Design Rule Checker


Integrated Full Chip & Region Check Hierarchical DRC Supports All-angle DRC Simple Location and Repair of Errors Supports Complex Rules with Boolean Operations Configurable for Multiple Foundry Support

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Design Rule Check Speedup

Guidelines for faster DRC


Have enough memory (no swapping). Hierarchical designs. Reduce complexity of derivations. Fix errors at the lowest level. Huge speedups possible. Encourages hierarchical design. Errors reported where they occur. Best practice: Clean, non-overlapping cell design.
Do not create devices in cell overlaps. Minimize inter-layer connections that require looking at multiple cells. These will still work, but you will suffer a performance penalty.
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Hierarchical DRC

Design Rule Check Procedures

Layout /

DRC Setup Run DRC Find Errors using DRC Error Navigator Repair Errors (in the lowest hierarchy) Hidden Layers are not checked.

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DRC Error Navigator


Browse and Display DRC errors Simplifies iterations of the DRC error correction View DRC errors in top-level or cell context DRC Error Navigator

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DRC Error Navigator

DRC Error Navigator (DEN)


Toggle Error Mark Next DRC Error . (period) Previous DRC Error - , (comma) DEN Options View All Rules View By Rule/Cell Cell/Top Level Context DEN Menu Delete DRC Error Number of DRC Errors including hidden errors DRC Job Back Forward

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DRC Error Navigator

Hint: map F1 to show/hide DRC Error Navigator (Browse DRC) & F2 to show/hide DRC Error marker (Toggle Mark)

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DRC Setup

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Minimum/Exact Width

Poly minimum width = 0.24 m

Exact width = 0.36 m

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Spacing
Layer 1 (dark) to Layer 2 (light) spacing

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Surround
Layer 2 (light) surrounds Layer 1 (dark) This is the distance that is checked Outside Edge to Inside Edge

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Extension
Layer 2 (dark) extend beyond Layer 1 (light) Typically used to confirm gate and channel extensions to make valid selfaligned FETs

This is the distance that is checked Inside Edge to Outside Edge


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Overlap
Layer 2 (dark) overlap into Layer 1 (light) .i.e. N-Select overlap Active

This is the distance that is checked Inside Edge to Inside Edge

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Geometry Flags

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V11 Foundry Compatible DRC


Calibre

rule decks DRACULA rule decks Syntax checking editor Rule browser
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L-Edit Extract

Creates a SPICE Netlist from the Layout.


for LVS for post-layout simulation Connectivity of Layout Active Devices Passive Devices Device Area & Perimeter Fringe & Area Parasitic Capacitance Subcircuit

Extracts:

Process Configurable Labels Devices

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Extract Definition File

Connection Statements

Layer 1 Layer 2 Connection layer Device type Device recognition layer rlayer Pin layer Device model

Devices Definitions

... connect(Metal1, Metal2, Via1) connect(Metal2, Metal3, Via2) connect(Metal3, Metal4, Via3) connect(Metal4, Metal4 - Pad, Metal4) connect(LPNP Emitter, pdiff, LPNP Emitter) connect(LPNP Collector, pdiff, LPNP Collector) # NMOS transistor with poly gate device = MOSFET( RLAYER=ntran; Drain=ndiff, AREA, PERIMETER; Gate=poly wire; Source=ndiff, AREA, PERIMETER; Bulk=Substrate; MODEL=NMOS; ) ...

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Extract Run Options


C:\Tanner\MyChips\class\tech\Tech4class.ext

Parasitic extraction

Declare devices for LVS or commands for T-Spice


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Extract Output Netlist

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Extract: Naming nodes and


elements

Use ports to assign names

Port box has to be over the appropriate layer


Recognition layer for devices Electrical layer for nodes Can be on a layer used to derive a connect or pin layer

Alternately, L-Edit can automatically label devices

Slow, memory intensive but permanent

Or, use Tools>Goto Device to locate dynamically named devices. Requires coordinates to be written to the SPICE file.
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Devices and Parameters


Capacitor

Layout/Extract/

Capacitance (area + fringe) Resistance (including odd shapes) Inductance (user calculated) Model Area (rlayer area | pin area) Area = layout area / nominal area Model Area (rlayer area | pin area) Area = layout area / nominal area Model Area (rlayer area | pin area) Area = layout area / nominal area Length and width
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Resistor

Inductors

BJT

Diode

MESFET

Devices and Parameters


MOSFET

Layout/Extract/

Model Length and width (including odd gate shapes) source/drain area/perimeter Fraction of gate width to include in perimeter (Gate) GEO
1 drain and source area are not shared 2 drain is shared 3 source is shared 4 both drain and source are shared

JFET

Model Area (rlayer area | pin area) Area = layout area / nominal area

Non-Standard and Compound devices Subcirciut Extraction

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L-Edit Extractor
Devices are located by finding polygons on recognition layers Pins are polygons on userspecified layers that overlap or touch the recognition polygon

# NMOS transistor with poly gate device = MOSFET( RLAYER=ntran; Drain=ndiff, AREA, PERIMETER; Gate=poly wire; Source=ndiff, AREA, PERIMETER; Bulk=Substrate; MODEL=NMOS; ) ntran = N-Channel AND NOT Capacitor ID N-Channel = Gate AND NOT N Well AND N Select Gate = Poly AND Active ndiff = diff AND N Select diff = field active AND NOT Resistor ID ntran field active = Active AND NOT Poly poly wire = Poly AND NOT Resistor ID

Drawn layout

ndiff

poly wire

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Extract: MOSFETs
DEVICE=MOSFET ( RLAYER = rLayer ; Drain = dLayer {[, AREA] [, PERIMETER [/GATE=#]] | [,GEO]}; Gate = gLayer ; Source = sLayer [, AREA] [, PERIMETER [/GATE=#]]; [Bulk = [bLayer ];] MODEL = model ; ) [IGNORE_SHORTS]
Mname drn gat src [blk] model L=lengthValue W=widthValue {[AD=areaValue] [PD=perimeterValue] [AS=areaValue] [PS=perimeterValue] | [GEO=#]}

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Extract: Resistors
DEVICE=RES ( RLAYER = rLayer [, LW]; Plus = Layer1 ; Minus = Layer2 ; MODEL = [ModelName ]; ) [IGNORE_SHORTS] Rxxx n1 n2 [ModelName] [R=]rValue LW keyword: Rxxx n1 n2 [ModelName] L=rLength W=rWidth rWidth = average length of pin edges shared with RLAYER rLength = RLAYER area / rWidth rValue = rho * rLength / rWidth
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Extract: Subcircuits
DEVICE=SUBCKT ( RLAYER = rLayer [, AREA] [, PERIMETER] [, LW]; pin1Name = pin1Layer [, AREA] [, PERIMETER] [, WIDTH] [, DEVICEWIDTH]; pin2Name = pin2Layer [, AREA] [, PERIMETER] [, WIDTH] [, DEVICEWIDTH]; ... MODEL = model ; Xzzz n1 [n2 ...] cName [NominalArea = areaVal ;] [AREA=rLayerArea/areaVal] [PERI=rLayerPerimeter/areaVal] ) [IGNORE_SHORTS]
DEVICEWIDTH Modifier [AREA_pin1Name=pin1Area/areaVal] WIDTH = Average of pin widths that have DEVICEWIDTH [PERI_pin1Name=pin1Perimeter] LENGTH = AREA/WIDTH
# IC Poly Resistor device = SUBCKT( RLAYER=PolyResistor, LW; Plus=PolyWire, DEVICEWIDTH; Minus=PolyWire, DEVICEWIDTH; Bulk=Substrate; MODEL=ICResPoly; ) [WIDTH_pin1Name=pin1Width] [AREA_pin2Name=pin2Area/areaVal] [PERI_pin2Name=pin2Perimeter] [WIDTH_pin2Name=pin2Width] ... [L=cLength W=cWidth]

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Extract: Connections
Connections

between layers explicit

Connect( A, B, C ) Connects polygons on layer A and layer B, where (A AND C) overlaps or touches B
The

result is a single electrical node


connect(n well wire, ndiff, ndiff)

connect(pdiff, Metal1, Active Contact)

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Extract: Parasitics
If

enabled, nodal capacitances (to ground) are calculated and output Be careful not to double count Does not calculate crosstalk parasitics

Use devices to extract these parasitics

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LVS Layout-vs-Schematic

Compares Netlists

Reads common SPICE format, flat or hierarchical netlists . Compares parameters with user-specified tolerance. Collapsing of Devices
series/parallel R, C, MOSFETS

We want to know if the correct number, type and size of elements in the layout are connected together exactly as they are in the schematic of course, any two netlists can be compared

Single or Batch Mode Verification


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LVS Objects Diagram


S-Edit
.VDB LVS setup

L-Edit Extract
.SPC layout netlist Model declarations .LIS device & net correspondence

.SP schematic netlist Model declarations .PRE device & net prematch

LVS compare

.LVS (.OUT) results


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LVS Window Regions - Input


Menu bar Run LVS Toolbar Setup Window

Nondefault values indicated

Status Bar
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LVS / Output

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LVS / Device Parameters

Consider L & W

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LVS Optimizations

Polarized components

MOSFETS (Drain/Source are indistinguishable) Resistors (usually unpolarized) Capacitors (sometimes unpolarized) MOSFETS, Rs, Cs (usually OK) MOSFETS (maybe OK), Rs, Cs (usually OK)

Parallel components

Series components

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LVS / Merge Devices


Caution: Choices of LVS options are very important.
Merging by Model Syntax:
type_name1, type_name2 type = device

abbreviation nameX = Model name

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LVS / Parasitics

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LVS / Options

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LVS / Performance

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LVS Results

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Interpreting LVS Results


If LVS reports circuits are equal, they are! If LVS reports circuits are not equal, then there is a real error between the netlists. Fragmented classes. If LVS reports circuits are only topologically equal, then there are parametric errors.

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SPR

Standard Cell Place and Route


The

Purpose of SPR
80% solution for 10% price Low cost applications

EDIF

input Placement optimizer for minimal wire lengths Cell clustering for placement Compact 3 layer channel routing with over-the-cell route Global signal routing Critical net assignment Padframe generator, pad router

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SPR Operations
Design flow steps:
1) Core Place&Route 2) Padframe placement 3) Pad routing

Layout / Standard cell Place & Route /

Core only for macro functions Placement optimization parameter Pad location control

Core, Padframe, and Pad Route menus

Wire capacitance output SDF timing output

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Schematic Preparation for SPR


Add PadOut to input/output ports Add PadVdd

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NAND2 Layout Draw Metal2 Layer Signal Ports

Ports A,B,Out on Metal2 H=0, W=0.36 um Purpose: show SPR where to connect signal wires.

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AO22 Core Layout - shows library cells fitting together

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AO22 - Completed SPR Layout

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Plot

Layout /

L-Edit Plot (an optional module)


independent colors & fills better resolution legends scales titles memory management

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Beyond Training
Tanner Customer Support 877-304-5544 (Toll Free) (626) 685-5969 (International) support@tanner.com Tanner CES (Consulting & Engineering Services) (626) 792-3000
TM

9 Physical Design of CMOS Integrated Circuits Using LEdit by John P. Uyemura - ISBN 0-534-94326-8 9 The Art of Analog Layout by Alan Hastings ISBN 0-13-087061-7 9 IC Layout Basics by Christopher Saint/Judy Saint ISBN 0-07-138625-4 9 IC Mask Design by Christopher Saint/Judy Saint ISBN 0-07-138996-2 9 CMOS IC Layout by Dan Clein - ISBN 0-750-67194-7 9 Design of Analog CMOS Integrated Circuits by Behzad Razavi - ISBN 0-07-238032-2 9 Absolute Beginner's Guide to C by Greg Perry ISBN 0-672-30510-0
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A Division of Tanner Research, Inc.

Glossary
.SDB S-Edit Database file. .TPR Tanner Place and Route file, a proprietary format for use by L-Edit. .EDN EDIF (Electronic Design Interchange Format) file use by L-Edit for place and route. .EDS EDIF schematic file used for porting schematics to other software. .SP Default extension for SPICE netlists generated by S-Edit. .SPC Default extension for SPICE netlists generated by L-Edit. .TDB Tanner Database is an L-Edits database file. SPR Standard Place and Route. DRC Design Rule Checker. LVS Layout vs. Schematic. UPI User Programmable Interface (Macros). .GDS or GDSII Standard file format for transferring/archiving 2D graphical design data. .CIF Caltech Intermediate Format T-Cell Parameterized cell. .EXT L-Edits extraction definition file, .XST Cross-section definition file for use with L-Edits Cross-section Viewer. .TTX Tanner Text Format File contain L-Edits technology information in text format. .SDF Standard Delay Format file Generated by SPR which contains pin-to-pin delay information. .LIB - Synopsys Liberty file that contains pin characteristics for standard cells. SPR uses this information to generate SDF file. Xref External reference cell. LMB Left mouse button. MMB Middle mouse button or Minimum Bounding Box. RMB Right mouse button.

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A Division of Tanner Research, Inc.