ADDERS:

Lets design the combinatonal circuit for binary adder. A combinational circuit that performs the addition of two bits is called Half adder while the circuit which adds 3 bits is called Full adder. Half adder: For this adder we have two inputs and two outputs. The two inputs are those 2 bits a and b which are to be added and the the 2 outputs are the sum and the carry. The following table shows the result of different combinations of inputs: a 0 1 0 1 b 0 0 1 1 S(sum) C(carry) 0 1 1 0 0 0 0 1

Now we can see from the table that carry is one only when both inputs are 1 while sum is 1 when only one of the two is 1 like a XOR gate.So
S= ab + ab C= ab

Or we can get the equations from the K-map also which are discussed on the next page

K-map for the variable Sum is

K-map for the variable Carry is

And the circuit diagram is as follow:

FULL ADDER(FA): The full adder has 3 inputs and 2 ouputs. The first 2 inputs are the 2 bits a & b to add while the 3rd input c is the carry from the previous significant bit while the outputs are the same: sum S and the carry C. The following table shows the result of different combinations of inputs: a 0 0 1 1 b 0 1 0 1 c 0 0 0 0 1 0 S(sum) C(carry) 0 1 0 1 0 0

0 0 1 1

0 1 0 1

1 1 1 1

1 0 0 1

0 1 1 1

K-map for the output variable SUM is as follow:

This circuit is a level 3 circuit as we also need inverters at level 1, then we have 4 3-input AND gates at level 2 and 4-input OR gate at level 3. So we need 3 gate delays (3) to get the output for Sum. K-map for the variable carry is as follow:

When we implement this circuit we see that this is a level 2 circuit as we have AND gates at level 1 and 3-input OR gate at level 2 and hence we need 2 gate delays (2) to get carry output.

Lets now put the equations in different form: S = abc + abc + abc + abc = (1,2,4,7)

= b (ac + ac) + b (ac + ac) = b (ac + ac) + b (ac + ac) =b (a xor c) + b (a xor c) ac = a xor c} = bz + zb= b xor z = b xor a xor c S = a xor b xor c {We know (ac + ac) = ac + ac and ac + {z= (a xor c)}

and C = ab + ac + bc = ab(c + c) + ac (b + b) + bc (a + a) = abc + abc + abc + abc + abc + abc = abc +abc+abc+abc= (3,5,6,7) So we can draw the circuits using XOR, NOT, AND & OR gates

Similar to the adder, we can also design subtractors and we also have half and full subtractors. Half subtractor (HS): This circuit subtracts two bits and gives Borrow and Difference as 2 outputs. The following table shows the result for different combinations of inputs: a b B(borrow) D(difference)= D = a b

0 1 0 1

0 0 1 1

0 0 1 0

0 1 1 0

We scan easily see that diference is 1 only when we have one of the inputs as 1 and other as 0 just like a XOR gate. So equation for difference is D= ab + ab We can also obtain the equations using K-maps

And the digital circuit to implement the above functions is as follow:

This has 3 inputs- 2 are the numbers to be subtracted and c is the borrow which is taken for previous bit and we have 2 outputs Difference and the Borrow. The following table shows the results for all combinations of inputs: a 0 0 1 1 0 0 1 1 b 0 1 0 1 0 1 0 1 c 0 0 0 0 1 1 1 1 B(borrow) 0 1 0 0 1 1 0 1 D(difference)= D = a b c 0 1 1 0 1 0 0 1

So we can get the equations for the D and B from the K-maps as shown on next page. K-map for the output variable Difference is as follow:

We need 3 gate delays (3) to get the output. K-map for the variable Borrow is as follow: Note that we have taken opposite values of variable a in the K-map.

We can get the output in 2 gate delays as we assume that a, b the input numbers are stored in flipflops hence we can have the complimented a from the flipflop directly. So we dont consider the delay of the inverter shown in the circuit. Similar to the adder we have D = abc + abc + abc + abc = a xor b xor c And B= ab + ac + bc And we have the following circuit diagram for full subtractor: