LETTERS International Journal of Recent Trends in Engineering, Vol 2, No.

6, November 2009

VHDL Modeling of Convolutional InterleaverDeinterleaver for Efficient FPGA Implementation

B. K. Upadhyaya1, S. K. Sanyal2
1

Tripura Institute of Technology, Agartala, Tripura, India Email: bku_ju@rediffmail.com 2 Jadavpur University, Kolkata, India Email: {s_sanyal}@ieee.org

Abstract Interleaving along with error correction coding is an effective way to deal with different types of error in digital data communication. Error burst due to multipath fading and from other sources in a digital channel may be effectively combated by interleaving technique. In this paper an efficient technique to model convolutional interleaver using a hardware description language is proposed and implemented on field programmable gate array (FPGA) chip. Our technique utilizes embedded shift register of FPGA chip to implement incremental shift register in the interleaver. Software simulation of the model is presented. The proposed technique reduces consumption of FPGA resources to a large extent compared to conventional implementation technique using flip-flop. This implies lower power consumption and reduced delay in the interconnection network of the FPGA. This technique is also efficient in reducing wastage of memory compared to memory based implementation technique for digital audio broadcasting (DAB) application. Index Terms Convolutional Interleaver, VHDL, FPGA, embedded shift register, memory wastage

I. INTRODUCTION The error correction codes (ECC) play very important role in modern digital communication systems. Interleaving technique is traditionally used to reduce bit error rate (BER) of digital transmission over a bursty channel [1]. Interleaving is a process to rearrange code symbols so as to spread burst of errors into random like errors and thereafter ECC can be applied to correct them. Interleaving improves [2] the performance of digital transmission at the cost of increased memory requirement, system complexity, and delay. Many papers in the literature have addressed the issue of designing interleaver in order to achieve low bit error rate [3,4,5]. On the contrary, very few papers have addressed the efficient implementation issue of the interleavers [6,7]. Block and Convolutional are the two popular interleavers employed in digital data transmission. The former is simple and easy to implement whereas the later offers advantages like lesser end-to-end delay and reduced memory requirement [8]. In this paper we have proposed an efficient and novel technique to model and implement convolutional interleaver-deinterleaver pair on field programmable gate array (FPGA) platform. Proposed technique employs embedded shift register offered by different FPGA manufacturers [9,10] to model the delay unit of the

interleaver. We have modeled and implemented 8 bit and 32 bit version of interleaver as well as deinterleaver. Both these implementation techniques are different in the sense that they involve full FPGA based design leading to less resource requirement and thereby making lesser power consumption and interconnect delay. Comparative analysis shows saving of FPGA resources above 81 % in comparison to conventional technique using flipflops. Use of lesser slices leads to reduced delay in the interconnection network inside the FPGA. The obvious implication is reduced power consumption. In addition, the memory wastage is further lowered by 30.38% for digital audio broadcast (DAB) application in comparison with [6]. The rest of the paper is organized as follows. Section II discusses the background of convolutional interleaving technique. In Section III, we briefly describe the embedded shift register of Spartan-3 FPGA of Xilinx Inc. that was used to obtain our implementation results. Section IV provides functional description of the proposed VHDL model of convolutional interleaver. Simulation result of the VHDL model is explained in Section V. Section VI performs the critical analysis of FPGA implementation result. Concluding remark is given in Section VII. II. CONVOLUTIONAL INTERLEAVER A convolutional interleaver [2] consists of N rows of shift registers, with different delay in each row. In general, each successive row has a delay which is J symbols duration higher than the previous row as shown in Fig. 1. The code word symbol from the encoder is fed into the array of shift registers, one code symbol to each row. With each new code word symbol the commutator switches to a new register and the new code symbol is shifted out to the channel. The i-th (1 i N-1) shift register has a length of (i-1)J stages where J = M/N and the last row has M-1 numbers of delay elements. The convolutional deinterleaver performs the inverse operation of the interleaver and differs in structure of the arrangement of delay elements. Zeroth row of interleaver becomes the N-1 row in the deinterleaver. 1st row of the former becomes N-2 row of later and so on.

2009 ACADEMY PUBLISHER

66

LETTERS International Journal of Recent Trends in Engineering, Vol 2, No. 6, November 2009
Delay Element 0 1 J 2 J 3 J J J From Encoder N-1 J J J J Clock Clock circuit 3 Counter To Channel Din SIPO register 8 Buffer 8 Delay unit 8 8:1 MUX Dout J

from the output of the interleaver is applied as input to the deinterleaver block along with clock as synchronization signal. It is observed that the scrambled code word is converted into its original form at the output of the deinterleaver block.

Figure1. Convolutional Interleaver

III. HARDWARE DESCRIPTION OF FPGA In our experimentation, Xilinx Spartan-3 (device XC3S 400) with 400K gate count FPGA is used [9]. It has total 896 numbers of configurable logic blocks (CLBs) arranged in 32 X 28 matrix fashion. Each CLB has four slices and two of them are named as SLICEM and rest two as SLICEL. Each SLICEM can be used as 16 bit (embedded) shift register (SRL16). DAB application requires a convolutional interleaver of array size [6]; of 17 X j (j = 0, 1, , 11) = 1122 numbers of delay elements. Numbers of SRL 16 required to implement the interleaver is 77 which is only 4.3% of available SRL16. Because of our efficient FPGA implementation technique, sufficient FPGA resources are made available for implementing other circuitry of the transmitter / receiver. IV. PROPOSED MODEL OF CONVOLUTIONAL INTERLEAVER The proposed VHDL model [11] of an 8 bit convolutional interleaver with J = 1 is presented in Fig. 2. The code word symbols (Din) received in serial form from an encoder is converted into an 8 bit parallel code word by a Serial Input Parallel Output (SIPO) register. The SIPO output changes its value with each clock which is not desirable at the input of the delay unit. The buffer unit delivers a word to the delay unit after every 8 clock cycles. The delay unit is comprised of eight rows and is having the structure as narrated in Fig. 1. Each code symbols of the 8 bit code word is applied to the respective row of the delay unit. The code word gets scrambled as it progresses through the delay unit. The scrambled code word then applied to the input of an 8 line to 1 line multiplexer (MUX) which converts it into stream of serial data (Dout). The interleaver circuit requires a clock signal to drive the SIPO register, a clock circuit and a three bit counter. The clock circuit basically divides the system clock frequency by 8 which is used to drive the buffer and delay unit. The 3 bit counter generates the select input for the MUX. The VHDL model of the deinterleaver is exactly similar to Fig. 2. In order to verify the VHDL models for the interleaver and deinterleaver the authors have developed another top level VHDL model, combining interleaver and deinterleaver. The scrambled code words
Figure 2. Block diagram of proposed 8 bit convolutional interleaver.

V. SIMULATION RESULT The simulation result in the form of timing diagram obtained using ModelSim Xilinx Edition-III, version 6.0a is shown in Fig. 3. The 8 bit (=111111112 ) input signal is applied at data_in input of the interleaver. The interleaver produces scrambled output at d_out. This scrambled output is fed as input to the deinterleaver which arranges them in such a way that the original code word is generated at its output (data_out). The authors have also modeled, simulated and tested 32 bit Convolutional interleaver and deinterleaver pair, however to maintain clarity the simulation result of the same is not provided. VI. CRITICAL ANALYSIS OF FPGA IMPLEMENTATION RESULTS The VHDL model of Convolutional interleaverdeinterleaver pairs (both 8 bit and 32 bit) are implemented and tested into Xilinx Spartan-3 (Device: XC3S400) FPGA platform. Table I shows a comparative analysis of the FPGA resource requirement in the delay units of interleaver and deinterleaver taken together for the two implementations: with and without SRL16 for both 8 bit and 32 bit version. Table I clearly signifies that our proposed implementation technique saves 50 % and above 81 % of FPGA resources compared to implementation technique without SRL16 for 8 bit and 32 bit respectively. Use of lesser slices leads to reduced delay in the interconnection network inside the FPGA. This further implies reduction in power consumption too.
TABLE I. COMPARATIVE ANALYSIS BETWEEN VARIOUS IMPLEMENTATIONS Interleaver word length 8 bit 32 bit 1 bit delay units required 8 X 7 = 56 32 X 31 = 992 FPGA slices required without SRLC16 56 2 = 28 992 2 = 496 with SRLC16 14 92 Slice saving in % 50.00 % 81.45 %

2009 ACADEMY PUBLISHER

67

LETTERS International Journal of Recent Trends in Engineering, Vol 2, No. 6, November 2009

Figure 3. Simulation result with input code word = 111111112

Table II makes comparison of our proposed technique with Kim et. al. [6] in the issue of reduction in memory wastage for interleaver implementation. It is found that our proposed technique further reduces memory wastage by 30.38 % for DAB application. In addition, obviously the access time of embedded shift register is lower than that of external memory.
TABLE II. COMPARATIVE ANALYSIS WITH RESPECT TO MEMORY WASTAGE row no. 1 bit delay units required using Kim et. al. technique RAM size wasted memory 60 86 --1 1 1 9 --------158 our proposed technique wasted no. of SRLC16 memory required 2 15 3 14 4 13 5 12 6 11 7 10 8 9 9 8 10 7 11 6 12 5 110

interconnection delays are the obvious implications of the technique. It also lower the memory wastage by 30 % compared to a popular implementation technique for DAB application. REFERENCES
[1] Y. Q. Shi, X. M. Zhang, Z. C. Ni, and N. Ansari, Interleaving for Combating Bursts of Errors, IEEE Circuits and System magazine, first quarter, pp. 29-42, 2004. [2] G. D. Forney, Burst-Correcting Codes for the Classic Bursty Channel, IEEE Transaction on Communication Technology, vol. COM-19, pp. 772-781, 1971. [3] F. Daneshgaran, M. Laddomada, and M. Mondin, Interleaver design for serially concatenated convolutional codes: theory and application, IEEE Transactions on Information Theory, vol. 50, no. 6, pp. 1177-1188, 2004. [4] V. D. Nguyen, and H. P. Kuchenbecker, Block interleaving for soft decision Viterbi decoding in OFDM systems, IEEE VTS 54th Vehicular Technology Conference, U.S.A, pp. 470, 2001. [5] H. R. Sadjadpour, N. J. A. Sloane, M. Salehi, and G. Nebe, Interleaver design for turbo codes IEEE Journal on Selected Areas in Communications, vol. 19, no 5, pp. 831837, 2001. [6] J. B. Kim, Y. J. Lim, and M. H. Lee, A Low Complexity FEC Design for DAB, IEEE ISCAS, Sydney, Australia, pp. 522-525, 2001. [7] H. Yang, Y. Zhong, and L. Yang, An FPGA Prototype of a Forward Error correction (FEC) Decoder for ATSC Digital TV, IEEE Transaction on Consumer Electronics, vol. 45, No.2, pp. 387-395, 1999. [8] S. A. Hanna, Convolutional interleaving for digital radio communications, Second IEEE International Conference on Personal Communications: Gateway to the 21st Century, vol.: 1, pp. 443-447, 1993. [9] Xilinx, Spartan-3 FPGA Family: Complete Data Sheet, 2007, available at www.xilinx.com. [10] Altera, Cyclone III Device Handbook, vol. 1, 2007 available at www.altera.com. [11] D. Perry, VHDL: Programming by Example, 3rd Edition, Tata McGraw Hill, New Delhi, 2001.

1 2 3 4 5 6 7 8 9 10 11

17 128 (R1+R3) 34 256 (R2+R8) 51 merged with R1 68 256 (R4+R11) 85 256 (R5+R10) 102 256 (R6+R9) 119 128 136 merged with R2 153 merged with R6 170 merged with R5 187 merged with R4 Total wastage

Due to efficient modeling, the Convolutional interleaver-deinterleaver pair uses very few FPGA resources thereby making room for other associated circuitry to be implemented on the same FPGA chip. The estimated power consumption of the 32 bit model is found to be 125mW. VII. CONCLUSION In this paper an efficient VHDL model of convolutional interleaver is proposed. Simulation result in the form of timing diagram using ModelSim is presented which endorses the successful operation of the model. The model efficiently utilizes embedded shift register of FPGA. This technique reduces FPGA resource utilization up to 81 % compared to other implementation technique. Lesser power consumption and reduced FPGA
2009 ACADEMY PUBLISHER

68