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Terminology
Each basic block in a design is modeled as a module Functionality is modeled inside each module by one or more
concurrent processes (threads or methods) Communication between modules is handled using channels, that implement some interfaces Interfaces are responsible to make the separation between communication and computation possible Modules are bound to and access channels interfaces through ports A transaction represents the data being exchanged A master (initiator) is a module that starts a transaction A slave (target) is a module that receives and serves transactional requests System synchronization is an action at least between 2 modules that need to coordinate their behavior
Modeling approach
The main goals in TLM are:
modeling the internal functionality of a hardware block at the
functional or behavioral level Propose a standard way to handle communication
Modeling accuracy
There are 2 main factors to determine the degree of modeling
accuracy:
Granularity of communication data
Application packet (ex. frame-by-frame transfer for a video) Bus packet (ex. macro block transfer made of lines and columns) Bus size (ex. pixel-based transfer for a video)
Timing accuracy
in order to assure deterministic behavior Only a partial order of execution is implemented through synchronization points There is a small degree of indeterminism Any execution order is permitted as long as their causal dependencies are well respected
Full execution order is local to each process Partial execution order is instead used for the system There are also 2 system synchronization points between P1 and P2 Examples of different possible execution orders
assurance of memory or data consistency If an untimed TLM generates deadlocks or failures, it means that the system synchronization has been badly designed
features of the untimed TLM For the way the SystemC kernel is implemented, it is not possible to predict in which order processes are executed Once the simulation is executed, the kernel will repeat the same execution order Due to that, it is possible to miss the bugs hidden in other execution orders We must make sure that any execution order conforms to the system functional specification Coverage can be increased by using a random function that shuffles all of the legal
process interleaves
Such coverage could produce a huge and useless number of combinations: alternative is
introducing successive constraints to limit amount of useless combinations (ex. timing constraints: only related to functional constraints (ex. 30 frames per second), not to micro-architecture constraints)
Functional delays are not referred to the micro-architecture Functional delays do not influence the model of computation By introducing functional delays, we limit the choices of
process interleaves at a given time instant
accuracy and the expected precision 3) think in a functional way, do not include micro-architectural and clock-based information 4) model explicitly the system synchronization that affects the IP behavior 5) use events and specific synchronization protocols to model inter-module synchronization 6) avoid process-activation based on regular basis
Observe:
TS will handle transactions received from channels in 2 ways:
Insensitive access: transaction is received from C and continues directly in TS: the TLM transaction is propagated in advance compared to actual occurrence in the silicon Sensitive access: transaction emitted from TI is rejected: early accesses are not granted. TI must regenerate the transaction by transferring it through the timed channel TC, in order to include the related communication time delay