Ca

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Appeal No. 2012-1634 (Reexamination No. 95/001,134)
UNITED STATES COURT OF APPEALS FOR THE FEDERAL CIRCUIT
RAMBUS, INC., Appellant,
v.
TERESA STANEK REA, ACTING DIRECTOR, UNITED STATES PATENT AND TRADEMARK OFFICE, Appellee.
Appeal from the United States Patent and Trademark Office, Board of Patent Appeals and Interferences. BRIEF FOR APPELLEE - DIRECTOR OF THE UNITED STATES PATENT AND TRADEMARK OFFICE NATHAN K. KELLEY Deputy Solicitor WILLIAM LaMARCA COKE MORGAN STEWART Associate Solicitors Office of the Solicitor - Mail Stop 8 U.S. Patent and Trademark Office P.O. Box 1450 Alexandria, VA 22313-1450 571-272-9035 Attorneys for the Director of the United States Patent and Trademark Office
March 6, 2013
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Representative Claim 1
1. A method of controlling a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises: issuing a write request to the memory device, wherein in response to the write request, the memory device samples first and second portions of data; providing a first portion of data to the memory device synchronously with respect to a rising edge transition of an external clock signal; and providing a second portion of data to the memory device synchronously with respect to a falling edge transition of the external clock signal.
See A69-70, col. 24, line 60-col. 25, line 6.
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TABLE OF CONTENTS
I.
STATEMENT OF THE ISSUE .................................
II. III.
STATEMENT OF THE CASE .................................. 3 STATEMENT OF THE FACTS ................................. 4 A. DRAM Technology ..................................... 4 The Claimed Invention (the '097 Farmwald Patent): A Method of Controlling a Synchronous Memory Device .................. 5 The Prior Art . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7
1.
B.
C.
Inagaki (Japanese patent publication) .................. 7 iAPX Manual: A Memory Module Controlled by a Bus Controller .................................... 9 iAPX Specification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11
2.
3. D.
The Board Decision and the Examiner's Answer ............. 11

1.
Anticipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Obviousness. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
12 15
2. 3. IV. V.
Secondary Considerations .......................... 18
SUMMARY OF THE ARGUMENT ............................ 19 ARGUMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 24 A. Standard of Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 24
11
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B.
Representative Claim 1 is anticipated by Inagaki ............. 26 1. Inagaki Discloses an "External Clock Signal" and a Synchronous Memory Device" as Those Terms are Properly Construed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 28 The Board Properly Construed the Term "Write Request" 32
2. C.
Representative Claim 1 Would Have Been Obvious in View ofthe iAPX Manual/Specification and Inagaki .. . . . . . . . . . . . .. 37 1. The iAPX Manual/Specification and Inagaki Would Have Rendered the Claims Obvious to the Ordinary Artisan. . .. 39 Rambus's Arguments that Inagaki's Clocking Scheme Would Not Be Used with iAPX's System Fail .......... 41 The Board Properly Determined Rambus's Secondary Evidence Was Insufficient to Overcome the Strong case of Obviousness ..................................... 48
A.
2.
3.
Rambus's Long-Felt Need Evidence Lacks Nexus and Is Not Commensurate in Scope with Claim 1 . .. 49 Rambus's Commercial Success Evidences Lacks Nexus and Is Not Commensurate in Scope with Claim 1 . .. 52
B.
VI.
CONCLUSION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 56
111
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B.
Representative Claim 1 is anticipated by Inagaki .............. 26 1. Inagaki Discloses an "External Clock Signal" and a Synchronous Memory Device" as Those Terms are Properly Construed ................................. 28 The Board Properly Construed the Term "Write Request" .. 32
2. C.
Representative Claim 1 Would Have Been Obvious in View ofthe iAPX Manual/Specification and Inagaki ................ 37 1. The iAPX Manual/Specification and Inagaki Would Have Rendered the Claims Obvious to the Ordinary Artisan ..... 39 Rambus's Arguments that Inagaki's Clocking Scheme Would Not Be Used with iAPX's System Fail ........... 41 The Board Properly Determined Rambus's Secondary Evidence Was Insufficient to Overcome the Strong case of Obviousness ...................................... 48 A. Rambus's Long-Felt Need Evidence Lacks Nexus and Is Not Commensurate in Scope with Claim 1 .... 49 Rambus's Commercial Success Evidences Lacks Nexus and Is Not Commensurate in Scope with Claim 1 .... 52
2.
3.
B.
VI.
CONCLUSION .............................................. 56
III
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TABLE OF AUTHORITIES CASES Berg, Inre, 320F.3d 1310 (Fed. Cir.2003) ......................... 43,47 CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359 (Fed. Cir. 2002) ...... 33 Consolidated Edison Co. v. NLRB, 305 US. 197 (1938) .............. 25,26 Cybor Corp. v. FAS Techs., Inc., 138 F.3d 1448 (Fed. Cir. 1998) .......... 24 Dance, Inre, 160 F.3d 1339 (Fed. Cir. 1998) ........................ 26,38 DBC, In re, 545 F.3d 1373 (Fed. Cir. 2008) . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25 Elmer v. ICC Fabricating, 67 F.3d 1571 (Fed. Cir. 1995) ................. 26 Etter, In re, 756 F.2d 852 (Fed. Cir. 1985) ............................. 42 Ex Parte Papst-Motoren, 1 US.P.Q.2d 1655 (BPAI Dec. 23,1986) ...... 24,25 Gartside, In re, 203 F.3d 1305 (Fed. Cir. 2000) ......................... 25 Graham v. John Deer Co., 383 US. 1 (1966) . . . . . . . . . . . . . . . . . . . . . . . . . .. 38 Gurley, In re, 27 F.3d 551 (Fed. Cir. 1994) ............................ 45 Huang, Inre, 100 F.3d 135 (Fed. Cir. 1996) ............................ 55 Hyatt, In re, 211 F.3d 1367 (Fed. Cir. 2000) ........................ 24,25 Inland Steel, Co., In re, 265 F.3d 1354 (Fed. Cir. 2001) .................. 55 Iron Grip Barbell Co., Inc. v. USA Sports, Inc., 392 F.3d 1317 (Fed. Cir. 2004) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55
IV
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Jolley, In re, 308 F.3d 1317 (Fed. Cir. 2002) ........................... 26 Kahn In re, 441 F.3d 977 (Fed. Cir. 20006) ............................ 45 Kao, In re, 639 F.3d 1057 (Fed. Cir. 2011) ............... 48,49,51,52,54,55 Kotzab, In re, 217 F.3d 1365 (Fed. Cir. 2000) .......................... 25 KSR Int'l Co. v. Teleflex, Inc., 550 U.S. 398 (2007) . .. 22,25,38,39,41-45,47
Monolithic Power Sys., Inc. v. Micro InrI Ltd., 558 F.3d 1341 (Fed. Cir. 2009) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 37,38 Mouttet. In re, 686 F.3d 1322 (Fed. Cir. 2012) . . . . . . . . . . . . . . . . . . . . . . . . .. 42 Napier, In re, 55 F.3d 610 (Fed. Cir. 1995) ............................ 25 Newell Co. v. Kenney Mfg. Co., 864 F.2d 757 (Fed. Cir. 1988) . . . . . . . . . . .. 48 Para-Ordnance Mfg. v. SGS Importers Int'l, 73 F.3d 2000) ............ 25,55 Paulson, In re, 30 F.3d 1475 (Fed. Cir. 1994) . . . . . . . . . . . . . . . . . . . . . . . . . .. 55 Phillips v. A WH Corp., 415 F.3d 1303 (Fed. Cir. 2005) ............. 25,29,33 Rambus Inc. v. Infineon Technologies, 318 F.3d 1081 (Fed. Cir. 2003) ... 21,36 Rambus, In re, 694 F.3d 42 (Fed. Cir. 2012) ....................... 6, 16,24 Rambus v. LSI v. STMicroelectronics, 2012 WL 4466578 (N.D. Ca. 2012) .. 32 Sibia Neurosciences, Inc. v. Cadus Pharma. Corp., 225 F.3d 1349 (Fed. Cir. 2000) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 53 SmithKline Beecham Corp. v. Apotex Corp., 439 F.3d 1312, 1319 (Fed. Cir. 2006) ............................................. 38
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Sneed, In re, 710 F.2d 1544 (Fed. Cir. 1983) ........................ 16,42 Taokai Corp. v. Easton Enterprises, Inc., 632 F.3d 1358 (Fed. Cir. 2011) .... 49 Watts, In re, 354 F.3d 1362 (Fed. Cir. 2004) ......................... 24,46 Wyers v. Master Lock Co., 616 F.3d 1231 (Fed. Cir. 2010) ............. 48,49 ZIetz, In re, 893 F.2d 319 (Fed. Cir. 1989) . . .. . . ... .... . .. ......... . . .. 25
STATUTES
35 U.S.C. 103 (a) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 38
OTHER AUTHORITIES
iAPX 432 Interconnect Architecture Reference Manual (Intel Corp.) (1982) . .. 9 Intel, Memory Components Handbook (1985) . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 McGraw-Hill Dictionary of Scientific and Teclmical Terms 387 (5 th Ed. 1994) ................................................
12
VI
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STATEMENT OF RELATED CASES

The Director is not aware of any other appeal to this court related to the reexamination proceeding on appeal in this case, but is aware of other cases that Rambus identified involving the underlying patent, i.e.,
u.s. Patent No. 6,260,097
("Farmwald '097 patent"), including: Rambus Inc. v. Hynix Semiconductor, No. 505-cv-00334-RMW (N.D. Cal.) (Whyte, J.); Rambus Inc. v. LSI Corporation, No. 3:10-cv-05446-RS (N.D. Cal.) (Seeborg, J.); Rambus Inc. v. Micron Technology, Inc., No. 5:06-02244-RMW (N.D. Cal.) (Whyte, J.); Rambus Inc. v. STMicroElectronics, N.V., No. 3:10-cv-05437-RS (N.D. Cal.) (Seeborg, J.). Rambus also identified in its brief cases that do not involve the '097 patent but involve patents from the same family, i.e., related to application 07/510,989, including: In re Rambus Inc., 694 F.3d 42 (Fed. Cir. 2012); Hynix Semiconductor Inc. v. Rambus Inc., No. 5:00-cv-20905-RMW (N.D. Cal.) (on remand from Micron Tech. v. Rambus, Inc., 645 F.3d 1336 (Fed. Cir. 2011)); Micron Technology, Inc. v. Rambus, Inc., No.1 :00-cv-00792-SLR (D. Del.) (on remand from Micron Tech. v. Rambus, Inc., 645 F.3d 1311 (Fed. Cir. 2011)).1
Before the Board, Rambus also identified cases not involving the '097 patent, but involving other patents in the same family. See A3; A1612-1616.
I
Vll
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Appeal No. 2012-1634 (Reexamination No. 95/001,134)
UNITED STATES COURT OF APPEALS FOR THE FEDERAL CIRCUIT

RAMBUS, INC., Appellant, v. TERESA STANEK REA, ACTING DIRECTOR,z UNITED STATES PATENT AND TRADEMARK OFFICE, Appellee.
Appeal from the United States Patent and Trademark Office, Board of Patent Appeals and Interferences.
I.
STATEMENT OF THE ISSUE
The Farmwald '097 patent, owned by Rambus, claims a method of controlling a computer memory device with a plurality of memory cells. The method includes the steps of: (1) issuing a "write request" to the memory device which, in response, (2) writes data synchronously to its memory with respect to both the rising and falling edge of an external clock signal. Effective February 1,2013, Teresa Stanek Rea became the Acting Under Secretary of Commerce for Intellectual Property and Acting Director of the United States Patent and Trademark Office pursuant to 35 U.S.C. 3(b)(1). Therefore, in her official capacity, she is automatically substituted as a party for David J. Kappos pursuant to Federal Rule of Appellate Procedure 43(c)(2).
2
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The Board found that such a method was already known. In particular, the Board found that Inagaki, a 1981 Japanese patent publication, discloses a memory device that: (1) receives a signal representing a "write request," and, in response, (2) inputs or "writes" data to memory based on an external clock signal and uses both rising and falling edges of that external clock to synchronously time the writing of data (i.e., on every half cycle of the external clock). A key issue in this case is whether substantial evidence supports the Board's finding that Inagaki anticipates representative claim 1. The Board also found that another prior art reference, the iAPX Manual, discloses a synchronous memory device that receives write and read requests and synchronously writes data to its memory device based on the rising edge of an external clock signal (i.e., once per clock cycle). The iAPX Manual does not use the "falling" clock edge to synchronously time the writing of data as in claim 1. However, as the Board found, such a modification would have been obvious in light of Inagaki' s teaching of using both the rising and falling edge of an external clock. Thus, a second issue in this case, which this Court need not reach if it affirms the anticipation rejection (see infra page 37), is whether the Board properly concluded that an ordinary artisan would have used Inagaki's teachings with the iAPX system to render claim 1 obvious. 2
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II.
STATEMENT OF THE CASE

Rambus's now expired '097 patent, entitled "Method and Apparatus for
Controlling a Synchronous Memory Device" issued on July 10, 2001 on an application (09/514,872) that claimed priority to an application filed in 1990. A41-71. 3 On January 9, 2009, third party NVIDIA filed a request to reexamine the '097 patent with the United States Patent and Trademark Office (PTO). A27822889. On March 13,2009, the PTO found a substantial new question of patentability and ordered reexamination of claims 1-35. A2758(a-l)-2758(a-32). On November 14,2009, the Examiner finally rejected numerous sets of claims in the '097 patent on various grounds. A2707-2758 (ACP). Following responses by Rambus and NVIDIA, on August 18, 2010, the Examiner issued a right of appeal notice (RAN) (AlO23-1190), confirming certain original claims,4 withdrawing certain rejections and maintaining rejections of: (1) claims 1-2, 7-8, 10 and 14 as anticipated by Inagaki (Al059-1075); (2) claims 1-5,7,8, 10-12, 14,26,28-32, and 34-35 as obvious over iAPX Manual in view ofInagaki (Al075-1119); (3) claims 1-5, 7, 8, 10-12, 14,26,28-32, and 34-35 as obvious over Budde in
Citations to "A- " refer to the Joint Appendix. Citations to "Br. at - " refer to Rambus's opening brief."
3
4
See Al026 (original claims 6, 9,13,15-25,27 and 33 were "confirmed"). 3
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view ofInagaki (A1119-1156); and (4) claims 1-5, 7-8, 10-12, 14,26,28-32, and 34-35 as obvious over iAPX Manual in view ofInagaki further in view ofiAPX Specification (Al164-1166). Subsequently, Rambus appealed (A1608) and NVIDIA cross-appealed to the Board. A2759-2780. The Examiner answered. A3; A1022(a)-1022(e) (incorporating his RAN (AlO23-1190)). On April 4, 2012, the Board held a hearing. A1000-l022. On June 11,2012, the Board affirmed the Examiner's rejections of claims 1-2,7-8, 10 and 14 as anticipated by Inagaki, and claims 1.-5, 7 -8, 10-12, 14, 26, 28-32, and 34-35 as obvious over iAPX Manual/Specification and Inagaki. Al-34. This appeal followed. On August 14,2012, NVIDIA moved to be voluntarily dismissed from this appeal. CAFC Docket 2012-1634 (entry 25).
III.
STATEMENT OF THE FACTS A. Dynamic Random Access Memory (DRAM) Technology
In general, this case relates to how a computer's memory stores, sends and receives information. Computers store and retrieve information in digital form on some type of memory. A1766 (Murphy Decl.
~13).
One type of memory
discussed in the '097 patent is called Dynamic Random Access Memory ("DRAM"). A60, col. 6, lines 13-16. DRAMs store information "dynamically" which means the memory must be periodically refreshed because the data stored in
4
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the memory cells is lost over time. A1766 (Murphy Decl.
,m 15-16).5 The phrase
"random access" refers to the ability to retrieve specific data from any physical location in an array of memory cells randomly, i.e., the data need not be accessed in a specific order. A1766-67 (Murphy Decl.
n 13-20).
According to Rambus, most conventional DRAM memory operated nonsynchronously prior to 1990, i.e., reading from and/or writing to memory did not occur in response to an external clock signal. Br. at 7. Rambus asserts that using an external clock signal to time the reading and writing of memory data is a "hallmark" characteristic of a synchronous memory device. rd. Rambus also asserts that the '097 patent, with a priority date of April 18, 1990, claims a novel way to synchronously "write" information to a memory device, i.e., timing the writing of data by both the rising and falling edges of an external clock signal. 6
B.
The Claimed Invention (the '097 Farmwald Patent): A Method of Controlling a Synchronous Memory Device
The '097 Farmwald patent discloses a method of controlling a memory
See A3407 (Intel, Memory Components Handbook (1985) ("[D]ynamic RAMs require periodic charge refreshing to maintain data storage.".
5
Figure 8 (b) of the '097 patent shows a graphical representation of the rising and falling edge of a clock signal used as a trigger or synchronizing signal. See A50; A67, col 19, lines 16-23.
6
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device.? A41 (abstract). The method includes synchronizing (timing) the writing of information to a memory device in response to an external clock signa!. A41 (abstract); see also A69-70, co!. 24, line 60-co!. 25, line 6 (claim 1). Operationally, the '097 patent uses a controller to send data requests (e.g., control data) to a memory device. A46 (Fig. 4); A60, co!. 6, lines 17-18. The control data may include an operational code that indicates whether a request is to "read" or to "write" data. A12-13; A62, co!. 9,1-3,38-55. The control data can also include information defining the amount of data to be transmitted. See A46 (Fig. 4); A63, col. 11, lines 38-60. Once the memory controller issues write requests to a memory device, the memory device samples portions of data which is then written to the memory based on an external clock signal. See A41(abstract); A60, co!. 6, line 53-co!. 7, line 16; A62, co!. 9, lines 10-12,18-22,45-62. In particular, data is sent to a memory device "synchronously" with respect to an external clock signal, i.e., the writing of data to the memory occurs on both ? The '097 specification explains that memory devices are "slave devices," which respond to control signals that have been sent along a bus by a "master" or controller device. A60, co!. 6, lines 13-24. While examples of a single chip "memory device" are shown, the specification also describes multi-chip embodiments. See A67, co!. 20, lines 5-8; A51 (Fig. 9); see also In re Rambus, 694 F.3d 42,50 (Fed. Cir. 2012) (construing "memory device" as a component of a memory subsystem, not limited to a single chip). Rambus mentions that there is a "pending petition for panel rehearing in In re Rambus." Br. at 64. That petition was denied on December 12,2012. See CAFC docket 20ll-1247 (entry 37). 6
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the rising and falling edges of the external clock signal. A41 (abstract); A69-70, col. 25, lines 1-6. Claim 1, which is representative of the claims on appeal, is below: 1. A method of controlling a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises: issuing a write request to the memory device, wherein in response to the write request, the memory device samples first and second portions of data; providing a first portion of data to the memory device synchronously with respect to a rising edge transition of an external clock signal; and providing a second portion of data to the memory device synchronously with respect to a falling edge transition of the external clock signal. See A69-70, col. 24, line 60-col. 25, line 6 (emphasis added).
C.
The Prior Art

1.
Inagaki8 (Japanese patent publication)
Inagaki discusses methods of increasing data transfer (read/write) rates with computer memory devices. 9 A2954. Inagaki explains that conventional methods
8
9
Inagaki, JP 57-210495 (Dec. 24,1982). A2944-2952; A2953-2967.
Inagaki's states that it allows access to "memory that transfers data with a speed that is twice the conventional speed, by performing 1/0 of data on every half-cycle of the external clock." A2955, ~ 4.
7
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used to increase data transfer rates in RAM devices include increasing the bus width, however, such methods increase the physical structure of the memory. Id. Inagaki arrived at an alternative solution that doubled the data rate by synchronizing (i.e., timing) data transmission with both rising and falling edges of an external clock without increasing the clock rate. See A2956,
~
3. That is,
Inagaki's system performs "data input or output every half-cycle based on an external clock." A2954, line 3 (Inagaki's claim 1). Specifically, Inagaki states that its memory device is "synchronized" with an external clock, i.e., the reading and writing of data is timed by the rising and falling edges of an external clock signal (twice per clock cycle). A2955,
~
3 ("I/O shift register drive clocks <pI and
<p2" are "synchronized by an external clock <po ").10 In this way "one bit can be
output on each half-cycle" of the external clock and "the operating speed can be doubled." Id. See also A2957, ~~ 3-4 (alternative embodiment of Fig. 7). Thus, Inagaki explains that it improves the efficiency over conventional systems by transferring "data with a speed that is twice the conventional speed, by performing I/O of data on every half-cycle ofthe external clock." A2955,
~~
3-4.
Alternatively, Inagaki's Figure 3 embodiment shows that once "clocks <pI and <p2 are generated on the rise of external clock <p, and the I/OI signal is sent to the data output buffer," then "clocks <p 1 and <p2 are generated on the fall of external clock <p and the 1/02 signal is sent to the data output buffer." A2956, ~ 6 (emphasis added).
10
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To input and output data, Inagaki issues "read" and "write" request signals to its memory device. That is, Inagaki states that "an I/O shift: register ... uses [a] read circuit to perform parallel reading of signals so as to continuously read data [i.e., a read operation]," or "reads an external signal to perform parallel reading of data into the memory cells [i.e., a write operation]" wherein the "110 shift: register performs data input or output every half-cycle based on an external clock." A1060; A2955, ~ 5. 11
2. iAPX Manual: 12 A Memory Module Controlled by a Bus Controller
The iAPX Manual describes a memory device with an array of memory storage chips and one or more controllers that provide logic for those chips to function. A2984-2985 (Fig. 1-2). A memory bus (i.e., MACD bus) provides the principal communication path carrying all memory access requests and interprocessor communications. A2986. The memory arrays of the iAPX include high-density dynamic RAM (DRAM) components. A2986,
~
1. The iAPX
Manual also describes a bus interface unit (BIU) that works with a general data
Inagaki also specifically claims that its system "reads an external signal to perform parallel writing of data" to memory. A2966 (claim 1.)
II
iAPX 432 Interconnect Architecture Reference Manual (Intel Corp.) (1982). See A6, n.2; A2969-3220.
12
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processor (GDP) and "accepts ... access requests from an iAPX 432 processor" and "decides which memory bus( es) will be used to perform the access." A2985. The BIU issues data packets that include write requests to a memory control unit (MeU). See A16 ("iAPX BID ... sends ... a write request to the MeU"); A1077-1078; A321 0-3211 (Table F-I showing write requestformats). In response to a write request, the Meu "performs the necessary access sequencing to read or write data into the [memory] storage array." A20; A1078; A2986,
~
1. The
memory bus is clocked and therefore iAPX's interface between the MeU and its memory device is synchronous, i.e., data is packetized on the bus and sent synchronously to the memory array with respect to a rising edge of an external clock signal (i.e., sending data to memory is triggered by an external clock signal).13 The iAPX system also uses dual clock edges of two different periodic clocks for various functions. A22-23; A1638-1640 (citing Al 078 and A3285).14
13 See Al 078 (Examiner found iAPX teaches request and reply messages are sent synchronously since they are packetized on a clocked memory bus) (citing A3029-3030 (discussing clock cycle lock step operation); A3211(Request message formats, Table F-l); A3212 (Reply message formats, Table F-2. 14 Further, when multiple processors seek access to a shared memory, iAPX's BIU controls interleaving the requests which "spreads the accesses to a common segment of memory across several memory buses." A2986. 10
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3.
iAPX Specification 15
It is undisputed that the iAPX specification describes the same system as the
iAPXManual. 16 A15, n.8; A1642. Essentially, the iAPX specification "presents electrical specifications for the iAPX 432 interconnect components" along with examples of how to interface the components with processors. A3242,
~
1. The
iAPX specification discloses that its BIU inputs and outputs data in response to the rising and falling edge transitions of a clock (e.g., CLKB). A3285.
D. The Board's Decision and the Examiner's Answer
The Board affirmed the Examiner's rejections of: (i) claims 1-2, 7-8, 10 and 14 as anticipated by Inagaki, and (ii) claims 1-5, 7-8,10-12,14,26,28-32, and 34-35 as obvious over iAPX (Manual and/or Specification) and Inagaki. AI-34Y
Electrical Specification for iAPX 43204 Bus-Interface Unit (BIU) and iAPX 43205 Memory Control Unit (MCU) (Intel Corp.) (March 1983). See A6, n.4; A3239-3345.
15
The iAPX Specification cross references the iAPX Manual. A3242 ("More information about the interconnect system is available in: iAPX 432 Interconnect Architecture Reference Manual (Manual Order #172487-001)").
16
Since the Board affirmed the Inagaki anticipation rejections and the obviousness rejections (based on iAPX and Inagaki), it did not reach the rejections based on another reference, Budde. A33. For reference purposes, Budde is found at A3223-3237 (Budde, et. aI., U.S. Pat. No. 4,480,307 (Oct. 30, 1984.
17
11
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1.
Anticipation
The Board found Inagaki discloses a method of controlling a synchronous memory device, including the use of an external clock and a write request as set forth in claim 1. A6-14. And, that "Inagaki describes an 'external clock' and bits [of data] that are input (written) based on internal clocks synchronized [by] the rising and falling edges of that external clock." A8. Further, the Board found "Inagaki's clock is periodic 'at least during ... data input'" operations. Id. The Board also agreed that the Examiner's interpretation of the term "clock" comports with the industry meaning, i.e., "a source of accurately timed pulses, used for synchronization in a digital computer." A8, n.S (citing A36 (McGraw-Hill Dictionary of Scientfic and Technical Terms 387 (Sth Ed. 1994). Rejecting Rambus's assertion that Inagaki's "clock" is not continuously periodic because it only operates during data input/output operations, the Board noted that "[t]he '097 patent does not disclose a computer clock that runs forever or that cannot be turned off." A9. The Board also explained that claim 1 only requires "that the clock runs during data inputs to synchronize data transfers and Inagaki's clock 'at least shows a limited periodic duration. '" Id. The Board found Inagaki discloses a signal that represents a "write request" as claimed. A9-1O. Rambus argued that Inagaki "did not identify a signal that
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distinguishes between a read and a write," but the Board explained that "Inagaki's RAM memory device necessarily must distinguish between a read and write; otherwise, it could not function as the well-known 'RAM' and perform input and output (110) of data." AI0. Confirming that Inagaki identifies a signal that distinguishes between "read" and "write" operations, the Board noted that the Examiner relied upon: (i) Inagaki's amended claim 1 (A2966), which "recites that the block memory 'reads an external signal to perform parallel writing of data into said memory cells, '" and (iii) Inagaki' s description of Figure 5 states that "data that is to be input or output to the 110 buses is read or written." AI0 (citing AI070 (RAN)). Thus, the Board found Inagaki disclosed an "external signal" that corresponds to the claimed "write request," and in response to that signal, Inagaki's system writes data to its RAM. Id. 18 Rambus also argued that Inagaki' s temporary storage of data in a shift
Although Rambus appears to have dropped the argument, the Board recognized that claim 1 does not require the "write request" to be issued synchronously with respect to the external clock as Rambus asserted to the Board. AlO-ll. Rather, claim 1 requires "providing 'the portion[s] of data to the memory device synchronously with respect to ... an external clock'" which occurs after the write request has issued. AI0. In support of its reading, the Board compared claim 1 with claim 26. AI0-11; A70, col. 25, lines 1-2 (claim 1 first requires "issuing the write request" and then requires "providing a first portion of data to the memory device synchronously"); A71, col. 27, lines 36-37 (claim 26 requires "the memory device samples the write request synchronously").
18
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register foreclosed it from teaching a write request or write operation because any write operation signals would not occur until after storage in the shift register. All; AI623. The Board did not agree that Inagaki's shift register embodiment worked that inefficiently, but even if it did, the Board found that Inagaki also teaches non-shift register embodiments and therefore, regardless of the arrangement, the Board found Inagaki discloses that a write request and write operation still occurs. Al1-12Y The Board also rejected Rambus's argument that the claimed "write request" mandatorily required a "series of bits." AI2-13. The Board determined that "claim I does not define [or limit] a 'write request' [to] a 'series of bits.'" Al3. In fact, Rambus's own expert, Mr. Murphy, declared that a write request could be "the state of a signal at a particular time" which shows that the claimed write request is not necessarily a series of bits. A12; Al810 (Supp. Dec!. at 20). While the '097 specification showed examples with a "series of bits" carried by a
The Examiner also found that Inagaki's received external signals qualified as a "write request" because "even amended claim I ofInagaki discloses [] performing 'parallel writing of data into said memory cells.'" AI070; A2969. Further, the Board found that Inagaki teaches another signal meeting the claimed "write request," i.e., an '''address signal ... [which is supplied to] a data input buffer that latches these signals and supplies data to the memory cells'" wherein the I/O shift register performs data input or output every half-cycle based on an external clock. AI2; AI071 (RAN) (citing Inagaki at A2955)).
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request packet, the Board explained that a request packet is not synonymous with a "write request." Al3. Moreover, Mr. Murphy declared that the "operation code" of dependent claim 2, which further qualifies claim l's "write request," only required "one or more bits to specifY a type of action." A13. Thus, the Board reasoned that even if claim 1 did require a series of bits, a single bit was sufficient. Al3-14.20 Accordingly, the Board found that Inagaki sufficiently disclosed a "write request" as claimed and Rambus had failed to show any error in the Inagaki anticipation rejection. A14. 2. Obviousness
The Board found that iAPX's bus interface unit (BIU) sends write requests to a memory control unit (MeU) which is a synchronous interface to a memory device (i.e., memory arrays) and that data is sent synchronously with respect to rising clock edges. A16; AI075-1081 (adopting NVIDIA's rationale at A27082808). Although iAPX synchronizes the writing of data to a memory timed by the 20 The Examiner noted the specification describes an operation code as merely a "type of access," rather than a "series of bits." Al 073. Further, the Board found "Inagaki's memory device processes digital signals including an operation code which signifies a write action and reasonably constitutes a bit, even if a 'bit' is somehow different than a signal." AI4 (Mr. Murphy's conclusion "fails to explain adequately why Inagaki's signal is not the same as 'the state of a signal at a particular time' which Mr. Murphy testifies corresponds to the op code and write request."). 15
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rising edge of an external clock, it does not additionally show the use of the falling clock edge as claimed. Accordingly, the Board found that iAPX teaches all limitations of claim 1 except for providing data on both the rising and falling edges of the clock signal- but determined that an ordinary artisan would have found it obvious to modify iAPX's system to use both the rising and falling clock edges as taught by Inagaki. A16; AI075-1081; A2801-2804 (claim chart). Rambus argued to the Board that iAPX's system was insufficient because it did not disclose a "single chip" memory device - but the Board previously determined in other related cases that the "memory device" did not require a single chip. AI6-18. As such, the Board incorporated the previous findings. A17. Notably, one ofthe incorporated decisions was appealed to this Court, which agreed that Rambus's memory device is not restricted to a single chip. Rambus, 694 F.3d at 50 (construing "memory device" as not limited to a single chip). The Board also rejected Rambus's argument that iAPX's memory device and Inagaki's teachings were not combinable. A22-29. In particular, the Board rejected Rambus's argument that the two references must be physically combined with an actual substitution of elements. A22 (citing In re Sneed, 710 F .2d 1544, 1550 (Fed. Cir. 1983)). While iAPX did not disclose the use of both rising and falling clock edges (i.e., dual edge clocking) of an external clock in the same way, 16
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the Board noted that the iAPX system employs dual edges oftwo different periodic clocks demonstrating that iAPX already had the circuitry available to send/receive data on both edges. A23 (citing A2772). Further, Inagaki teaches using dual edges of a single clock to increase speed or reduce the number of data paths in a memory device. A22-23. In light ofInagaki's and iAPX's similarities and common goals, the Board found that a skilled artisan would have recognized how to apply Inagaki's technique of using both the rising and falling edges of an external clock to time the writing of data to memory to improve iAPX's memory device that samples and writes data on just the rising edge of a clock. 21 A23-2S; AI092-1093 (RAN); A2771-2773; A2S07-2S0S. Thus, the Board explained that "Inagaki's teachings, and the iAPX use of dual edges, evidence a reasonable expectation of success in using dual clock edges on data for increased speed" - and - "[i]ncreased speed and compactness by reducing bus width and corresponding pin number while saving cost[] constitute The Board found that Inagaki teaches fast clocks can be created by using dual edges of slower external clocks which suggests using a similar external clock to trigger the internal clocks in iAPX's system. A25-26. Further, the Board noted Rambus's argument that "complex systems like iAPX's cannot have significant features replaced by other features" were not commensurate with broad claim 1. A25. As the Board found, "skilled artisans easily could have modified the iAPX system in view ofInagaki's clocking scheme by dropping, instead of replacing, many functions" thereby "creat[ing] a 'cleaner' memory device for handling mere one way data transfers embraced by broad claim 1." A25.
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universal motivators" supporting its obviousness conclusion. A24.
3.
Secondary Considerations
Finally, the Board found Rambus's secondary consideration evidence to be unpersuasive. A29-33. The Board explained that Rambus failed to show a nexus between any alleged solution to a long-felt need and features in claim I, failed to show its evidence was commensurate with the scope with claim 1, and failed to offer evidence establishing an inventive solution to a long-felt problem at the time of filing ofthe '097 patent. A30-3l. Notably, regarding its long-felt need evidence, the Board pointed out that claim 1 does not require any specified higher performance, recite any bottleneck problem, or recite any specific clock speed. Yet, Rambus's evidence almost solely focuses on these features or other features that did not appear in claim l. Therefore, the Board found that Rambus's evidence had no nexus to claim l. A30. Regarding evidence of commercial success, Rambus had not shown that any such success was not due to features found in other known devices. A31. Similarly, with regard to commercial success by way oflicensing, Rambus did not point to any evidence that the licenses were not due to other reasons besides claimed features - nor did Rambus explain what claimed features the licenses pertained. A31. 18
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Ultimately, the Board found that Rambus's arguments and evidence suggested that many unclaimed features may have contributed to commercial success, e.g., delay-locked loop, multiplexed buses, clocks and memory controllers or other features that may have appeared in other patents in the same family, but not in claim 1 of the '097 patent. Thus, Rambus's evidence was neither commensurate with the scope of claim 1, nor did it satisfy the nexus requirement and therefore, did not overcome the strong prima-facie case of obviousness.
IV.
SUMMARY OF THE ARGUMENT

Claim 1 recites a method of controlling a computer memory including the
steps of issuing a "write request" to a memory device and, in response, data is written to the memory on both the rising and falling edges of an external clock signal (i.e., writing of data is timed by the rising and falling edges of an external clock). Such a method was already known, as disclosed by Inagaki, a 1981 Japanese patent publication, which shows a memory device that receives a signal representing a "write request," and in response to that signal, writes data to its memory synchronized by the rising and falling edges of an external clock signal. Accordingly, Inagaki anticipates claim 1. Rambus asserts that the Board improperly construed the terms "external clock signal" and "write request." In Rambus's view, the "external clock signal" 19
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must be continuously periodic and Inagaki's clock does not quality because it only runs intermittently during "data input." But claim I is not so limited; rather, it only requires an external clock be periodic for a limited duration, i.e., while writing data to a memory device. Further, as the Board found, the term "clock" has an industry meaning - a source of accurately timed pulses, used for synchronization in a digital computer - which is precisely what Inagaki's external clock is. As Inagaki states, it doubles its data rate by synchronizing data transmission timed by both rising and falling edges of an external clock. Thus, although Inagaki's external clock may only run during data input/output operations, claim I simply requires that data be written to a memory device synchronously with respect to a rising and falling edge of an external clock signal - which is precisely what Inagaki discloses. Rambus also argues the claimed "write request" must be limited to a "series of bits." But claim 1 does not limit a "write request" to only a "series of bits"; it simply recites "issuing a write request to a memory device." While the '097 specification shows examples of write requests using packets that include a series of bits, the claims are not so limited. In fact, Rambus's expert, Mr. Murphy, declared that the claims do not require any packets and a non-packetized protocol may be used to transmit write requests. Further, Mr. Murphy declared that an 20
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operation code, which can be included in a "write request," only requires "one or more bits to specifY the type of action." In fact, the '097 patent states a write or read operation code can be either a "1" or a "0" to specifY a read or write operation which supports that a write request can be a code of either a "1" or "0." Moreover, Mr. Murphy declared that a write request or operation code could be "the state of a signal at a particular time" which means it need not necessarily be a series of bits but could be some other signal. With that fact in mind, the Board found the "write request" could be a high or low voltage signal which can signifY a write or read operation. Because write requests and operation codes can correspond to "the state of a signal at a particular time" and need not necessarily be a series of bits, the Board properly detennined Inagaki's write signal satisfied claim 1. Further, the Infineon case, relied upon by Rambus, does not undennine the Board's construction. Although Infineon addressed a different patent in the same family (with the same specification), consistent with the Board's reading, Infineon held that a "request packet" is distinct from a read request or write request. And, even though Infineon detennined a write request means "a series of bits used to request data," it did not decide that such a series could not correspond to a single bit signal or that a write request could not be some other signal. That simply was not at issue in that case.
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IfInagaki fails to anticipate claim 1, iAPX in view ofInagaki renders claim 1 obvious. The iAPX Manual discloses all the limitations of claim 1 except for the use of a "falling edge." But, Inagaki teaches using dual edges of a single clock to increase speed and reduce the number of data paths in a memory device. Further, iAPX's system employs dual edges of two different clocks, which shows it already has the circuitry available to send/receive data on dual clock edges. In light ofInagaki's and iAPX's similarities and common goals, a skilled artisan would have been motivated to apply Inagaki's use of both the rising and falling edges of an external clock signal to synchronously trigger the writing of data to a memory to improve iAPX's memory device. Contrary to Rambus's argument, the Board did not ignore that iAPX's system discloses using only one clock edge for data transfer and uses the remaining clock edges for other functions. Rather, the Board addressed that precise point which led to its recognition that iAPX's system already had the circuitry available to perform dual edged clocking - it merely needed to use its existing circuitry in a different way. Simply because iAPX's existing dual edged clocking circuitry may have been used to transmit other types of data, did not mean that it could not be used to improve the speed of its memory writing function in accordance with Inagaki's teachings. As the Board found, making other
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modifications to increase iAPX's speed by using both clock edges, as Inagaki teaches, does not defeat obviousness or show inoperability. KSR Int'l Co. v. Teleflex, Inc., 550 U.S. 398, 424 (2007) ("[T]he interaction of multiple components means that changing one component often requires others to be modified as well."). Finally, Rambus's secondary consideration evidence is unpersuasive. As the Board found, Rambus did not show a nexus between claim 1 and any alleged solution to a long-felt need, nor did it show its evidence was commensurate with the scope of claim 1. Rambus's secondary evidence almost solely focuses on specified higher performance and specific speed increases (e.g., touted as five to ten times faster). But none of these specific features are found in claim l. Rather claim 1 is broad enough to encompass devices like those in the prior art (e.g., the combination of iAPX and Inagaki which only double the speed) that simply synchronize the writing of data triggered by both the rising and falling edge of an external clock. Similarly, with regard to evidence of commercial success and success by way oflicensing, Rambus did not establish a nexus or that such evidence was commensurate with the scope ofthe claim. That is, Rambus did not show that any such evidence was not due to other features found within other known devices or that other non-claimed factors were the motivators for the 23
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alleged success or drivers behind the licenses. As the Board found, Rambus's arguments and evidence suggested that many features not found in claim 1 may have contributed to commercial success, e.g., delay-locked loop, multiplexed buses, packetized control or other features claimed in other patents in the same family. Thus, since Rambus's evidence is not commensurate with the scope of claim 1 and does not satisfY the nexus requirement, it does not overcome the strong prima-facie case of obviousness.
V.
ARGUMENT
A. Standards of Review
Rambus bears the burden of demonstrating reversible error by the Board. In re Watts, 354 F.3d 1362, 1369 (Fed. Cir. 2004). The proper interpretation of claims is a question oflaw reviewed de novo on appeal. Rambus Inc., 694 F.3d at 46 (citing Cybor Corp. v. FAS Techs., Inc., 138 F.3d 1448,1454 (Fed. Cir. 1998) (en bane. While claims are generally given their broadest possible scope during prosecution, In re Hyatt, 211 F.3d 1367, 1372 (Fed. Cir. 2000), the Board's construction of the claims of an expired patent is similar to that of a district court's. Rambus, 694 F.3d at 46 (citing Ex Parte Papst-Motoren, 1 US.P.Q.2d 1655, 1655-56 (BPAI Dec. 23, 1986. While the "claims must be read in view of the specification," which "is the single best guide to the meaning of a disputed 24
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term," Phillips v. AWH Corp., 415 F.3d 1303 (Fed. Cir. 2005) (en bane), the agency must be careful not to improperly read limitations from the specification into the claims. See In re ZIetz, 893 F.2d 319,321 (Fed. Cir. 1989); see also Papst-Motoren, 1 USPQ2d at 1657 (the agency is "mindful that it has been held improper for 'inferential limitations' to be added to a claim.")). Obviousness is a question of law based on underlying fact findings. See KSR, 550 U.S. at 427; In re DBC, 545 F.3d 1373, 1377 (Fed. Cir. 2008). What a reference teaches, including whether it teaches toward or away from the claimed invention, is a question of fact. Para-Ordnance Mfg. v. SGS Importers Int'l, 73 F.3d 1085, 1088 (Fed. Cir. 1995). Anticipation is also question of fact. In re Hyatt, 211 F.3d 1367, 1371 (Fed. Cir. 2000). In addition, an inherent teaching of a prior art reference is also a question of fact which arises both in anticipation and obviousness. In re Napier, 55 F.3d 610,613 (Fed. Cir. 1995). This Court upholds the Board's factual findings unless they are unsupported by substantial evidence. In re Gartside, 203 F.3d 1305, 1316 (Fed. Cir. 2000). Substantial evidence "is something less than the weight of the evidence but more than a mere scintilla of evidence," In re Kotzab, 217 F.3d 1365, 1369 (Fed. Cir. 2000), and "means such relevant evidence as a reasonable mind might accept as adequate to support a conclusion," 25
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Consolidated Edison Co. v. NLRB, 305 U.S. 197,229 (1938). Further, if"the evidence in [the] record will support several reasonable but contradictory conclusions," then this Court "will not find the Board's decision unsupported by substantial evidence simply because the Board chose one conclusion over another plausible alternative." In re Jolley, 308 F.3d 1317, 1320 (Fed. Cir. 2002).
B. Representative Claim 1 is Anticipated by Inagaki
Anticipation requires two steps. First, the claim must be properly construed. Elmer v. ICC Fabricating, Inc., 67 F.3d 1571, 1574 (Fed. Cir. 1995). Second, the construed claim is compared to the prior art to determine whether all the limitations ofthe claims are disclosed in the prior art. rd. Here, claim 1, which is representative 22 ofthe claims on appeal, requires the following: 1. A method of controlling a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises: issuing a write request to the memory device, wherein in response to the write request, the memory device samples first and second portions of data;
Rambus acknowledges that claim 1 is representative of the claims on appeal. Br. at 15. Since Rambus does not argue any other appealed claims separately, they stand or fall with claim 1. In re Dance, 160 F.3d 1339, 1340, n.2 (Fed. Cir. 1998). Rambus does not appeal the rejection of claims 8, 10-12 and 14. Br. at 3, n.1.
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providing a first portion of data to the memory device synchronously with respect to a rising edge transition of an external clock signal; and providing a second portion of data to the memory device synchronously with respect to a falling edge transition of the external clock signal. See A69-70, col. 24, line 60 - col. 25, line 6 (emphasis added). As the Board and Examiner found, each element of claim 1 is disclosed by Inagaki. A6-14; A1059-1079. That is, Inagaki discloses a method of controlling a synchronous memory device with a plurality of memory cells (AI 059-1060) that includes: (1) issuing a write request to the memory device, and, in response, (2) the memory device samples first and second portions of data (AI 060) and data is provided (written) to memory synchronously with respect to both a rising and falling edge transition of an external clock signal (AI 061-1 062). See also A6-8 (Board's Fact Findings 11-17); see also A2793-2796 (NVIDIA's claim chart). Accordingly, the Board found claim 1 to be anticipated by Inagaki. A14. Rambus argues that: (i) Inagaki fails to disclose a "synchronous memory device" because, according to Rambus, the Board improperly construed "external clock signal" as that phrase is used in the '097 patent (Br. at 46-51), and (ii) the Board improperly construed the claim term "write request." Br. at 51-56. Rambus's arguments, however, have no merit because they attempt to narrow the 27
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ordinary meaning of the claim terms by improperly importing limitations from the specification into the claims and they ignore substantial evidence supporting the Board's findings regarding Inagaki's disclosure.
1. Inagaki Discloses an "External Clock Signal" and a "Synchronous Memory Device" as Those Terms are Properly Construed
Rambus argues that the Board failed to properly construe the claim term "external clock signal." Br. at 46. According to Rambus, the "'external clock signal' must be continuously periodic" in order for the claimed "memory device" to operate as a "synchronous memory device." Br. at 46. While Rambus recognizes that Inagaki uses an external clock, it asserts that it is only periodic during intermittent periods (i.e., during data transfer) and thus, under Rambus's theory, Inagaki fails to disclose a synchronous memory device. Br. at 50-51. First, Rambus reads limitations into claim 1 that are not found in the claim or required by the specification. Specifically, Rambus's argued limitation of "continuously periodic" does not appear in claim 1. Id. Rather, claim 1 simply requires that data is provided (written) to a memory device synchronously with respect to a rising and falling edge of an external clock signal. In pertinent part, claim 1 recites a "method of controlling the memory device" comprising the steps of "issuing a write request to the memory device" wherein data is provided to the
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memory device "synchronously with respect to a rising edge transition" and the "falling edge transition" of "an external clock signal." See A69-70, col. 24, line 60 - col. 25, lines 6. Further, the '097 specification does not provide any specialized definition or lexicography, but at best shows examples of preferred embodiments. It is settled that claim scope cannot be limited by a preferred embodiment described in the specification. Phillips, 415 F.3d at 1323 ("For instance, although the specification often describes very specific embodiments of the invention, we have repeatedly warned against confining the claims to those embodiments ... "). In fact, the specification states that "persons skilled in the art will recognized that many variations of the teachings of this invention can be practiced that still fall within the claims." A60, col. 24, lines 57-59. Second, contrary to Rambus's assertion, Inagaki discloses an external clock that is sufficiently periodic to satisfy the requirements of claim 1. Specifically, Inagaki describes an "external clock signal" and the writing of data to a memory that is synchronized with respect to the rising and falling edges of that external clock signal. AS. Inagaki expressly states that its "drive clocks <pI and <p2" are "synchronized by an external clock <p." A2955, ~ 3. Inagaki explains that it doubles the data rate by synchronizing data transmission triggered by both rising and falling edge transitions of an external clock without increasing the clock rate. 29
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See A2956,
3 (When "[t]he rise and fall ofthe external clock q> are detected, and
clocks q> 1 and q>2 are generated" then "[c]locks q> 1 and q>2 drive shift pulses of the shift register ... [and] [i]n this way, since one bit is output on each half-cycle, the operating speed is twice that ofthe conventional speed."). In Inagaki's words, its system performs "data input or output every half-cycle based on an external clock." A2954, line 3 (Inagaki's claim 1). Accordingly, by timing the writing of data to its memory with respect to the rising and falling edges of an "external clock," Inagaki synchronizes the writing of data to memory. A2955,
~
4. And,
Inagaki explains that its dual edged clocking technique improves efficiency by transferring "data with a speed that is twice the conventional speed, by performing [input/output] I/O of data on every half-cycle ofthe external clock." Id. Rambus points to the Examiner's finding that Inagaki's clock is periodic "at least ... during data input." AI069; see also Br. at 27-30 (arguing the Examiner found the "external clock" to be satisfied by an intermittent, nonperiodic signal). And, according to Rambus, this means Inagaki's clock is not sufficiently periodic to synchronize the writing of data to memory as claim 1 requires. Further, Rambus asserts that the Board erred when it relied on the Examiner's rationale that the "claims need only cover a certain moment, such that the external clock need only be periodic for a limited duration." Br. at 50. 30
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However, as the Board explained, the Examiner's interpretation of the term "clock" comports with the industry meaning, i.e., a "clock" is a source of accurately timed pulses, used for synchronization in a digital computer. AS. That is precisely what Inagaki does - it uses an external clock as a source of accurately timed pulses to synchronize writing of data to its memory. Further, Inagaki expressly states that it "synchronizes" the reading and writing of data to a memory with respect to an external clock signal. A2955, ~ 3 ("110 shift register drive clocks <pI and <p2," which cause reading or writing data to memory, are "synchronized by an external clock cp."). Thus, even ifInagaki simply synchronizes intermittently (e.g., during read and write operations) that is enough, as claim 1 simply requires that data is written to a "memory device synchronously with respect to a rising edge transition of an external clock" and "with respect to a falling edge transition of the external clock" - precisely what Inagaki discloses. Moreover, Inagaki describes its clock as having a "cycle."
~
See,~,
A2955,
3 ("In this conventional example, one bit is output for each cycle of the clock <po .
."); A2957, ~ 3 ("Clock <pI is generated synchronously with the external clock <po Clock <p2 is a waveform that is a half cycle later than <p 1."). As NVIDIA pointed out to the Board, a "cycle" is a "complete range of states or magnitudes through which a periodic waveform or periodic feature passes before repeating itself 31
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identically." A2762 (citing IEEE Dictionary (1988) at A3397-3400). The fact that Inagaki's clock goes through cycles means that it is sufficiently periodic to satisty the clocking functions of claim 1. Thus, to the extent the "external clock" of claim 1 needs to be periodic so it can synchronize the writing of data to a memory based on a rising and falling edge clock of a signal, Inagaki' s external clock satisfies that requirement. Additionally, while this Court is not bound by a district court's claim construction, we note that the Northern District of California recently refused to adopt Rambus's narrow reading of "external clock signal" and instead agreed with the Board's construction, i.e., that "the claimed clock signal must be continually present 'during data inputs to synchronize data transfers,' not at all times." See Rambus v. LSI v. STMicroelectronics, 2012 WL 4466578, *7 (ND. Cal. 2012). That is, the claimed clock signal is "a periodic signal [that] may be intermittent, e.g., present during read or write operations, without being always present." Id. 2. The Board Properly Construed the Term "Write Request"
Rambus also argues that the Board erred in its construction of the claim term "write request." Br. at 51-56. Rambus asserts that the claimed "write request" must be limited to a "series of bits" and it cannot be read to include some other type of signal or a signal based on a single bit. Br. at 51. 32
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But, as the Board and Examiner explained, claim 1 does not limit the term "write request" to a "series of bits." A13; see also AI073. And, Rambus cannot read into the claims the additional limitation of a "series of bits" simply because it appears in certain embodiments in the specification. See Phillips v. AWH Corp., 415 F.3d 1303, 1323 (Fed. Cir. 2005) ("[A]lthough the specification often describes very specific embodiments of the invention, we have repeatedly warned against confining the claims to those embodiments."); see also CCS Fitness, Inc. v. Brunswick Corp., 288 F.3d 1359, 1366 (Fed. Cir. 2002) (explaining that the presumption of ordinary meaning cannot be rebutted "simply by pointing to the preferred embodiment or other structures or steps disclosed in the specification or prosecution history").
In contrast to Rambus's argued construction, claim 1 simply recites "issuing

a write request to the memory device." A69, col. 24, line 65. While the '097 patent includes examples of a write request using packets (that include a series of bits), the claims do not limit the "write request" to the use of packets. In fact, the portion of the' 097 disclosure relied upon by Rambus is simply a description of an example where a series of bits are carried by a "request packet.,,23 A62, col. 9, Consistent with the Board (A13), the Examiner found a "series of bits" carried by a packet was merely an example, not a claim requirement. See A10701074 at 1074. See also A2763 ("The claims do not recite a 'series of bits,' but
23
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lines 23-64. Reading the '097 disclosure as a whole, makes clear that a "request packet" is not synonymous with the "write request" recited in claim 1. Indeed, Rambus's own expert, Mr. Murphy, explained "the claims do not require any packet." Al3. In particular, Mr. Murphy declared that an ordinary artisan reading the '097 patent's original disclosure would "understand that a non-packetized protocol may be used to transmit read and write requests." AI771, ~ 35. Further, the '097 disclosure states a "write or read operation code can be either a 1 or a 0 to specifY a read or write." A14 (citing the '097 patent at A62, col. 9, lines 46-55). That is, a "write request" can consist of a single bit or signal (e.g., a "1 "or a "0"). Consistent with the '097 disclosure, Mr. Murphy also declared that the "operation code," as recited in dependent claim 2, which qualifies claim 1 's "write request," only "requires one or more bits to specifY a type of action." Al3; A1794, ~ 122 ("one of ordinary skill in the art would understand an operation code is 'one or more bits to specifY a type of action"'); A 70, col. 25, lines 7-8 (claim 2 states "the write request includes an operation code,,).24 In fact,
generally recite 'issuing a write request to a memory device.' ... While the '097 patent specification does illustrate an embodiment of a write request using packets ... the Examiner agrees that the claims are not limited to the use of packets."). As Rambus notes, claim 2 states the "write request includes an operation code" which means the write request may possibly include other information beyond the operation code. Br. at 54. However, neither claim 1 nor claim 2
24
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Rambus similarly described an operation code as "one or more bits specifying an action" (AI624,
~
2) and the Examiner found that "the specification only states
that an operation code 'specifies a type of action. ", A1074. Thus, the Board had good reason to find that "even if claim 1 somehow requires a series of bits, the series can be a series of one bit." AI3-14. Moreover, Mr. Murphy declared that a "write request" or "operation code" could be "the state of a signal at a particular time" which means it need not be made up of a series of bits but could be some other signal. See A181 0, ~ 20 ("Write requests and operation codes are made up of bits or the state of a signal at a particular time.") (emphasis added). In light ofthe '097 specification, Mr. Murphy's declaration, and Rambus's statements, the Board properly determined that "the operation code recited in dependent claim 2, [] which narrows the write request in independent claim 1, only requires one bit" or some other signal "specify[ing] a type of action" to satisfy the "write request" of claim 1. A13. As the Board explained, an example of such a signal would be "a high or low signal (voltage) level signifies the two possible choices: a write or a read operation code." A14. Accordingly, the Board properly determined "write
mandates that other information beyond an operation code must be included as part of the "write request." 35
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requests and operation codes can correspond to 'the state of a signal' and not necessarily 'a series ofbits.'" AI3-14. Finally, the Infineon case, upon which Rambus relies (Br. at 51-52), does not undermine the Board's construction of the term "write request." See Rarnbus Inc. v. Infineon Technologies, 318 F.3d 1081, 1092 (Fed. Cir. 2003). While Infineon determined a "write request" means '''a series of bits used to request a write of data to a memory device, '" (318 F.3d at 1093), as the Board noted, it "did not decide if such a series could be one bit or a signal." A14, n.7. That issue was not before the Infineon court. Rather, Infineon was focused on holding that a "request packet" is distinct from a "read request" or "write request." See Infineon, 318 F.3d at 1092 ("the specification does not use read request and request packet interchangeably."). Infineon simply did not address whether a "series of bits" could be a single bit, as that was not an issue in that case. Thus, under a proper construction, Inagaki discloses an external signal that corresponds to the claimed write request. As previously noted, Inagaki states, "an I/O shift register ... uses the read circuit to perform parallel reading of signals so as to continuously read data [i.e., a read operation], or that reads an external signal to perform parallel reading of data into the memory cells [i.e., a write operation] .. . wherein: the I/O shift register performs data input or output every half-cycle 36
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based on an external clock." A2955, ~ 5 (emphasis added); see also A1060. And, as the Examiner found, Inagaki's claim 1 states that it "reads an external signal to perform parallel writing of data" to its memory. Al 070-1 071; A2966 (Inagaki amended claim 1). It is hard to understand why this external signal, in a digital environment, could not include one or more bits. Regardless, since the broadly claimed "write request," at a minimum, corresponds to a signal and need not always be a series of bits, the Board properly found that Inagaki's received external signal 25 that directs its memory to read or write data satisfies claim 1. A14; see also AI060.
C.
Representative Claim 1 Would Have Been Obvious in View of the iAPX Manual/Specification and Inagaki
Rambus limits its obviousness arguments to representative claim 1 and does not separately argue the features of any other claims. Accordingly, if the Court agrees that claim 1 is anticipated based on Inagaki, it need not reach Rambus's obviousness arguments. See Dance, 160 F.3d at 1340, n.2. Further, to the extent that Rambus attempts to argue features beyond those in claim 1 in its reply, those
See also AI074 (Examiner found that "[s]ince an operation code 'specifies a type of action' and since the memory device of Inagaki writes data in response to receive [d] signals that cause the memory to write data" that means "the signals of Inagaki include[] an operation code since an operation code merely specifies a type of action to perform."); A2793-2796 (claim chart)
25
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arguments would be waived. See SmithKline Beecham Corp. v. Apotex Corp., 439 F.3d 1312, 1319 (Fed. Cir. 2006) ("Our law is well established that arguments not raised in the opening brief are waived."). A claimed invention is unpatentable if the differences between it and the prior art "are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art." 35 US.C. 103( a). In assessing whether the subject matter would have been obvious, this Court follows the guidance of the Supreme Court in Graham v. John Deere Co., 383 US. 1 (1966) and KSR, 550 US. 398. That guidance provides that the "combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results." KSR, 550 US. at 416. In other words, "[s]ection 103 of Title 35 requires this court to inquire 'whether the improvement is more than the predictable use of prior-art elements according to their established functions.'" Monolithic Power Sys., Inc. v. Micro Int'l Ltd., 558 F.3d 1341,1352 (Fed. Cir. 2009) (quoting KSR, 550 US. at 417). Furthermore, the obviousness "analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim, for a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ." KSR, 550 US. at 418. 38
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Applying these principles, the Board properly found claim 1 of the '097 patent would have been obvious to those of ordinary skill in light of the teachings ofthe prior art, i.e., iAPX Manual/Specification and Inagaki. A15-33.
1. The iAPX Manual/Specification and Inagaki Would Have Rendered the Claims Obvious to the Ordinary Artisan
In pertinent part, claim 1 requires (1) issuing a write request to a memory device that, in response, (2) synchronously provides (writes) data to the memory on both the rising and falling edges of an external clock signal. See A69-70, col 24, line 60 - col. 25, line 6. The iAPX Manual shows each of these elements except that the writing of data to its memory is not synchronized by (i.e., timed by) both the rising and falling edges of a clock signal. 26 See A15-16 (Board's FF A1-3); A1075-1078 (Examiner's findings) (citing iAPX at A2983-2987, A3060, A3209-3212, A30293030); A280 1-2804 (claim chart - iAPX disclosure ).27 That is, iAPX shows
The iAPX Manual shows a processor module using an external clock to control a memory device. A2985 (Fig. 1-2). The iAPX also has bus interface unit (BIU) that sends write requests to a memory control unit, which is a synchronous interface to a memory device and data is sent synchronously with respect to rising edges of an external clock. A16; A1075-1081 (adopting requester's rationale at A2799-2808 (citing iAPX at A2983-2990; A3030; A3060; A3208-3211 )).
26
27 Notably, Rambus acknowledges the "iAPX Specification (at BIU-38) reveals that the BIU inputs and outputs ACD15 .. 0 data (to and from a processor) on the rising and falling edges of CLKB." A28; A1638-1639 (Rambus citing
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synchronized writing timed by only the rising edge of an external clock signal; it does not show the use of the falling clock edge as well. However, Inagaki uses both the rising and falling edges of an external clock signal to synchronize the writing of data to a memory, and an ordinary artisan would have found it obvious to combine Inagaki's teachings with iAPX' s system. As the Examiner and Board recognized, both Inagaki and the iAPX Manual are directed to semiconductor devices, and the iAPX Manual recognizes the need for more bandwidth. Al079 (citing iAPX at A2984). Similarly, Inagaki recognizes a need for more bandwidth and a solution - doubling the speed through the use of both the rising and falling edges of an external clock. Al080 (citing Inagaki at A2955, ~ 4). Thus, not only are the iAPX Manual and Inagaki in the same field but also they seek to solve the same problem; i.e., they both seek to increase the speed and efficiency of memory writing functions. Accordingly, as the Board concluded, "Inagaki's teachings, and the iAPX use of dual [clock] edges, evidence a reasonable expectation of success in using dual clock edges on data for increased speed," and "increased speed and compactness ... while saving cost" constitute universal motivators. A24. Thus, an ordinary artisan in semiconductor field
iAPX Spec., BIU-38 at A3285); A3285 (showing iAPX 43204 Clock Edge Table; "Input/Output" of "ACD 15 .. 0" data based on rising and falling edge of CLKB)). 40
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would have had good reasons to combine the elements of the iAPX Manual and Inagaki. Al 079-1 081. As the Supreme Court has made clear, "if a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond his or her skill." See KSR, 550 U.S. at 417. 2. Rambus's Arguments that Inagaki's Clocking Scheme Would Not be Used with iAPX's System Fail
Rambus argues that since the iAPX system "used only one clock edge for data transfer and used the remaining edges of both clock signals for other functions," an ordinary artisan would never have used the teachings ofInagaki with iAPX's system. Br. at 57; see also Br. at 33-35. Rambus's argument fails for a number of reasons. First, as the Board explained, Rambus's argument amounts to an "unpersuasive assertion that the two systems must be bodily incorporated." A22.
It is well-established that a determination of obviousness based on teachings from
multiple references does not require an actual, physical substitution of elements. See In re Mouttet, 686 F.3d 1322, 1332 (Fed. Cir. 2012); In re Etter, 756 F.2d 852, 859 (Fed. Cir. 1985) (en banc) ("the criterion being not whether the references
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could be physically combined but whether the claimed inventions are rendered obvious by the teachings ofthe prior art as a whole"); In re Sneed, 710 F.2d 1544, 1550 (Fed. Cir. 1983). Rather, the test for obviousness is what the combined teachings of the references would have suggested to those having ordinary skill in the art - it is not whether the reference could be physically combined. Here, an ordinary artisan skilled in the semiconductor memory field would have recognized that Inagaki's dual-edged clocking scheme could be used with iAPX's system, predictably resulting in increased speed and efficiency. See KSR, 550 U.S. at 416 ("The combination of familiar elements according to known methods is likely to be obvious when it does no more than yield predictable results."). Contrary to Rambus's argument, substantial evidence in the record supports the Board's findings - the Board did not merely rely on its "own conjecture" or "say-so" - as Rambus asserts.28 Br. at 58. As the Board specifically found, "Inagaki teaches using dual edges of a single clock in order to increase speed or reduce the number of data paths in a
28 Notably, "[a]s persons of scientific competence in the fields in which they work, examiners and administrative patent judges on the Board are responsible for making findings, informed by their scientific knowledge, as to the meaning of prior art references to persons of ordinary skill in the art and the motivation those references would provide to such persons." In re Berg, 320 F.3d 1310, 1315 (Fed. Cir. 2003). 42
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memory device." A22. Consistent with the Board, the Examiner also found Inagaki's system "provides read/write data at twice the rate of the external clock." AI092. As Inagaki states, it performs "I/O of data on every half-cycle of the external clock" to increase its speed over conventional systems. A2955,
~
4.
These same motivations/desires for increased speed and bandwidth are expressed in iAPX's disclosure. As the Examiner found, "the iAPX Manual recognizes the need for more memory bandwidth" and it also discusses "creat[ing] a [data] pipeline, in which a memory bus can queue up to three memory requests at a time." AI091 (citing iAPX at A2984 ("When more memory bandwidth is required, additional memory ... can be added.") and A2987 ("Each memory bus in an iAPX 432 interconnect system can queue a maximum of three memory requests.")). Accordingly, both Ingaki and iAPX expressly teach that they each seek to improve the speed and efficiency of their respective memory systems. Therefore, the Board had a substantial evidentiary basis to find that an ordinary artisan would have good reason to combine Inagaki's dual edged clocking method with iAPX's system. KSR, 550 U.S. at 402,421 ("When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known 43
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options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense."). Contrary to Rambus's allegations, the Board did not ignore that "iAPX used only one clock edge for data transfer and used the remaining edges of both clock signals for other functions." Br. at 57. Rather, the Board addressed that precise argument in its decision - and it reasoned that, "'the fact that iAPX already uses both rising and falling edges ofthe clock' for other purposes 'means that iAPX already has the circuitry available to send/receive data on both edges' without a shift register." A23 (citing NVIDIA Br. at 2772). Therefore, as the Board found, this feature of iAPX, if anything, makes the claimed invention all the more obvious. Moreover, as the Board recognized, "'[t]he fact that the clock signals are used to transmit many different types of data and control signals does not negate, or render impossible, the ability to transfer data on both the rising and falling edge of a clock. '" A23 (citing NVIDIA's Board brief at A2772). As KSR recognizes, "the interaction of multiple components means that changing one component often requires others to be modified as well." KSR, 550 U.S. at 424. Consistent with this principle oflaw, the Board found that "making other required modifications to increase the data speed by using both clock edges, as Inagaki teaches, does not 44
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defeat obviousness or show inoperability." A25. In light ofthis evidence and reasoning, the Board concluded that "Inagaki's teachings, and the iAPX use of dual edges, evidence a reasonable expectation of success in using dual clock edges on data for increased speed" and "increased speed and compactness ... constitute universal motivators." A24. In contrast to Rambus's assertion that iAPX "teaches away," (Br. at 57-58), these are strong reasons why an ordinary artisan would use the clocking scheme of Inagaki with iAPX's system. See In re Kahn, 441 F.3d 977,990 (Fed. Cir. 2006) (quoting In re Gurley, 27 F.3d 551,553 (Fed. Cir. 1994) ("[ a] reference may be said to teach away when a person of ordinary skill, upon reading the reference, would be discouraged from following the path set out in the reference, or would be led in a direction divergent from the path that was taken by the applicant.")). Finally, Rambus argues that it "showed that, in iAPX, data is held for a full clock cycle during data output" and therefore "the dual edged/double-data-rate feature [is] infeasible" with iAPX. Br. at 34; 57. However, this argument was not properly raised before the Board (A26) and it is therefore waived. In re Watts, 354 F.3d 1362, 1367 (Fed. Cir. 2004). Even ifnot waived, as the Board found, Rambus had not persuasively demonstrated that any inherent "hold" or "delay" times in the iAPX system "necessarily impact the data length on the bus." A27, 45
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n.16. And further, "[s]imilar delays would occur in the '097 patent system." Id. Regardless, even if Rambus's characterizations were correct, the Board explained that "such data holding does not impact the substitution and modification rationales" it had discussed. A27. That is, even ifthere was an inherent "hold" or "delay" time, it does not defeat the strong motivators for an ordinary artisan to modify iAPX's system with Inagaki's dual-edged clocking scheme. To help illustrate its point, the Board explained that, for example, "having rising and falling edges of an external clock trigger the rising [clock B] edges does not impact any timing relying on those rising [clockB] edges, regardless of data hold length." A27. Or "replacing the iAPX system's dual clock system with Inagaki's simpler single clock system to handle simple one-way (or two-way) data transfers, without arbitration or other unneeded functions pursuant to the breadth of claim I" would still involve using dual clock edges. Id. As the Board reasoned, "Inagaki's system provides the fastest speed relative to the dual clock edges regardless ofthe data length, because the speed is ultimately governed by dual edges of the clock or the bus width and the system constraints." Id. Accordingly, the Board made numerous alternative findings showing that claim I would be satisfied, even ifRambus's "data holding" argument were correct. Rambus asserts that "the Board relied on its own conjecture" and its own
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"say-so" rather than relying on the "expertise of the examiner" to make these alternative findings. Br. at 58. Contrary to Rambus's assertion, the Board is entitled to make its own fact findings when interpreting prior art references in order to rebut a new argument and/or evidence.
See,~,
Berg, 320 F.3d at 1315.
And, contrary to Rambus's implication (Br. at 59), the Board is entitled to rely on "common sense" as part of its analysis.
See,~,
KSR, 550 U.S. at 420
("Common sense teaches, however, that familiar items may have obvious uses beyond their primary purposes, and in many cases a person of ordinary skill will be able to fit the teachings of multiple patents together like pieces of a puzzle."). Rambus also asserts that because the Board found a "RAM memory device necessarily must distinguish between a read and a write," its finding that iAPX could be modified to a simpler system without unneeded functions would not be feasible. Br. at 57. Rambus misinterprets the Board's finding. The Board's finding did not preclude both "read" and "write" functions under a modified system. Rather, the Board understood that claim 1 only requires that "writing" of data to memory must be synchronized with both the rising and falling edges of an external clock, whereas claim 1 permits "reading" of data in other ways
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3.
The Board Properly Determined Rambus's Secondary Evidence Was Insufficient to Overcome the Strong Case of Obviousness
Finally, Rambus argues that the Board failed to give proper consideration to its secondary evidence. See Br. at 61 ("The Board erred in failing to credit Rambus's evidence of long-felt need and skepticism in the art."); Br. at 62-63 (arguing the Board did not credit commercial success evidence). Although proffered evidence of secondary considerations "must be considered, they do not control the obviousness conclusion." See Newell Co. v. Kerrney Mfg. Co., 864 F.2d 757, 768 (Fed. Cir. 1988) (citations omitted). While "it is error not to consider" secondary evidence, "there is a more fundamental requirement that must be met before secondary considerations can carry the day"; i.e., the "proponent must establish a nexus between the evidence and the merits ofthe claimed invention." In re Kao, 639 F.3d 1057, 1068 (Fed. Cir. 2011) (citing Wyers v. Master Lock Co., 616 F.3d 1231, 1246 (Fed. Cir. 2010. Thus, "[w]here the offered secondary considerations actually results from something other than what is both claimed and novel in the claim, there is no nexus to the merits ofthe claimed invention." Kao, 639 F.3d at 1068; see also Taokai Corp. v. Easton Enterprises, Inc., 632 F.3d 1358, 1369 (Fed. Cir. 2011) (if "commercial success is due to an element in the prior art, no nexus exists"). In addition, secondary
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evidence must also be "reasonably commensurate with the scope ofthe claims." In re Kao, 639 F.3d at 1068 (party seeking to establish that evidence of secondary considerations relating to one embodiment covered by the claim is commensurate with the scope of the claim must "provide[] an adequate basis to support the conclusion that other embodiments falling within the claim will behave in the same manner"). Here, Rambus does not meet either requirement - it has not shown that its secondary evidence is sufficiently linked to subject matter falling within claim 1 to establish a nexus, or that the evidence is commensurate with the scope of claim 1.
A. Rambus's Long-Felt Need Evidence Lacks Nexus and Is Not Commensurate in Scope with Claim 1
Rambus asserts that it "showed long-felt need in the art" and showed "early skepticism of the invention ... particularly skepticism of the speeds they could produce by combining a synchronous memory device with a dual edgedJdoubledata-rate feature." Br. at 60 (emphasis added). Rambus relies heavily on its expert's declaration and several articles from 1992, which "touted the dualedge/double-data-rate feature as a big factor in increasing the speed of Rambus's synchronous devices." Br. at 40-41 (citing, e.g., A2615 (1992 article addressing increases in speed, i.e., "offering a tenfold speed boost to memory chips"); A261 7
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(1992 article addressing specific speed increases of "five to 10 times"); A2623 (1992 article addressing "a ten fold increase" in speed); Al770 ~ 30 (expert declaring that in mid 1990s there was skepticism about Dr. Farmwald's and Horowitz's solution to increase speed to certain levels)); see also A2621 (1992 article touting an "increase by more than 10 times"). As the Board noted, claim 1 does not "recite a specific clock speed" or a specified speed increase. A30. Rather, claim 1 simply requires a "method of controlling a synchronous memory device" that includes "issuing a write request to the memory device" and providing data to the memory device synchronously with respect to a rising and falling edge transition of an external clock signal. See A69-70, col. 24, line 60-col. 25, line 6. While using both the rising and falling edges of an external clock to synchronize the writing of data to a memory can increase speed of a particular memory configuration, there are no limitations within claim 1 that require a particular speed or degree of speed increase, e.g., a five or ten fold increase. That is, claim 1 is broad enough to encompass a wide span of memory devices that have faster and relatively slower speeds. For example, Inagaki shows that it was known that the speed could be increased (at least doubled) by using dual edges of an external clock to time the writing of data to memory. 50
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Without a claimed distinction showing specific speed increases, Rambus's evidence oflong-felt need (i.e., skepticism and accolades regarding specific speed increases of five to ten times) is not probative of the non-obviousness of a claim with the breadth of claim 1. To be relevant, Rambus's evidence oflong felt need must be linked to a particular claimed feature and also must exclude the alleged slower performing devices in prior art (e.g., the combination of iAPX and Inagaki); i.e., Rambus must show a nexus. Kao, 639 F.3d at 1068 ("Where the offered secondary consideration actually results from something other than what is both claimed and novel in the claim, there is no nexus to the merits of the claimed invention."). In addition, Rambus has not shown that its touted five to tenfold speed increases were not due to other features not found in claim 1. For example, the touted speed increases may have been due to features found in different patents in the same family or other claims with different features than those found in claim 1. Rambus has simply not satisfied the nexus requirement. Further, Rambus's secondary evidence must be commensurate with the scope of claim 1. Not only must Rambus show its evidence comes within the scope of the claim, Rambus must "provide[] an adequate basis to support the conclusion that other embodiments falling within the claim will behave in the same manner." See Kao, 639 F.3d at 1068. But claim 1 's breadth encompass both 51
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faster and slower devices already in the prior art, like the combined device resulting from iAPX and Inagaki which would have at least doubled its speed as taught by Inagaki. That is, claim 1 simply requires the writing of data to a memory synchronized by an external clock signal, but it does not require a specific speed or specific speed increases - surely there is no requirement for a five to tenfold increase. Thus, Rambus cannot show that the slower prior art devices and the faster devices which both fall within claim 1 behave in the same manner - by definition they behave differently. Accordingly, the Board had good reason to find that Rambus's "evidence fails to establish an inventive solution to a long-felt problem at the time of the effective filing date listed on the face of the '097 patent." A30. Because Rambus cannot show nexus or that its evidence is commensurate with the scope of claim 1, its long-felt need evidence does not establish the non-obviousness of claim 1.
B. Rambus's Commercial Success Evidences Lacks Nexus and Is Not Commensurate in Scope with Claim 1
Rambus also alleges that "the Board erred in failing to credit Rambus's commercial success because it was in the form of licenses rather than sales of a product." Br. at 62-63; see also Br. at 43-44. Contrary to Rambus's assertions, the Board considered its licensing
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evidence, but simply found it unpersuasive. Rambus failed to show that its licensing programs succeeded for reasons linked to the claimed invention. As the Board pointed out, Rambus did not point to "evidence of any sales" and "it is well established that competitors have many reasons for taking licenses which are not necessarily related to unobviousness (i.e., litigation costs, etc.)." A31. Further, it is well settled that "the mere existence of ... licenses is insufficient to overcome the conclusion of obviousness." Sibia Neurosciences, Inc., v. Cadus Pharma. Corp., 225 F.3d 1349, 1358 (Fed. Cir. 2000. Rambus also did not explain whether the licenses, or the reasons the licensees entered into the licenses, were tied to any particular feature in claim 1 or whether some other reasons drove its licensing campaign. A31. Notably, there are numerous patents in the '898 family which include many claims of varying scope and features different from those in claim 1 in this case. In fact, as the Board highlighted, Rambus's expert testified about "complexity" being "added to DRAMs" and that "memory controllers available today ... employ features that are claimed in the 097 patent." A31-32 (citing Murphy Dec!. at Al770, ~ 30 ("others have attempted to create faster controllers and memory devices without using the synchronous interface". But Rambus does not identify whether the alleged "features that are claimed in the '097 patent" or "add[ ed] complexity to 53
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DRAMs" are features recited in claim I. In fact, as the Board explained, claim I does even "require DRAMs." A31-32. Further, as the Board noted, Rambus's arguments and evidence suggest that many features not found in claim I may have contributed to the commercial success, such as delay-locked loop, multiplexed buses, packetized control or other features claimed in other patents in the '898 family. A32 (citing AI645 (expert stated "it was felt that ... one could not put a phase locked loop or delay locked loop in the DRAM itself," which according to Rambus were expressions of disbelief supporting non-obviousness)). Thus, Rambus did not point to any evidence showing that its licensing success was the result of the merits of claim I as opposed to other factors. Nor do we know whether there are other license terms that could have been a motivating factor in their existence. It is well-settled that when considering commercial success evidence, the key is "whether the commercial success" evidence presented "resulted from the merits of the claimed invention as opposed to the prior art or other extrinsic factors." In re Kao, 639 F.3d 1057, 1069 (Fed. Cir. 2011). Notably, it is Rambus's burden to come forth with that evidence - it is not the Board's burden to disprove it.
See,~,
In re Huang, 100 F.3d 135, 140 (Fed.
Cir. 1996) ("[T]he PTO must rely upon the applicant to provide hard evidence of commercial success" including proofthat the evidence was a "direct result ofthe 54
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unique characteristics of the claimed invention - as opposed to other economic and commercial factors unrelated to the quality of the patented subject matter."). Without such evidence a nexus has not been shown. Iron Grip Barbell Co., Inc. v. USA Sports, Inc., 392 F.3d 1317, 1324 (Fed. Cir. 2004) ("Without a showing of nexus, 'the mere existence of ... licenses is insufficient to overcome the conclusion of obviousness' when there is a strong prima facie case of obviousness."). See also In re Paulsen, 30 F.3d 1475, 1482 (Fed. Cir. 1994). Even considering any value in Rambus's secondary consideration evidence, it does not outweigh the strong prima facie case of obviousness over iAPX in view of Inagaki. See In re Inland Steel Co., 265 F.3d 1354, 1366 (Fed. Cir. 2001) (broad deference is given to the Board in weighing secondary consideration evidence.); see also Para-Ordnance Mfg. v. SGS Importers Int'!, Inc., 73 F.3d 1085, 1091 (Fed. Cir. 1995). Given the strength ofthe prima facie case, the evidence of secondary considerations is inadequate to outweigh the Board's conclusion that claim 1 of the '097 patent would have been obvious.
55
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CONCLUSION
Because Rambus has failed to show the Board committed any reversible error in determining that representative claim 1 would have been anticipated or obvious in view ofthe prior art, and the Board's underlying findings are supported by substantial evidence, the Board's decision should be affirmed.
Respectfully submitted, /s/ WILLIAM LaMARCA Nathan K. Kelley Deputy Solicitor William LaMarca Coke Morgan Stewart Associate Solicitors
Office of the Solicitor - Mail Stop 8 U.S. Patent and Trademark Office P.O. Box 1450 Alexandria, VA 22313-1450 571-272-9035 Attorneys for the Director of the United States Patent and Trademark Office
March 6, 2013
56
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CERTIFICATE OF COMPLIANCE
I certifY that the foregoing BRIEF FOR APPELLEE DIRECTOR OF THE UNITED STATES PATENT AND TRADEMARK OFFICE complies with Fed.
R. App. P. 32 (a)(7)(B) ar:tdFederal Circuit Rule 32 (b) and contains 13,291

words.
/s/ WILLIAM LaMARCA William LaMarca Associate Solicitor
57
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CERTIFICATE OF SERVICE
I certifY that on March 6, 2013, I electronically filed the foregoing BRIEF FOR APPELLEE - DIRECTOR OF THE UNITED STATES PATENT AND TRADEMARK OFFICE with the Court's CMlECF filing system, which constitutes service, pursuant to Fed. R. App. P. 25(c)(2), and the Court's Adminstrative Order Regarding Electronic Case Filing 6(A) (May 17, 2012), to all registered CMlECF users.
Counsel fOr Rambus (Appellant-Patent Owner) (CMlECF) l. Michael lakes lames R. Barney Molley R. Silfen Finnegan, Henderson, Farabow, Garrett & Dunner, LLP 901 New York Avenue, NW Washington, DC 20001 (202) 408-4000
Counsel fOr NVIDIA (Requester) (Courtesv Copy bv US Mail! David L. McCombs Hayne & Boone, LLP 2323 Victory Avenue Dallas, TX 75219
/s/ WILLIAM LaMARCA William LaMarca Associate Solicitor

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Case: 12-1634

Appeal No. 2012-1634 (Reexamination No. 95/001,134)

UNITED STATES COURT OF APPEALS FOR THE FEDERAL CIRCUIT

RAMBUS, INC., Appellant,

See A69-70, col. 24, line 60-col. 25, line 6.

STATEMENT OF THE ISSUE .................................

The Board Decision and the Examiner's Answer ............. 11

Secondary Considerations .......................... 18

SUMMARY OF THE ARGUMENT ............................ 19 ARGUMENT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 24 A. Standard of Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 24

STATEMENT OF RELATED CASES

u.s. Patent No. 6,260,097

Appeal No. 2012-1634 (Reexamination No. 95/001,134)

UNITED STATES COURT OF APPEALS FOR THE FEDERAL CIRCUIT

STATEMENT OF THE ISSUE

STATEMENT OF THE CASE

See Al026 (original claims 6, 9,13,15-25,27 and 33 were "confirmed"). 3

STATEMENT OF THE FACTS A. Dynamic Random Access Memory (DRAM) Technology

One type of memory

the memory cells is lost over time. A1766 (Murphy Decl.

,m 15-16).5 The phrase

The '097 Farmwald patent discloses a method of controlling a memory

The Prior Art

Inagaki8 (Japanese patent publication)

Inagaki, JP 57-210495 (Dec. 24,1982). A2944-2952; A2953-2967.

3 ("I/O shift register drive clocks <pI and

universal motivators" supporting its obviousness conclusion. A24.

SUMMARY OF THE ARGUMENT

In contrast to Rambus's argued construction, claim 1 simply recites "issuing

2) and the Examiner found that "the specification only states

Berg, 320 F.3d at 1315.

KSR, 550 U.S. at 420

In re Huang, 100 F.3d 135, 140 (Fed.

R. App. P. 32 (a)(7)(B) ar:tdFederal Circuit Rule 32 (b) and contains 13,291

/s/ WILLIAM LaMARCA William LaMarca Associate Solicitor

/s/ WILLIAM LaMARCA William LaMarca Associate Solicitor

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