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Analysis and Comparison of Turn-off Active Gate Control Methods for Low-Voltage Power MOSFETs With High Current Ratings
Bjoern Wittig, Student Member, IEEE, and Friedrich Wilhelm Fuchs, Senior Member, IEEE
AbstractAn analysis and improvement of the switching behavior of low-voltage power MOSFETs with high current ratings is presented. At turn-off, a high overvoltage arises for power MOSFETs. An improvement can be achieved by means of lowering the current slope via the driving stage during switching. Likewise, the current slope can exceed the required limits despite high gate resistances. These problems are of major concern for low-voltage power MOSFETs and can be solved via the driving stage. Thus, turn-off active gate control methods are analyzed and their performance is investigated focusing on reducing the overvoltage at turn-off under the precondition of only a minor increase of switching losses. With only a small number of additional components, a remarkable reduction of turn-off losses is achieved. Thus, these methods are well suited to industrial applications. The control concepts are experimentally compared to a basic gate drive circuit. Index TermsDriver circuits, losses, overvoltage protection, power MOSFETs, switching transients.

I. INTRODUCTION N BATTERY-FED drives, such as in lift trucks and electrical passenger cars, power MOSFETs with high current ratings play a signicant role. Typical applications are dc/ac converters for feeding a three-phase ac motor or dc/dc converters, e.g., for battery backup systems [1][5]. Due to the high power and low voltages of, e.g., 24 V in some applications, high currents result. Thus, there is a high market demand for low-voltage power MOSFETs with a low drainsource on-state resistance RDS(on) and a low temperature dependence in order to achieve lower conduction losses. Due to the trend of reducing the drainsource on-state resistance RDS(on) of modern automotive power MOSFETs and subsequently decreasing conduction losses, the switching losses get a higher inuence on the total power losses of the semiconductors. With increasing switching frequencies, this effect becomes more signicant and can play an important role in

Manuscript received January 6, 2011; revised May 16, 2011; accepted July 5, 2011. Date of current version February 7, 2012. This work was supported in part by Fraunhofer-Gesellschaft and by the State of Schleswig-Holstein. This work was partly presented at the IEEE International Symposium on Industrial Electronics, 2010. Recommended for publication by Associate Editor S. K. Mazumder. The authors are with the Institute of Power Electronics and Electrical Drives, Christian-Albrechts-University of Kiel, Kiel 24143, Germany (e-mail: bw@tf.uni-kiel.de; fwf@tf.uni-kiel.de). Color versions of one or more of the gures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identier 10.1109/TPEL.2011.2162531

the development of converters with power MOSFETs. Gate drive circuit design has an important inuence on switching losses because in some cases the control of the negative current slope during turn-off can only be achieved satisfactorily with the use of an additional snubber, clamping networks, with soft switching converter topologies, or with a very high external gate resistance, resulting in higher power losses and/or longer turn-off and turn-on delay times. Besides, the use of lossless snubber networks or soft-switching topologies in high current applications leads to high stress on additional inductors, capacitors, and diodes/semiconductors, which often have to carry the whole load current for a short time [6][10]. Therefore, active gate control of low-voltage power MOSFETs could be a way to reduce the switching losses and/or the overvoltages with negligible additional power losses of the control circuitry and additional components. In the literature, many low cost and easy to implement active gate control methods have been presented for applications with insulated gate bipolar transistors (IGBTs) under hard switching conditions. Only a few publications, focus on use for power MOSFETs [11][14]. In [11], a small inductance in the source path is used to measure the current slope in the power MOSFET for decreasing or increasing the switching speed. In addition, a concept is presented for measuring the drainsource voltage slope of the MOSFET to inuence the switching behavior, already known as du/dt-control for IGBTs as in [15] and [16]. Another method is the use of a small transformer to control a signal MOSFET at the gate drive circuit and to inject an additional current during turn-on, which leads to a decreasing turn-on switching energy [12]. In [14] an adjustment of the turn-on and turn-off gradients of the drain current and drain-to-source voltage via an optically activated gate control for power semiconductors is shown. Here, the variable gate resistance is controlled by the amplitude of the pulse signal thereby modulating the charging and discharging of the input capacitance of the device. In [13], an electromagnetic interference suppression driver is presented that slows down the gatesource voltage transition near the gatesource threshold voltage, reducing the drainsource voltage slope. Similar considerations have been made for IGBTs in [17] and [18], where the turn-on behavior is inuenced by a gate voltage shape generator. An obvious way to increase or to decrease the voltage and current slopes applied for an IGBT is to switch on or off an additional gate resistor and current path to the available gate resistor as described in [19][22]. In [23][25], a modied gate

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Fig. 1. Typical test circuit for the hard switching process of power MOSFETs with an inductive load and a conventional gate drive circuit.

voltage characteristic is used where the transistor is turned on again for a very short time after the end of the switching process to decrease the current slope and the overvoltage caused by the parasitic inductances in the commutation path. Furthermore, a common method is the use of a current sink and/or current source to inuence and to improve the switching characteristic of IGBTs [26][32]. Similar investigations are done here for low-voltage power MOSFETs with high current ratings. This paper is structured as follows: in Section I, a short explanation and analysis of the theoretical switching behavior is given. Next, in Section II, the effect of the stray inductance of the commutation path and the common source inductance on the drainsource voltage characteristic is explained. In Section III, different turn-off active gate control methods are presented and analyzed. These methods are divided into four typesthe du/dtcontrol, the di/dt-control, the two-stage control, and the current injection gate drive circuitand the functionality of each is explained. Experimental results are presented and a performance comparison of the different proposed active gate control methods is worked out in Section IV. Section V concludes the paper. II. SWITCHING BEHAVIOR OF LOW-VOLTAGE POWER MOSFETS A typical test circuit for the hard switching process of power MOSFETs with an inductive load and with a conventional gate drive circuit is illustrated in Fig. 1. Here, the MOSFET M1 is the device under test and M2 is used as a freewheeling diode as in a typical half-bridge conguration. LDC 1 and LDC 2 represent the stray inductances of the dc tracks and LD 1 , LD 2 , LS 1 , and LS 2 indicate the inductances between the respective chip and the dc track, respectively, the center tap of the half-bridge. The total stray inductance L of the commutation path is dened as in (1) L = LD 1 + LS 1 + LDC 1 + LDC 2 + LD 2 + LS 2 . (1)

Fig. 2. Theoretical current and voltage characteristic at turn-on and turn-off of a power MOSFET, without (continuous line) and with (dotted line) consideration of the stray inductance L in the commutation path.

The theoretical current and voltage characteristic at turn-on and turn-off of a power MOSFET are displayed in Fig. 2 [2], [33]. The widely used denitions of the current and voltage rise and fall times and the turn-on and turn-off delay times for power MOSFETs are depicted as well. In Fig. 2, the dotted lines show the theoretical characteristic considering the stray inductance L . The drain current overshoot, which results from the reverse recovery current IRRM of the body diode of M2 , is indicated also. At turn-on, during the current rise time, the induced positive voltages at the stray inductances in the commutation path lead to a lower voltage stress of the power MOSFET M1 [5], [33]. In this phase, the voltage decrease is diD . (2) dt During the turn-off process and the current fall time, the induced voltages at the stray inductances are negative. Considering the turn-on overvoltage VFRM of the inverse body diode of M2 , leads to the following overvoltage peak at turn-off [33] Vind = L diD + VFRM . (3) dt At lower current slopes, the turn-on overvoltage VFRM of the body diode can be neglected but at higher values, VFRM increases and can lead to an additional overvoltage of a few volts for a short time. The induced voltage can be in the range of the supply voltage and is of special importance for low-voltage power MOSFETs Vpk = L

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Fig. 3. Experimental turn-on and turn-off process of the power MOSFET NP110N055PUG from NEC [35]: V G S 5 V/div (blue line), V D S 10 V/div (green line), ID 50 A/div (red line), t 200 ns/div; V D D = 24 V , R G = 3 .9 , T J = 20 C.

Fig. 4. du/dt-control methods. (a) du/dt-control by means of an external gate drain capacitance. (b) du/dt-control by means of an external gate drain capacitance and a zener diode in series.

with high current ratings. As described in [31] and [34], the current rise and fall times are strongly inuenced by the stray inductances in the commutation path of the current. Taking into account the transconductance gfs , the input capacitance of the power MOSFET Ciss , and the gate threshold voltage VGS , th , the relationship of the current slope during switching and the common source inductance LS 1 , which is the stray inductance between the source of M1 and the source tap of the driving stage (depicted in Fig. 1), can be approximated as in (4) [31], [32], [34]. In fact, this is just an approximation that neglects the total stray inductance L of the switching loop
D Vgg VGS , th 2Ig diD fs . dt (RG Ciss g1 ) + L S 1 fs

Fig. 5. di/dt-control methods. (a) di/dt-control by means of a zener diode. (b) di/dt-control by means of a signal MOSFET in the current feedback path.

(4) measurements of a low-voltage power MOSFET (VDSS = 55 V, ID , cont . = 110 A). The reduced voltage stress at turn-on and the overvoltage at turn-off are obvious.

For gate drive circuit design and MOSFET selection, the converter designer has to nd an optimum of a preferably high current slope diD /dt to reduce the switching losses and the maximum allowable resulting overvoltage Vpk at turn-off. Therefore, for correct gate drive circuit design, the breakdown voltage VDSS , the voltage reserve which has to be maintained, and the maximum dc-link voltage VDD have to be taken into account. Using these, a maximum absolute value of allowable current slope |diD /dt|m ax can be determined. In some applications this could mean that an unfavorable high gate resistance must be chosen or additional snubber or clamping networks have to be implemented in order to not to exceed this limit of current slope and to guarantee a normal failure free operation [36]. In Fig. 2, the principal characteristic of the switching losses is also illustrated. There the conduction losses and the normally negligible blocking losses are indicated as Econd and Eblo ck , respectively. Considering the parasitic stray inductances in the commutation path and the described voltage characteristic as mentioned earlier, these induced voltages are responsible for a low turn-on energy Es (on) . In contrast to that, the turn-off energy Es (o ) is several times higher than the turn-on energy due to the high overvoltage Vpk . Because of the usually low resulting turn-on energy and the relatively low amplitude of drain current overshoot, turn-on active gate control methods are not very effective and not mandatory. Therefore, the following analysis of active gate drive concepts deals only with the inuence and improvement of the turn-off switching characteristic of lowvoltage high power MOSFETs. Fig. 3 shows turn-on and turn-off

III. ACTIVE GATE TURN-OFF CONTROL CIRCUITS A. du/dt-Control A widely used method of inuencing the switching behavior is the du/dt-control, for which the circuit can be seen in Fig. 4(a) [16], [19]. There the voltage slope is fed back, i.e., by a small capacitance between the gate and the drain of the power MOSFET. The current through the external gate-drain capacitance CGD , which is proportional to the voltage slope dvDS /dt of the transistor, is directly coupled into the gate of the power MOSFET. This leads to increases in the voltage rise time and the current fall time. An expansion of this switching control method is shown in Fig. 4(b), where an additional zener diode Dz is used in series to the external capacitance CGD , well known as an active clamping concept. This induces a conventional voltage rise at the beginning of the turn-off process at low drainsource voltages due to the blocking zener diode. At higher drainsource voltages above the breakdown voltage of the zener diode, the latter one is conducting and the now available current path through CGD , RGD , and Dz leads to a slower voltage rise at higher drain source voltage. Additionally, the current slope is reduced. Thus, it is possible to react only to excessive overvoltages.

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Fig. 6.

Two-stage control gate drive circuit.

Fig. 7. off.

Proposed gate drive circuit with current injection into the gate at turn-

B. di/dt-Control Another way to inuence the switching speed is to measure the current slope diD /dt with a feedback circuit at the gate, which is called di/dt-control. This can be done by an additional inductance at the source pin of the power MOSFET or by using the parasitic source inductance LS 3 of the copper wire or track. If an excessively current falling slope is detected by means of the induced voltage at the inductance, a positive current is fed back via RS and D1 into the gate of the power MOSFET during the current fall time, which is controlled toward on state, and the steepness of the slope is reduced. In Fig. 5, two ways of realizing the control method are displayed [19]. The rst method in Fig. 5(a) does not lead to satisfactory results because of the slow response time and the relatively high on-state resistance of the zener diode. Using a signal transistor TS instead of a zener diode as shown in Fig. 5(b) leads to better results. Thus, it is possible to control the current slope without inuencing the voltage slope at turn-off. C. Two-Stage Control A more complex active gate control method is the two-stage control, where a low ohmic current path for switch off is in parallel to the conventional gate resistor during the voltage rise time. Fig. 6 shows the principal circuit of the two-stage control circuit. The low ohmic current path is realized by the transistor T2 , the low ohmic resistance RGo , 2 , and the diode DGo , 2 . Initially, the power MOSFET is conducting and the gate signal Vgg is at the high level (e.g., + 15 V). This means that at the beginning of the turn-off process, T2 is turned on via the gate signal Vgg . Additionally, a small current is injected through R1 and D1 into the power stage and leads to a voltage drop across R2 and R3 . This voltage drop is nearly the drainsource voltage of the power MOSFET plus the forward voltage of the diode D1 . At a dened measured drainsource voltage, the transistor T1 is turned on, and hence, T2 is turned off. During the current fall time, the low ohmic current path is switched off in this way. Although this leads to nearly the same current fall time and, therefore, nearly the same induced voltage peak Vpk compared to the conventional gate drive circuit, the voltage rise time can be reduced. Furthermore, the turn-off delay time td (o ) is kept

TABLE I DATASHEET PARAMETERS OF THE USED POWER MOSFET IN THE LABORATORY SETUP

low and nearly constant for increasing main gate resistance RG . This method has also been presented in the literature with IGBTs instead of low-voltage power MOSFETs [37]. D. Current Injection Gate Drive Circuit Fig. 7 shows the proposed gate drive circuit for a low-voltage power MOSFET with an adjustable current source. During turn-off, the drainsource voltage VDS of the power device is measured by the resistor R1 and the diode D1 and scaled down by the resistors R2 and R3 . This method is very common in desaturation detection circuits or in other active gate control methods [37][39]. If the applied voltage at R3 exceeds the threshold voltage of the n-channel MOSFET T1 , T1 and, consequently, the p-channel MOSFET T2 , are turned on. By applying the turn-off control voltage Vd , a small positive current IS is injected through R5 and D2 into the gate of the power MOSFET and slows down the current slope during turnoff. With this method it is possible to adjust the switching speed by means of the resistor R5 as well as by the amplitude of the turn-off control voltage Vd . This means setting down the control voltage Vd to zero, the current injection path has no inuence on the switching process, which could be desirable at low blocking voltages of the power MOSFET. At high dc-link- and blocking voltages, which can be measured very easily, the current injection path can be activated by applying an adjustable control voltage Vd , which, depending on its amplitude, slows down the current slope at turn-off. See [40] for additional information regarding adaptive active gate control or operation point dependent switching control.

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Fig. 8. Experimental turn-on and turn-off characteristics of the NP110N055PUG from NEC in the case of the du/dt-control and di/dt-control method in comparison with the conventional gate drive @ IL = 150 A , V D D = 24 V , T J = 20 C . (a) du/dt-control, R G = 10 , C G D e x = 2 .2 nF , R G D e x = 300 . (b) di/dt-control, R G = 10 , R s = 0 .3 .

When designing this current injection gate drive circuit, the dynamic and the steady-state behavior of the signal transistors T1 and T2 and the diodes D2 and D1 should be taken into account. For correct operation, all of these semiconductor devices should have very small switching and turn-on delay times. Additionally, the drainsource on state resistance RDS(on) of the transistor T2 and the differential bulk resistance of the diode D2 should be low ohmic for proper operation. IV. EXPERIMENTAL RESULTS For experimental analysis, the low-voltage power MOSFET NP110N055PUG from NEC is used, which is described briey in Table I [35]. The device has vertical trench structure, which is the most commonly used structure for low-voltage high-current applications. For implementation of the active gate control methods, critical MOSFET parameters are the input capacitance Ciss and the transconductance gfs . Besides a low drainsource onstate resistance RDS(on) , the NP110N055PUG offers a high input capacitance Ciss of typically 17100 pF and a low transconductance gfs of 83 S. Basic analysis by the authors employing power MOSFET IRFS3306PbF from International Rectier, which has a very low typical Ciss of just 4520 pF and a high minimum gfs of 230 S, have been presented in [41]. They show that with decreasing Ciss and/or rising gfs , the requirement of short response times of the active gate control circuits increases. Additionally, a few circuit parameters of the control methods have to be changed, e.g., the external capacitance CGD of the du/dt-control and the voltage dividers R2 and R3 of the two-stage control and current injection gate drive. Nevertheless, an improvement can still be achieved when using these devices. The stray inductance L of the whole current commutation path in this laboratory setup is determined to be about 36 nH

by double-pulse measurement [42]. The dc-link voltage VDD is chosen to be 24 V. All control methods have been tested at the same working point of IL = 150 A. Additional analyses at junction temperatures of TJ = 100 C have been made, which did not show any essential temperature dependence of the switching process with and without the proposed control methods and will therefore not be presented here. The experimental turn-on and turn-off characteristics of the power MOSFET used here in the case of the du/dt-control [see Fig. 4(a)] and the di/dt-control [see Fig. 5(b)] are shown in Fig. 8. For comparison the characteristic in the case of a conventional gate drive circuit is also illustrated. Due to the stray inductance L of the commutation path, the drainsource voltage is very low during the current rise time. The consequences are very low turn-on losses. During turn-off, both methods generate longer current fall times and, therefore, a reduction of the overvoltage. Naturally, both concepts lead to higher switching losses but without a mentionable increase of the voltage rise time and turn-off delay time. Therefore, they offer an advantage compared to an increase of the external conventional gate resistance. The turn-on and turn-off processes in the case of the two-stage control and the current injection gate drive circuit are depicted in Fig. 9. It is clearly seen that the two-stage control method leads to a faster voltage rise time and, therefore, to considerably lower turn-off losses. The current fall time is not inuenced by this method. In contrast to the two-stage control, the current injection gate drive circuit has no inuence on the voltage rise time. Only the current slope during turn-off is decreased with increasing control voltage Vd . For comparison, the results of the proposed active gate drive circuits are illustrated in Fig. 10. In addition to the described active gate control methods, a combination of the two-stage

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Fig. 9. Experimental turn-on and turn-off characteristics of NP110N055PUG from NEC in the case of the two-stage control and the current injection method in comparison with the conventional gate drive @ IL = 150 A , V D D = 24 V , T J = 20 C . (a) Two-stage control, R G = 10 .0 , and R G o , 2 = 0 .47 . (b) Current injection with varying control voltage V d , R G = 3 .9 , and R 5 = 3 .9 .

Fig. 10. Experimental results of the presented active gate control methods with the NP110N055PUG from NEC @ V D D = 24 V , IL = 150 A , and T J = 20 C ; recall the shifted zero (for clarity and for better showing the differences).

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Fig. 11. Experimental turn-off overvoltage V p k in dependence on the turnoff energy E s (o ) with the NP110N055PUG from NEC @ V D D = 24 V , IL = 150 A , and T J = 20 C .

Fig. 12. Turn-off energies E s (o ) of the proposed active gate drive methods related to conventional gate drive at a voltage peak of V p k = 20 V @ V D D = 24 V , IL = 150 A , and T J = 20 C .

control and the current injection gate drive is also proposed. This has the advantage that both voltage rise time and current fall time can be inuenced separately and lead to a totally controllable turn-off process. In Fig. 10(a), the dependence of the induced overvoltage Vpk on the gate resistance RG is illustrated. The two-stage control offers the same induced overvoltage as the conventional gate drive due to having the same gate resistance value during the current fall time tri . This can also be seen in Fig. 10(b) where the same current fall time is shown. Considering the di/dt-control, the overvoltage Vpk decreases with increasing gate resistance. This occurs because of the decreasing current slope and, therefore, decreasing induced voltage at LS 3 . The effectiveness of the feedback path is, therefore, only satisfactory at high current slopes. The du/dt-control, the current injection gate drive circuit, and the combination of the latter one with the two-stage control lead to a reduction of the overvoltage due to the decreased current slope. As mentioned previously, the two-stage control delivers the lowest voltage rise time tru , which is shown in Fig. 10(c). The following result is illustrated in Fig. 10(d) where the turn-off energy Es (o ) is depicted as a function of the gate resistance. Here, the two-stage control and the combination of the latter one and the current injection offer the lowest turn-off energies with increasing gate resistance. To evaluate these results and to make conclusions about the effectiveness and improvement of the proposed methods compared to the conventional gate drive circuit, the dependence of the overvoltage Vpk at turn-off in dependence on the turn-off energy Es (o ) is illustrated in Fig. 11. It is shown that all methods lead to lower turn-off energies at the same induced overvoltage when compared to the conventional gate drive. Especially the two-stage control, the current injection, and the combination of both deliver good results. Naturally, compared to du/dt-control and di/dt-control, these methods require a higher effort on electrical components. For example, the turn-off energy Es (o ) of the proposed turnoff active gate control methods related to conventional gate drive at an induced overvoltage of Vpk = 20 V is illustrated in Fig. 12. A reduction of about 2030% of the turn-off energy compared

Fig. 13. Experimental turn-off delay time td (o ) in dependence on the gate resistance R G with the NP110N055PUG from NEC @ V D D = 24 V , IL = 150 A , and T J = 20 C .

to the use of a conventional gate drive can be achieved for this working point. Another effect of the two-stage control is the short turn-off delay time td (o ) , which is nearly constant with increasing gate resistance and much lower than the other active gate drive methods (see Fig. 13). This can lead indirectly to lower power losses due to the possibility of reducing the mandatory deadtimes. V. CONCLUSION Different turn-off active gate control methods for low-voltage power MOSFETs with high current ratings have been presented and analyzed. First, the theoretical switching behavior of a power MOSFET has been explained. Different gate control concepts, the du/dt-control, di/dt-control, two-stage control, and the current injection have been presented. The proposed gate drive circuits have been implemented and measured in the laboratory. The two-stage control, the current injection method, and the combination of the two, deliver the best results of the analyzed active gate drive circuits considering the turn-off losses and their dependence on the turn-off overvoltage. Also, turn-off

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delay time can be reduced by the two-stage control in comparison to a conventional gate drive circuit. With only minor additional components needed, a remarkable reduction of power losses is achieved. Thus, these concepts can be judged well suited for industrial applications.

ACKNOWLEDGMENT This work was carried out in a combined project of the Centre of Competence for Power Electronics Schleswig-Holstein (KLSH). REFERENCES
[1] A. Emadi, Handbook of Automotive Power Electronics and Motor Drives. Boca Raton, FL: CRC Press, 2005. [2] B. Baliga, Fundamentals of Power Semiconductor Devices. New York: Springer-Verlag, 2008. [3] A. Lindemann and S. Foerster, Design aspects for power MOSFET components in automotive electronics, in Proc. 12th Int. Power Electron. Motion Control Conf., Maribor, Slovenia, 2006, pp. 19881993. [4] G. Belverde, C. Guastella, M. Melito, S. Musumeci, and A. Raciti, A lowvoltage MOSFET with small on-resistance: An extended characterization in high-efciency power converter applications, in Proc. IEEE 36th Ind. Appl. Conf. Rec., Chicago, IL, 2001, pp. 635640. [5] D. Schroeder, Elektrische Antriebe 3Leistungselektronische Bauelemente; Electrical Drives 3Power Electronic Components. Heidelberg, Germany: Springer-Verlag, 2006. [6] P. Todd. (1993). Snubber circuits: Theory, design and application, Application Note, International Rectier [Online]. Available: http://www.irf.com [7] C. Gallo, F. Tofoli, and J. Pinto, A passive lossless snubber applied to the ac-dc interleaved boost converter, IEEE Trans. Power Electron., vol. 25, no. 3, pp. 775785, Mar. 2010. [8] M. Jinno, P. Chen, and K. Lin, An efcient active LC snubber for forward converters, IEEE Trans. Power Electron., vol. 24, no. 6, pp. 15221531, Jun. 2009. [9] P. Das, B. Laan, S. Mousavi, and G. Moschopoulos, A nonisolated bidirectional ZVS-PWM active clamped dcdc converter, IEEE Trans. Power Electron., vol. 24, no. 2, pp. 553558, Feb. 2009. [10] E. Adib and H. Farzanehfard, Family of soft-switching PWM converters with current sharing in switches, IEEE Trans. Power Electron., vol. 24, no. 4, pp. 979985, Apr. 2009. [11] J. Berry, MOSFET operating under hard switching mode: Voltage and current gradients control, in Proc. 4th Eur. Conf. Power Electron. Appl., Symp. Mater. Devices Power Electron., Florence, Italy, 1991, pp. 131134. [12] T. Shimizu and K. Wada, A gate drive circuit of power MOSFETs and IGBTs for low switching losses, in Proc. 7th Int. Conf. Power Electron., Daegu, Korea, 2007, pp. 857860. [13] H. Yee, An EMI suppression MOSFET driver, in Proc. IEEE 12th Annu. Appl. Power. Electron. Conf. Expo., Vancouver, BC, 1997, pp. 242248. [14] S. Mazumder and T. Sarkar, Optically-activated gate control for power electronics, IEEE Trans. Power Electron., vol. 26, no. 10, Oct. 2011. [15] H. Lee, Y. Lee, B. Suh, and D. Hyun, An improved control scheme for snubberless operation of high power IGBTs, in Proc. IEEE 32nd Ind. Appl. Soc. Annu. Meet. Conf. Rec., New Orleans, USA, 1997, 975982. [16] H. Rothwangl and H. Schamboeck, Advanced IGBT control strategies improvement of the switching characteristics via active gate control, presented at the 10th Eur. Conf. Power Electron. Appl., Toulouse, France, 2003. [17] P. Grbovic, An IGBT gate driver for feed-forward control of turn-on losses and reverse recovery current, IEEE Trans. Power Electron., vol. 23, no. 2, pp. 643652, Mar. 2008. [18] P. Grbovic, F. Gruson, N. Idir, and P. Le Moigne, Turn-on performance of reverse blocking IGBT (RB IGBT) and optimization using advanced gate driver, IEEE Trans. Power Electron., vol. 25, no. 4, pp. 970980, Apr. 2010. [19] M. Helsper, Analyse und Verbesserung des Verhaltens von Planarund Trench-IGBT-Modulen in hart bzw. weich schaltenden Applikationen, Ph.D. dissertation, Inst. Power Electron. Electr. Drives, ChristianAlbrechts-University of Kiel, Kiel, Germany, 2003.

[20] M. Kimata, S. Chikai, T. Tanaka, and K. Ishii, High performance gate drive circuit of high voltage IPMs (HVIPMs), in Proc. 29th Annu. IEEE Power Electron. Spec. Conf., Fukuoka, Japan, 1998, pp. 11961200. [21] G. Schmitt, R. Kennel, and J. Holtz, Voltage gradient limitation of IGBTs by optimised gate-current proles, in Proc. IEEE Power Electron. Spec. Conf., Rhodos, Greece, 2008, pp. 35923596. [22] B. Weis and M. Bruckmann, A new gate driver circuit for improved turnoff characteristics of high current IGBT modules, in Proc. IEEE 33rd Ind. Appl. Soc. Annu. Meet., St. Louis, MO, 1998, pp. 10731077. [23] N. Idir, R. Bausi ere, and J. Franchaud, Active gate voltage control of turn-on di/dt and turn-off dv/dt in insulated gate transistors, IEEE Trans. Power Electron., vol. 21, no. 4, pp. 849855, Jul. 2006. [24] H. Sawezyn and R. Bausi` ere, A feedback voltage control of insulated gate power transistors, Control Intell. Syst., vol. 31, no. 3, 2003. Available: http://actapress.com. [25] V. John, B. Suh, and T. Lipo, High-performance active gate drive for high-power IGBTs, IEEE Trans. Ind. Appl., vol. 35, no. 5, pp. 1108 1117, Sep./ Oct. 1999. [26] M. Cacciato, A. Consoli, G. Frascadore, A. Testa, G. Giannini, and R. Nisci, Driving optimization of IGBT devices for traction applications, presented at the 11th Eur. Conf. Power Electron. Appl., Dresden, Germany, 2005. [27] S. Park and T. Jahns, Flexible dv/dt and di/dt control method for insulated gate power switches, IEEE Trans. Ind. Appl., vol. 39, no. 3, pp. 657664, May/Jun. 2003. [28] J. Kagerbauer and T. Jahns, Development of an active dv/dt control algorithm for reducing inverter conducted EMI with minimal impact on switching losses, in Proc. IEEE Power Electron. Spec. Conf., Orlando, FL, 2007, pp. 894900. [29] X. Zhou, Z. Liang, and A. Huang, A high-dynamic range current source gate driver for switching-loss reduction of high-side switch in buck converter, IEEE Trans. Power Electron., vol. 25, no. 6, pp. 14391443, Jun. 2010. [30] M. Rose, J. Krupar, and H. Hauswald, Adaptive dv/dt and di/dt control for isolated gate power devices, in Proc. IEEE Energy Convers. Congr. Expo., Atlanta, GA, 2010, pp. 927934. [31] A. Galluzzo, M. Melito, G. Belverde, S. Musumeci, A. Raciti, and A. Testa, Switching characteristic improvement of modern gate controlled devices, in Proc. 5th Eur. Conf. Power Electron. Appl., Brighton, U.K., 1993, pp. 374379. [32] C. Licitra, S. Musumeci, A. Raciti, A. Galluzzo, R. Letor, and M. Melito, A new driving circuit for IGBT devices, IEEE Trans. Power Electron., vol. 10, no. 3, pp. 373378, May 1995. [33] J. Lutz, Halbleiter-LeistungsbauelementePhysik, Eigenschaften, Zuverlaessigkeit; Semiconductor Power DevicesPhysic, Characteristics, Reliability. Heidelberg, Germany: Springer-Verlag, 2006. [34] S. Musumeci, A. Raciti, A. Testa, A. Galluzzo, and M. Melito, Switchingbehavior improvement of insulated gate-controlled devices, IEEE Trans. Power Electron., vol. 12, no. 4, pp. 645653, Jul. 1997. [35] NEC. (2009). Datasheet NP110N055PUG, Switching N-Channel Power MOSFET. NEC Electronics Corporation [Online]. Available: http://www.necel.com [36] F. Peng, G. Su, and L. Tolbert, A passive soft switching snubber for PWM inverters, IEEE Trans. Power Electron., vol. 19, no. 2, pp. 363370, Mar. 2004. [37] M. Helsper and F. Fuchs, Adaptation of IGBT switching behaviour by means of active gate drive control for low and medium power, presented at the 10th Eur. Conf. Power Electron. Appl., Toulouse, France, 2003. [38] International Rectier. (2009). Current Sensing Single Channel Driver, IR2127, Datasheet. [Online]. Available: http://www.irf.com. [39] B. Wittig, M. Boettcher, and F. Fuchs, Analysis and design aspects of a desaturation detection circuit for low voltage power MOSFETs, in Proc. 14th Int. Power Electron. Motion Control Conf., Ohrid, Macedonia, 2010, pp. T1-7T1-12. [40] B. Wittig and F. Fuchs, Current injection gate drive circuit for controlling the turn-off characteristic of low voltage power MOSFETs with high current ratings, in Proc. IEEE Int. Symp. Ind. Electron., Bari, Italy, 2010, pp. 767772. [41] B. Wittig and F. Fuchs, Analysis and improvement of the switching behaviour of low voltage power MOSFETs with high current ratings under hard switching conditions, in Proc. IEEE Int. Symp. Ind. Electron., Bari, Italy, 2010, pp. 644649. [42] T. Wernicke, S. Dieckerhoff, T. Kirfe, G. Feix, S. Guttowski, and H. Reichl, Experimental characterization methods for power MOSFET assemblies, in Proc. 12th Eur. Conf. Power Electron. Appl., Aalborg, Denmark, 2007, pp. 19.

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Bjoern Wittig (S09) was born in Kiel, Germany, in 1981. He received the Dipl.Ing. degree from the Christian Albrechts-University of Kiel, Kiel, Germany, in 2008. Since 2008, he has been a Research Assistant at the Institute of Power Electronics and Electrical Drives, Christian-Albrechts-University of Kiel. His main research interests include converters for low-voltage applications, i.e., for the automotive section gate drive circuits and the switching behavior of power semiconductors. In this regard, he investigates converter topologies and driver circuits for power semiconductors.

Friedrich Wilhelm Fuchs (M96SM01) received the Dipl.Ing. and Ph.D. degrees in electrical engineering from the Rheinisch-Westf alische Technische Hochschule University of Technology, Aachen, Germany, in 1975 and 1982, respectively. From 1975 to 1982, he was a Scientic Assistant in research for automotive ac drives at the RheinischWestf alische Technische Hochschule University of Technology. From 1982 to 1996, he was involved in research on development of power electronics and electrical drives, rst in a medium-sized company, later as the Managing Director at the Converter and Drives Division, AEG (currently Converteam), Berlin, Germany. Since 1996, he has been a Full Professor and the Head of the Institute of Power Electronics and Electrical Drives, Christian-Albrechts-University of Kiel, Kiel, Germany. Many research projects are carried out with industrial partners. The institute is a member of CEwind eG, a center of excellence for wind energy established as a joint project of universities and research establishments as well as of KLSH, a competence center for power electronics. He is the author or coauthor of more than 150 papers. His main research interests include power semiconductor application, converters topologies, variable speed drives, as well as their control. Other research interests include renewable energy conversion, especially wind and solar energy, on nonlinear control of drives, as well as on diagnosis of drives and fault tolerant drives. Dr. Fuchs is Chairman of the Board of CEwind, a convener in standardization for the German Commission for Electrical, Electronic & Information Technologies and the International Electrotechnical Commission and a member of the German Association of Electrical Engineers and the European Power Electronics and Drives Association.