PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M STANDARD HIGH-SPEED PAL CIRCUITS

SRPS016 D2705, FEBRUARY 1984 REVISED MARCH 1992

Choice of Operating Speeds High-Speed, A Devices . . . 25 MHz Min Half-Power, A-2 Devices . . . 16 MHz Min Choice of Input/Output Configuration Package Options Include Both Ceramic DIP and Chip Carrier in Addition to Ceramic Flat Package
DEVICE PAL16L8 PAL16R4 PAL16R6 PAL16R8 I INPUTS 10 8 8 8 3-STATE O OUTPUTS 2 0 0 0 REGISTERED Q OUTPUTS 0 4 (3-state buffers) 6 (3-state buffers) 8 (3-state buffers) I/O PORT S 6 4 2 0

PAL16L8 J OR W PACKAGE (TOP VIEW)

I I I I I I I I I GND

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

VCC O I/O I/O I/O I/O I/O I/O O I

description
These programmable array logic devices feature high speed and a choice of either standard or half-power devices. They combine Advanced Low-Power Schottky technology with proven titanium-tungsten fuses. These devices will provide reliable, high-performance substitutes for conventional TTL logic. Their easy programmability allow for quick design of custom functions and typically results in a more compact circuit board. In addition, chip carriers are available for further reduction in board space. The Half-Power versions offer a choice of operating frequency, switching speeds, and power dissipation. In many cases, these Half-Power devices can result in significant power reduction from an overall system level. The PAL16 M series is characterized for operation over the full military temperature range of 55C to 125C.

PAL16L8 FK PACKAGE (TOP VIEW)

I I I I I

4 5 6 7 8

3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

I I I VCC O I/O I/O I/O I/O I/O

Copyright 1992, Texas Instruments Incorporated

PAL is a registered trademark of Advanced Micro Devices Inc.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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I GND I O I/O

PAL16R4AM, PAL16R4A-2M, PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 D2705, FEBRUARY 1984 REVISED MARCH 1992

PAL16R4 J OR W PACKAGE (TOP VIEW)

PAL16R4 FK PACKAGE (TOP VIEW)

10

11

PAL16R6 J OR W PACKAGE (TOP VIEW)

10

11

PAL16R8 J OR W PACKAGE (TOP VIEW)

10

11

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I GND

OE Q Q

CLK I I I I I I I I GND

1 2 3 4 5 6 7 8 9

20 19 18 17 16 15 14 13 12

VCC Q Q Q Q Q Q Q Q OE

I I I I I

4 5 6 7 8

3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

I I CLK VCC Q Q Q Q Q Q

I GND

PAL16R8 FK PACKAGE (TOP VIEW)

OE I/O Q

CLK I I I I I I I I GND

1 2 3 4 5 6 7 8 9

20 19 18 17 16 15 14 13 12

VCC I/O Q Q Q Q Q Q I/O OE

I I I I I

4 5 6 7 8

3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

I I CLK VCC I/O Q Q Q Q Q

I GND

PAL16R6 FK PACKAGE (TOP VIEW)

OE I/O I/O

CLK I I I I I I I I GND

1 2 3 4 5 6 7 8 9

20 19 18 17 16 15 14 13 12

VCC I/O I/O Q Q Q Q I/O I/O OE

I I I I I

4 5 6 7 8

3 2 1 20 19 18 17 16 15 14 9 10 11 12 13

I I CLK VCC I/O I/O Q Q Q Q

PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M STANDARD HIGH-SPEED PAL CIRCUITS

SRPS016 D2705, FEBRUARY 1984 REVISED MARCH 1992

functional block diagrams (positive logic)

PAL16L8AM PAL16L8A-2M & 32 X 64 EN 1

7 7

O O I/O I/O I/O I/O I/O I/O

16 x I 10 16

7 7

16

7 7 7 7 6

PAL16R4AM PAL16R4A-2M OE CLK & 32 X 64 8 8 8 16 8 4 4 16 7 7 7 7 4 4 EN 1 I/O I/O I/O I/O Q 1 EN 2 C1 I=0 2 1D Q Q Q

16 x I 8

denotes fused inputs

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PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M STANDARD HIGH-SPEED PAL CIRCUITS

SRPS016 D2705, FEBRUARY 1984 REVISED MARCH 1992

functional block diagrams (positive logic)

PAL16R6AM PAL16R6A-2M OE CLK & 32 X 64 8 8 8 16 8 6 8 2 16 8 EN 1 Q Q Q 1 EN 2 C1 I=0 2 1D Q Q Q

16 x I 8

7 7 2 6

I/O I/O

PAL16R8AM PAL16R8A-2M OE CLK & 32 X 64 8 8 8 16 8 8 8 16 8 8 8 Q Q Q Q Q 1 EN 2 C1 I=0 2 1D Q Q Q

16 x I 8

8 denotes fused inputs

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PAL16L8AM, PAL16L8A-2M STANDARD HIGH-SPEED PAL CIRCUITS

SRPS016 D2705, FEBRUARY 1984 REVISED MARCH 1992

logic diagram (positive logic)

I 1 Increment 0 4 8 12 16 20 24 28 31

First Fuse Numbers

0 32 64 96 128 160 192 224

19

256 288 320 352 384 416 448 480 512 544 576 608 640 672 704 736 768 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 1824 1856 1888 1920 1952 1984 2016

18

I/O

17

I/O

16

I/O

15

I/O

14

I/O

13

I/O

12

11

Fuse number = First fuse number + Increment

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PAL16R4AM, PAL16R4A-2M STANDARD HIGH-SPEED PAL CIRCUITS

SRPS016 D2705, FEBRUARY 1984 REVISED MARCH 1992

logic diagram (positive logic)

CLK 1 Increment 0 4 8 12 16 20 24 28 31 First Fuse Numbers
0 32 64 96 128 160 192 224

19

I/O

256 288 320 352 384 416 448 480 512 544 576 608 640 672 704 736 768 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 1824 1856 1888 1920 1952 1984 2016

18

I/O

I=0 1D C1

17

I=0 1D C1

16

I=0 1D C1

15

I=0 1D C1

14

13

I/O

12

I/O

11

OE

Fuse number = First fuse number + Increment

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PAL16R6AM, PAL16R6A-2M STANDARD HIGH-SPEED PAL CIRCUITS

SRPS016 D2705, FEBRUARY 1984 REVISED MARCH 1992

logic diagram (positive logic)

CLK 1 Increment 0 4 8 12 16 20 24 28 31 First Fuse Numbers
0 32 64 96 128 160 192 224

19

I/O

256 288 320 352 384 416 448 480 512 544 576 608 640 672 704 736 768 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 1824 1856 1888 1920 1952 1984 2016

I=0 1D C1

18

I=0 1D C1

17

I=0 1D C1

16

I=0 1D C1

15

I=0 1D C1

14

I=0 1D C1

13

12

I/O

11

OE

Fuse number = First fuse number + Increment

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PAL16R8AM, PAL16R8A-2M STANDARD HIGH-SPEED PAL CIRCUITS

SRPS016 D2705, FEBRUARY 1984 REVISED MARCH 1992

logic diagram (positive logic)

CLK 1 Increment 0 4 8 12 16 20 24 28 31

First Fuse Numbers

0 32 64 96 128 160 192 224

I=0 1D C1

19

256 288 320 352 384 416 448 480 512 544 576 608 640 672 704 736 768 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792 1824 1856 1888 1920 1952 1984 2016

I=0 1D C1

18

I=0 1D C1

17

I=0 1D C1

16

I=0 1D C1

15

I=0 1D C1

14

I=0 1D C1

13

I=0 1D C1

12

11

OE

Fuse number = First fuse number + Increment

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PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 D2705, FEBRUARY 1984 REVISED MARCH 1992

programming information
Texas Instruments programmable logic devices can be programmed using widely available software and inexpensive device programmers. Complete programming specifications, algorithms, and the latest information on hardware, software, and firmware are available upon request. Information on programmers capable of programming Texas Instruments programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
NOTE 1: These ratings apply except for programming pins during a programming cycle.

recommended operating conditions

MIN VCC VIH VIL IOH IOL TA Supply voltage High-level input voltage Low-level input voltage High-level output current Low-level output current Operating free-air temperature 55 25 4.5 2 NOM 5 MAX 5.5 5.5 0.8 2 12 125 UNIT V V V mA mA C

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PAL16L8AM, PAL16R4AM, PAL16R6AM, PAL16R8AM STANDARD HIGH-SPEED PAL CIRCUITS

SRPS016 D2705, FEBRUARY 1984 REVISED MARCH 1992

electrical characteristics over recommended operating free-air temperature range

PARAMETER VIK VOH VOL IOZH IOZL II IIH IIL IOS ICC I/O Ports All others OE input All others VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 0.5 V VI = 0, 30 Outputs open 75 Outputs I/O ports Outputs I/O ports VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, TEST CONDITIONS II = 18 mA IOH = 2 mA IOL = 12 mA VO = 2.7 V VO = 0.4 V VI = 5.5 V VI = 2.7 V MIN 2.4 TYP 3.2 0.25 0.4 20 100 20 100 0.2 100 25 0.2 0.1 250 180 MAX 1.5 UNIT V V V A A mA A mA mA mA

timing requirements
MIN fclock tw tsu th Clock Frequency Pulse duration (see Note 2) Setup time, input or feedback before CLK Hold time, input or feedback after CLK Clock high Clock low 0 15 20 25 0 ns ns ns MAX 25 UNIT MHz

NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are only for clock high or low, but not for both simultaneously.

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER fmax tpd tpd ten tdis ten tdis FROM (INPUT) I, I/O CLK OE OE I, I/O I, I/O TO (OUTPUT) O, I/O Q Q Q O, I/O O, I/O R1 = 390 , R2 = 750 , See Figure 1 TEST CONDITION MIN 25 TYP 45 15 10 15 10 14 13 30 20 25 25 30 30 MAX UNIT MHz ns ns ns ns ns ns

All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid test equipment degradation.

10

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PAL16L8A-2M, PAL16R4A-2M, PAL16R6A-2M, PAL16R8A-2M STANDARD HIGH-SPEED PAL CIRCUITS

SRPS016 D2705, FEBRUARY 1984 REVISED MARCH 1992

electrical characteristics over recommended operating free-air temperature range

PARAMETER VIK VOH VOL IOZH IOZL II IIH IIL IOS ICC I/O Ports All others OE input All others VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 0.5 V VI = 0, 30 Outputs open 75 Outputs I/O ports Outputs I/O ports VCC = 4.5 V, VCC = 4.5 V, VCC = 4.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, VCC = 5.5 V, TEST CONDITIONS II = 18 mA IOH = 2 mA IOL = 12 mA VO = 2.7 V VO = 0.4 V VI = 5.5 V VI = 2.7 V MIN 2.4 TYP 3.2 0.25 0.4 20 100 20 100 0.2 100 25 0.2 0.1 250 90 MAX 1.5 UNIT V V V A A mA A mA mA mA

timing requirements
MIN fclock tw tsu th Clock Frequency Pulse duration (see Note 2) Setup time, input or feedback before CLK Hold time, input or feedback after CLK Clock high Clock low 0 25 25 35 0 ns ns ns MAX 16 UNIT MHz

NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are only for clock high or low, but not for both simultaneously.

switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER fmax tpd tpd ten tdis ten tdis FROM (INPUT) I, I/O CLK OE OE I, I/O I, I/O TO (OUTPUT) O, I/O Q Q Q O, I/O O, I/O R1 = 390 , R2 = 750 , See Figure 1 TEST CONDITION MIN 16 TYP 25 25 11 20 11 25 25 40 25 25 25 40 35 MAX UNIT MHz ns ns ns ns ns ns

All typical values are at VCC = 5 V, TA = 25C. Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid test equipment degradation.

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11

PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 D2705, FEBRUARY 1984 REVISED MARCH 1992

PARAMETER MEASUREMENT INFORMATION

5V

S1 R1 From Output Under Test CL (see Note A) R2 Test Point

LOAD CIRCUIT FOR 3-STATE OUTPUTS Timing Input tsu Data Input 1.5 V 3V 1.5 V 0 th 3V 1.5 V 0 VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 3V Input tpd In-Phase Output tpd Out-of-Phase Output (see Note D) 1.5 V 1.5 V 1.5 V 1.5 V 0 tpd VOH 1.5 V VOL tpd VOH 1.5 V VOL Output Control (low-level enabling) ten 1.5 V 1.5 V 0 tdis Low-Level Pulse 3V 1.5 V 1.5 V 0 VOLTAGE WAVEFORMS PULSE DURATIONS 3V tw High-Level Pulse 3V 1.5 V 1.5 V 0

3.3 V
Waveform 1 S1 Closed (see Note B) ten Waveform 2 S1 Open (see Note B) 1.5 V VOL tdis VOH 1.5 V

VOL + 0.5 V

VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES

VOH 0.5 V 0V

VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses have the following characteristics: PRR 10 MHz, tr and tf 2 ns, duty cycle = 50% D. When measuring propagation delay times of 3- state outputs, switch S1 is closed. E. Equivalent loads may be used for testing.

Figure 1. Load Circuit and Voltage Waveforms

12

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SRPS016

IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TIs standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL APPLICATIONS). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMERS RISK. In order to minimize risks associated with the customers applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TIs publication of information regarding any third partys products or services does not constitute TIs approval, warranty or endorsement thereof.

Copyright 1998, Texas Instruments Incorporated

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