DIRECT CONVERSION RECEIVERS IN WIDE-BAND SYSTEMS

THE KLUWER INTERNATIONAL SERIES IN ENGINEERING AND COMPUTER SCIENCE ANALOG CIRCUITS AND SIGNAL PROCESSING
Consulting Editor: Mohammed Ismail. Ohio State University Related Titles:
AUTOMATIC CALIBRATION OF MODULATED FREQUENCY SYNTHESIZERS D. McMahill ISBN: 0-7923-7589-0 MODEL ENGINEERING IN MIXED-SIGNAL CIRCUIT DESIGN S. Huss ISBN: 0-7923-7598-X CONTINUOUS-TIME SIGMA-DELTA MODULATION FOR A/D CONVERSION IN RADIO RECEIVERS L. Breems, J.H. Huijsing ISBN: 0-7923-7492-4 DIRECT DIGITAL SYNTHESIZERS: THEORY, DESIGN AND APPLICATIONS J. Vankka, K. Halonen ISBN: 0-7923 7366-9 SYSTEMATIC DESIGN FOR OPTIMISATION OF PIPELINED ADCs J. Goes, J.C. Vital, J. Franca ISBN: 0-7923-7291-3 OPERATIONAL AMPLIFIERS: Theory and Design J. Huijsing ISBN: 0-7923-7284-0 HIGH-PERFORMANCE HARMONIC OSCILLATORS AND BANDGAP REFERENCES A. van Staveren, C.J.M. Verhoev en, A.H.M. van Roermund ISBN: 0-7923-7283-2 HIGH SPEED A/D CONVERTERS: Understanding Data Converters Through SPICE A. Moscovici ISBN: 0-7923-7276-X ANALOG TEST SIGNAL GENERATION USING PERIODIC DATA STREAMS B. Dufort, G.W. Roberts ISBN: 0-7923-7211-5 HIGH-ACCURACY CMOS SMART TEMPERATURE SENSORS A. Bakker, J. Huijsing ISBN: 0-7923-7217-4 DESIGN, SIMULATION AND APPLICATIONS OF INDUCTORS AND TRANSFORMERS FOR Si RF ICs A.M. Niknejad, R.G. Meyer ISBN: 0-7923-7986-1 SWITCHED-CURRENT SIGNAL PROCESSING AND A/D CONVERSION CIRCUITS: DESIGN AND IMPLEMENTATION B.E. Jonsson ISBN: 0-7923-7871-7 RESEARCH PERSPECTIVES ON DYNAMIC TRANSLINEAR AND LOG-DOMAIN CIRCUITS W.A. Serdijn, J. Mulder ISBN: 0-7923-7811-3 CMOS DATA CONVERTERS FOR COMMUNICATIONS M. Gustavsson, J. Wikner, N. Tan ISBN: 0-7923-7780-X DESIGN AND ANALYSIS OF INTEGRATOR-BASED LOG -DOMAIN FILTER CIRCUITS G.W. Roberts, V. W. Leung ISBN: 0-7923-8699-X VISION CHIPS A. Moini ISBN: 0-7923-8664-7

DIRECT CONVERSION RECEIVERS IN WIDE-BAND SYSTEMS

by

Aarno Prssinen
Nokia Research Center

KLUWER ACADEMIC PUBLISHERS

NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW

eBook ISBN: Print ISBN:

0-306-47545-6 0-7923-7607-2

2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print 2001 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: and Kluwer's eBookstore at: http://kluweronline.com http://ebooks.kluweronline.com

Preface
This book is based on my doctoral thesis at the Helsinki University of Technology. Several different projects during five years guided me from the basics of the RF IC design to the implementations of highly integrated radio receiver chips. Sharing time and effort between IC and system issues is not always straightforward. I have been lucky to follow both topics and share experiences with diligent and enthusiastic people having different specialities. As a result, this book will cover a wide range of different topics needed in the design of highly integrated radio receivers. Experiences from the first receiver prototypes for the third generation cellular systems form the basis of this book. Most of the issues are directly related to the early proposals of European and Japanese standardization organizations. For example, the chip rate was originally set to 4.096 Mcps in a wide-band CDMA channel. I have kept that number in the book in most of the examples although it has been later changed to 3.84 Mcps. I hope that the readers will accept that and the possible other incompabilities to the latest specifications. At least in the research phase the changes even in the most essential requirements are definitely not a rare incident and IC designers should be able to react and modify their designs as soon as they can. Also several other new radio systems, like Bluetooth and wireless LAN, are coming to the market in a relatively short period of time hence often demanding shared resources and fast development times from IC designers. Radio system characteristics should be quickly transferred into integrated circuits using the most optimal architecture in each case. I hope that this book will be useful not only for IC designers contemplating on third generation cellular systems but also for professionals working with wider area of applications. To promote that I have tried to collect the most essential issues from radio communication principles without going deep into theory. I have assumed that the reader is familiar with the basic RF and IC design principles, and most of the details can be found in the references. The main focus in this book is to transfer the system description into an optimal IC implementation in different cases. Typically new systems will be specified without deep understanding of the implementation issues and even a small detail may cause considerable difficulties for the realization and extend the development time. Maybe this book could also give communications engineers some advice on the recent trends, limitations and capabilities of modern IC techniques for radio reception. I have done the research work included in this book at the Electronic Circuit Design Laboratory, Helsinki University of Technology except for one year at the University of California Santa Barbara. My supervisor Professor Kari Halonen deserves my gratitude for his confidence to my work and for giving me excellent challenges and opportunities. With a great enthusiasm for analog electronics Professor Veikko Porra guided my interest in this field during my studies and in the early steps of IC design. My first research project was given by Professor Stephen I. Long from the University of California Santa Barbara. He also offered me the possibility to work in California and instructed my research for several years. I am grateful for all his wise pieces of advice and for teaching me a scientific way of thinking. I would also like to thank Dr. Petteri Alinikula for the important support and encouragement he gave me as a teacher and as a mentor at the beginning of my RF IC design efforts. I would like to thank all my colleagues at the Electronic Circuit Design Laboratory. Especially, Mr. Kari Stadius and Dr. Risto Kaunisto deserve my gratitude for teaching me the essential practices of IC design and later being my close friends and advisors. Dr. Saska Lindfors taught me a lot of things about CMOS design and I will remember the cooperation in subsampling issues as a fruitful experience. I learned the principles of the third generation cellular systems in the team with Jarkko Jussila, Jussi Ryynnen, Lauri Sumanen and Kalle Kiveks. Their

dedication to the collective challenges when integrating direct conversion receivers has been respectable. I would like to thank all of them individually and acknowledge their importance as members of the team. Their work is an essential part of this book. Rami Ahola deserves my gratitude for prompt process support. I would also like to thank Rahul Magoon for the productive discussions and help during my stay at Santa Barbara. Timo Knuuttila has promoted this book by offering a challenging project to get acquainted with the third generation systems. Mauri Honkanen has been a significant advisor for me in the area of radio systems. Professor Qiuting Huang, Dr. Jan Sevenhans and Dr. Pertti Iklinen are acknowledged for reviewing my thesis. I would like to express my warmest thanks for their encouraging comments. I wish to thank my wife Salla, my parents Anna-Leena and Tapio and my sister Maria with her family for their constant and strong support. This book is based on the work, which has been financed by Graduate School in Electronics, Telecommunications and Automation, Technology Development Centre of Finland, Academy of Finland, Nokia Networks and Nokia Mobile Phones. Also, grants by Nokia Foundation, Foundation for Financial Aid at the Helsinki University of Technology, Emil Aaltonen Foundation and Elektroniikkainsinrien sti (Foundation of Electronics Engineers in Finland) have given significant support. All of them are gratefully acknowledged.

Aarno Prssinen September 2001

ii

Contents
Preface Contents Symbols and Abbreviations Symbols Abbreviations 1 Introduction 2 System Requirements for Radio Receivers in Wireless Communications 2.1 Mobile Communications 2.1.1 Wireless Systems 2.2 Multiple Access Methods and Duplexing 2.2.1 Frequency Division Multiple Access 2.2.2 Time Division Multiple Access 2.2.3 Code Division Multiple Access 2.2.4 Duplexing 2.3 Digital Modulation 2.3.1 Binary Phase Shift Keying (BPSK) 2.3.2 Quadrature Phase Shift Keying (QPSK) 2.3.3 Frequency Shift Keying (FSK) 2.3.4 Gaussian-Filtered Minimum Shift Keying (GMSK) 2.3.5 Quadrature Amplitude Modulation (QAM) 2.3.6 DS-CDMA QPSK Transmitter 2.4 Design Parameters for Radio Receivers 2.4.1 Sensitivity 2.4.2 Intersymbol Interference 2.4.3 Selectivity 2.4.4 Dynamic Range 2.4.5 Gain and Interface to Digital Signal Processing 2.4.6 Image Rejection Ratio 2.4.7 Quadrature Demodulation 2.4.8 Special Topics in CDMA Communications References Receiver Architectures 3.1 Superheterodyne 3.2 Direct Conversion 3.3 Low-IF 3.4 Wide-Band IF 3.5 Direct Digital And Digital IF 3.6 Comparison of Architectures References Direct Conversion Receivers 4.1 Direct Conversion in Wide-Band Systems 4.1.1 DC Offsets and Flicker Noise 4.1.2 Envelope Distortion 4.2 Radio Design iii i iii v v xii 1 3 3 6 8 9 9 9 12 12 14 15 17 18 18 19 19 20 25 28 41 46 51 56 59 73 76 77 80 86 90 92 97 98 104 104 104 109 115

4.3 Functional Blocks in Direct Conversion Receivers 4.3.1 Low-Noise Amplifiers 4.3.2 Mixers 4.3.3 LO Generation and I/Q Balance 4.3.4 Filtering 4.3.5 A/D Converters 4.3.6 Decoupling 4.4 Active Mixers in Direct Conversion 4.4.1 Active Mixer Topologies 4.4.2 Interfaces to LNA and Baseband 4.4.3 Theoretical Characterization of IIP2 in Transconductance Mixers 4.4.4 Switching Core 4.4.5 BiCMOS Transconductance Mixer 4.5 Downconversion by Subsampling 4.6 Single-Chip Radio Receivers 4.6.1 Frequency Planning in Mixed-Mode Implementations 4.7 IC Implementations References Circuit Implementations 5.1 Subsampling Mixer 5.1.1 Circuit Description 5.1.2 Measurement Setup 5.1.3 Experimental Results 5.1.4 Summary of the Subsampling Mixer 5.2 Low-Noise Amplifier and Interface to a Subsampling RF Front-End 5.2.1 Low-Noise Amplifier 5.2.2 Resonator Load with On-Chip Coupling Capacitors 5.2.3 Current Biasing Circuit for the LNA 5.2.4 Implementation 5.2.5 Summary of the LNA and Interface to Subsampling Mixer 5.3 Chipset for Direct Conversion WCDMA Receiver 5.3.1 Building Blocks of the Direct Conversion Receiver 5.3.2 Layout 5.3.3 Experimental Results 5.3.4 Summary of the WCDMA Chip Set 5.4 Single-Chip Direct Conversion Receiver for WCDMA 5.4.1 Circuit Design 5.4.2 Experimental Results 5.4.3 Summary of the Single-Chip Direct Conversion Receiver References

116 116 121 123 129 131 135 137 137 141 142 155 164 165 169 170 176 178 197 197 197 201 202 205 205 206 207 209 209 211 211 212 217 218 222 223 223 224 226 227

iv

Symbols and Abbreviations

Symbols
amplitude, gain of one branch in image rejection receiver second-order cross-modulation component at baseband third-order cross-modulation component at baseband dc level amplitude of the intermediate frequency signal amplitude of the second-order intermodulation product voltage gain of a low noise amplifier amplitude of the local oscillator signal voltage gain of a matching network voltage gain due to finite impedance levels amplitude of the nth harmonic of a local oscillator signal amplitude of a radio frequency signal amplitudes of positive and negative radio frequency signals desired signal component voltage gain voltage gain of a low noise amplifier voltage gains of successive stages gain scaling factors in active RC filter input amplitudes in two-tone test gain of the other branch in image rejection receiver information bandwidth effective noise bandwidth total radio bandwidth of a specific system transmission bandwidth spreading codes capacitor in the biasing network on-chip capacitance between ground and supply coupling capacitance positive and negative coupling capacitances degeneration capacitance decoupling capacitance off-chip capacitors gate-source capacitance hold capacitance in-phase load capacitance quadrature-phase load capacitance capacitance per unit area of the gate oxide parasitic capacitance capacitance of a damped resonator additional sampling capacitor capacitance to substrate total capacitance base-emitter capacitance capacitors

control node balancing factor deterioration parameter for intersymbol interference diameter of bondwire energy per bit sampling noise frequency noise factor bit rate of the data bandwidth of the desired channel at baseband blocking frequencies center frequency, cutoff frequency cutoff frequency of baseband filter corner frequency of flicker noise minimum channel spacing clock frequency noise factor of device under test cutoff frequency of a highpass filter intermediate frequency first and second intermediate frequencies noise factor of a low noise amplifier local oscillator frequency noise factor of mth stage Nyquist rate in sampling radio frequency radio frequencies in two-tone test sampling frequency or rate signal frequency frequency of a spurious component noise factor in subsampling maximum unity gain frequency noise factor of the receiver chain output frequency of the transmitter upper limit of the signal band noise factors of successive stages gate function power gain coding gain improvement in signal-to-noise ratio due to digital signal processing power gain of a low noise amplifier gate function in mixing positive and negative gate functions of commutating switches transconductance transconductances of positive and negative input stages gain at the passband of the receiver gain at the stopband of the receiver processing gain output conductance power gains of successive stages transfer function transfer function of a specific block

vi

impulse responses interference power current matrix balanced current in a two-port collector current supply current collector currents drain current drain saturation current emitter currents interference of the overhead channel from the own base stations interference in the CDMA reception due to cross-modulation interference in the CDMA reception due to intersymbol interference interference from non-CDMA transmissions or jammers at band of interest modal current matrix in-band noise power in CDMA channel interference from the traffic channels in other cells in CDMA system interference of the overhead channels from other near-by base stations in-band interference of other CDMA traffic channels at the band of interest lowpass filtered negative output current positive and negative output currents lowpass filtered positive output current interference in the CDMA reception due to phase noise interference in the CDMA reception due to quantization noise implementation-oriented non-idealities at the received CDMA radio channel radio frequency current saturation current saturation currents of bipolar transistors tail current of a switching pair tail current interference in the CDMA reception from the transmitter leakage unbalanced current in a two-port dc parts of the collector currents in bipolar transistors input currents of a two-port input compression point intermediate frequencies in the receiver starting from the first IF second-order input intercept point single-ended second-order input intercept point third-order input intercept point third-order input intercept points of successive stages third-order input intercept point at high signal levels positive and negative inputs Boltzmann's constant, number of harmonic component flicker noise factor, process and size parameter of a MOSFET inductance, length of gate in a MOSFET bondwire inductance common mode source inductance degeneration inductance emitter inductance gate inductance input inductance

vii

length of bondwire load inductance inductance of a damped resonator source inductance isolation between transmitter and input ports of the receiver inductors modulation index, number of bits, number of harmonic component implementation margin for digital algorithms MOSFETs scaling factor, number of harmonic component, number of gate fingers incoming noise at the input of a analog-to-digital converter noise power of device under test input noise power total input referred noise power internal noise power of the device or block measured noise power output noise power total phase noise power of the receiver in base station total phase noise power of a receiver total phase noise power of a transmitter quantization noise subsampling ratio internal noise power of spectrum analyzer total number of traffic channels at the CDMA radio channel maximum number of traffic channels at the CDMA radio channel thermal noise power thermal noise floor of the transmitter noise power spectral density noise figure noise figure of device under test total noise figure of the receiver total noise figure multiplication factor for the power, number of harmonic component power of the adjacent channel input power of a blocking signal power of a single traffic channel in CDMA transmission power dissipation probability of bit error multiplier matrix envelope power power of the image frequency component second- and third-order intermodulation products input referred second- and third-order intermodulation products input power maximum acceptable input power local oscillator power power of the lower sideband signal power of the minimum detectable signal output power power at radio frequency power at the sensitivity level of a receiver

viii

input referred power of a spurious component power of the upper sideband signal power of the wanted signal component sum terms magnitude of electronic charge, number of harmonic component multiplier matrix quality factor of the input stage of a low noise amplifier bipolar transistors sum terms bipolar transistors number of harmonic component base resistance biasing resistance decoupling resistance feedback resistance gate resistance input resistance series resistance of a inductor load resistance positive and negative load resistances output resistance parasitic resistance damping resistance of a LC network symbol rate, source resistance switch resistance resistors sheet resistance power spectral density signal at the input of a analog-to-digital converter correction factor for quantization noise input signal power scattering parameter for differential matching output signal power power spectral density of the radio frequency signal power spectral density of the thermal noise in the system spurious free dynamic range of the receiver signal-to-noise ratio at the output of a analog-to-digital converter signal-to-noise ratio of the scrambled channel signal-to-noise ratio of the correlated information signal-to-noise ratio at the input minimum required signal-to-noise ratio for detection of a signal signal-to-noise ratio at the output signal-to-quantization noise ratio scattering parameters of a two-port (reflection) scattering parameters of a two-port (transmission) absolute temperature bit period symbol period voltage matrix bias voltage base-emitter voltage

ix

dc-term of the base-emitter voltage base-emitter voltages biasing voltage balanced voltage in a two-port supply voltage positive and negative collector-emitter voltages common mode voltage dc voltage dc voltage at the output supply voltage drain-source saturation voltage of a MOSFET gate-source voltage positive in-phase input voltage negative in-phase input voltage input referred amplitude of second-order distortion output voltage of the third-order intermodulation product input voltage differential input voltage positive and negative input voltages input voltages of successive stages positive input voltage negative input voltage in-phase output voltage positive in-phase output voltage negative in-phase output voltage voltage of the least significant bit voltage of the local oscillator signal positive and negative local oscillator voltages modal voltage matrix noise voltage input referred noise voltages of successive stages output noise voltages of successive stages noise voltage of the source overdrive voltage output voltage output voltage of the analog baseband processing block positive and negative output voltages output voltages of successive stages positive and negative output voltages dc voltage of the virtual ground node in a differential pair peak-to-peak voltage positive quadrature-phase input voltage negative quadrature-phase input voltage quadrature-phase output voltage positive quadrature-phase output voltage negative quadrature-phase output voltage maximum input voltage of an analog-to-digital converter, reference voltage voltage of the radio frequency signal positive and negative radio frequency voltages output voltages of the mixer core source voltage

output voltage of a spurious tone thermal voltage threshold voltage unbalanced voltage in a two-port parameter of a MOSFET input voltages of a two-port voltage of an amplitude envelope width of gate in a MOSFET bandwidth of the single sideband signal radio frequency input excitation input excitation sampled input signal frequency responses output response response of the hold function response of the tracking function impedance matrix input impedance input impedances of successive stages load impedance modal impedance matrix modal z-parameters output impedances of successive stages source impedance inductance between supply rails z-parameters roll-off factor of a Nyquist filter, current gain factor, factor low frequency leakage coefficient in the downconversion coefficient of radio frequency leakage to local oscillator port nonlinear coefficients coefficient of the fundamental tone in the presence of blocker gain coefficient at baseband gain coefficient in downconversion gain coefficient at radio frequency nonlinear coefficients relative to fundamental tone envelope coefficient at baseband second-order nonlinear coefficient at local oscillator port envelope coefficient in downconversion envelope coefficient at radio frequency transconductance parameter phase error after the first downconversion in the image rejection receiver denominator in z-to-S transformation gain error between quadrature branches amplitude imbalance at radio frequency gain degradation from maximum deviation from center frequency, frequency slot imbalance between transconductances saturation current mismatch relative input power compared to minimum detectable signal second- and third-order intermodulation products relative to fundamental

xi

relative resistor mismatch emitter resistance mismatch load resistance mismatch deviation of the RC-product from nominal time difference from nominal clock jitter threshold voltage mismatch imbalance term difference between duty cycles of positive and negative gate functions difference in phase error between two radio frequency tones phase errors of differential input signals phase error of the local oscillator signal in the direct conversion receiver difference of the modulated tone from the carrier quantization noise phase response noise factor for MOSFET relative pulse widths of positive and negative gate functions duty cycle nominal duty cycle of gate functions posivite and negative duty cycles of gate functions permeability surface mobility of the channel for the nMOS device phase error of the first local oscillator signal in the image rejection receiver time delay, pulse width maximum passband group delay ripple group delay carrier frequency intermediate frequency frequency of the second-order intermodulation component input frequency local oscillator frequency local oscillator frequencies in the receiver starting from the front-end modulation frequency highest frequency component of a modulated channel at baseband resonance frequency radio frequency radio frequencies in two-tone test resonance frequency excitation frequencies in two-tone test frequency exactly between input and local oscillator frequencies

Abbreviations
ac A/D ADC AFC alternating current analog-to-digital analog-to-digital converter automatic frequency control

xii

AGC AM AMPS B BB BC BDR BER BFSK BiCMOS BJT BPSK BW C C/A CDMA CLCC CLK CMFB CMOS CMRR C/N CQFP CR CT-2 D/A DAC dc DCR DCS1800 DDS DECT D-MESFET DNL DSB DS-CDMA DSP DS-SS DUT EGSM EHF E-MESFET ENOB EVM FDD FDMA FET FFT FH-CDMA FH-SS FM

automatic gain control amplitude modulation advanced mobile phone system bipolar baseband BiCMOS blocking dynamic range bit error rate binary frequency shift keying bipolar complementary metal oxide semiconductor bipolar junction transistor binary phase-shift keying bandwidth CMOS coarse acquisition code division multiple access ceramic leadless chip carrier clock common mode feedback complementary metal oxide semiconductor common mode rejection ratio carrier-to-noise ratio ceramic quad flat pack capacitor resistor second generation cordless telephone digital-to-analog digital-to-analog converter direct current direct conversion receiver digital communications system direct digital synthesizer digital enhanced cordless telecommunications depletion-type MESFET differential nonlinearity double sideband direct sequence code division multiple access digital signal processing direct sequence spread spectrum device under test enhanced global system for mobile communications extreme high frequencies enhancement-type MESFET effective number of bits error vector magnitude frequency division duplexing frequency division multiple access field effect transistor fast Fourier transform frequency hopped code division multiple access frequency hopped spread spectrum frequency modulation

xiii

FSK GaAs GBW GFSK GMSK GPS GSM HF HPF I IC ICP IF IIP IMD IMT-2000 INL IRR ISI ISM IS-54 IS-95 LC LF LMS LNA LO LPF LSB MDS MESFET MF MIM MIX MOS MOSFET MPSK MSK NADC NF nMOS NMT NRZ OCP OIP OQPSK OSR PA PAM PCB PDC

frequency shift keying gallium arsenide gain bandwidth Gaussian-filtered frequency shift keying Gaussian-filtered minimum shift keying global positioning system global system for mobile communications high frequencies highpass filter in-phase integrated circuit input compression point intermediate frequency input intercept point intermodulation distortion international mobile telecommunications 2000 integral nonlinearity image rejection ratio intersymbol interference industrial, scientific, medical interim standard 54 interim standard 95 inductor capacitor low frequencies least mean square low-noise amplifier local oscillator lowpass filter least significant bit minimum detectable signal metal semiconductor field effect transistor medium frequencies metal-insulator-metal mixer metal oxide semiconductor metal oxide semiconductor field effect transistor multiple phase shift keying minimum shift keying North American digital cellular noise figure n-channel metal oxide semiconductor field effect transistor Nordic mobile telephone non-return-to-zero output compression point output intercept point offset quadrature phase-shift keying oversampling ratio power amplifier pulse amplitude modulation printed circuit board personal digital cellular

xiv

PDF PHS PLL PM pMOS PSD PSK Q QAM QPSK RC RC-PP RLC RF RRcos RSSI SC SCFL SFDR SHF Si SiGe SNDR SNR SSB TDD TDMA THD TH-SS TRF UHF UMTS VHF V-I VLF VLSI VSF WCDMA VCO WLAN
2-FSK 3GPP #

probability distribution function personal handy phone system phase locked loop phase modulation p-channel metal oxide semiconductor field effect transistor power spectral density phase-shift keying quadrature-phase, quality factor quadrature amplitude modulation quadrature phase-shift keying resistor capacitor resistor capacitor polyphase network resistor inductor capacitor radio frequency root raised cosine (filter) received signal strength indicator switched capacitor source coupled FET logic spurious free dynamic range super high frequencies silicon silicon germanium signal-to-noise and distortion ratio signal-to-noise ratio single sideband time division duplexing time division multiple access total harmonic distortion time hopped spread spectrum tuned radio frequency ultra high frequencies universal mobile telecommunications system very high frequencies voltage-to-current very low frequencies very large scaled integrated circuit variable spreading factor wide-band code division multiple access voltage controlled oscillator wireless local area network differentially encoded quadrature phase-shift keying binary frequency shift keying third generation partnership project number

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Introduction

Wireless communications is definitely one of the most significant driving forces in the analog electronics. The large volume of the industry and new services coming to the market are setting new demands also for traditional analog electronics. The main stream in the development of IC technologies has been focused on the digital signal processing and especially on the computer applications. As a consequence the line widths of MOS processes have decreased, which means smaller sizes together with increased speed and processing capabilities. The improvement of analog processes has followed the evolution in the second wave. MOS technologies are already capable of GHz-range analog signal processing while bipolar and BiCMOS processes are still dominating the market and also benefiting from improved high-frequency properties. In analog applications, the wireless communications have shown the direction in the development of IC processes. Although one general technology for all applications would be desirable the different characteristics of ideal analog and digital processes are difficult to combine. Another challenge is the mixed-mode signal processing where sensitive analog blocks must tolerate the distortion from digital rail-to-rail signals. These issues must be focused when the integration level increases towards single-chip radios. The single-chip receiver is quite a conflicting definition. A chip connected directly to the antenna recovering the transmitted data bits from the received information is surely not feasible in the near future. At least some external components are needed. A more realistic question would be whether digital signal processing could be done at all on the same chip with the sensitive analog RF front-end. More likely, a modern receiver should combine mixed-mode circuitry with RF as well as possible. Naturally, the minimized number of external components is a prerequisite. Another dimension in the modern receiver design is the choice of the optimal architecture for the implementation. The first century of the radio communications was mainly dominated by the superheterodyne architecture since its invention over an eighty years ago. Although it is still the most sensitive and selective structure, the integration level is limited because of a number of high-quality filters at the radio and intermediate frequencies. Therefore during the last ten years extensive research has taken place to achieve the corresponding performance with any other possible architecture more suitable for integration. The direct conversion receiver is a natural and simple option. The improved IC technologies have actually brought direct conversion, which invention dates back to the same era with superheterodyne, as a serious candidate for cellular applications. However, the fundamental limitations do not allow as general design approach as in the case of a superheterodyne receiver. The feasibility of direct conversion must be studied carefully in each system using parameters which are typically not considered when the overall system is specified. There are also some other possible structures, which will be discussed in this book. The other trend in the evolution focuses towards a digital receiver. The digital modulation methods have dominated the market since the GSM and other digital communications systems became general. The next step would be the processing of a larger number of channels digitally either at the baseband, at the intermediate or even at the radio frequency. Hence, some analog nonidealities could be avoided. The increased speed and resolution requirements of digital signal processing and the interface to the analog circuitry are critical issues in these direct digital or digital IF architectures. The scaling of the IC technologies constantly increases the speed and reduces the power consumption in the digital circuitry. The same benefit is however not easily achieved in analog circuits including the analog-to-digital conversion. In addition to the technological evolution and architectural aspects, the third main issue in the receiver integration is the growing demand of wireless services. The wireless internet and

multimedia applications should be possible in the third generation systems. The increased and flexible data rates need different approaches than in the existing systems. The extension of GSM to packet data services is one improvement. Another change will be the third generation systems which use a wide-band CDMA radio channel. The trade-offs compared to narrow-band systems will be different. Those issues must be taken into account also in the radio design. The focus of the book is on the design of wide-band radio receivers, and especially on the direct conversion of the radio channel from the radio frequency down to the baseband. The main emphasis is in the design of conventional direct conversion receivers, but also the limitations of the direct digital approach will be considered. Both issues are important and critical in the development of radio receivers for new and existing systems. The wide-band CDMA system for third generation cellular communications, often called UMTS or WCDMA, is analyzed in detail in this book. However, the same principles are generally applicable to all CDMA systems and in most cases to all radio receivers. This book is organized into five chapters. After the introduction, chapter 2 covers the basic background of the radio communications systems. The second part of the chapter focuses on the design parameters of the different analog blocks in a receiver at a fundamental level. Finally, the special requirements of wide-band CDMA receivers are analyzed. Chapter 3 introduces different radio architectures and describes the performance of some recent IC implementations. The architectures include superheterodyne, direct conversion, low-IF, wide-band IF or image rejection, digital IF and direct digital receivers. Detailed discussion about direct conversion receivers is given in chapter 4. First, system level requirements are introduced. Then, radio design and different functional blocks are described. The main emphasis is in the RF front-end circuitry. Separate sections are reserved for active and subsampling mixers after the general considerations. At the end of the chapter the special issues of single-chip receivers are dealt with followed by the comparison of reported direct conversion receivers and RF front-ends. Some IC implementations related to the topics of the book are presented in chapter 5. A subsampling RF downconversion mixer is implemented with a digital GaAs MESFET process. A CMOS LNA and an interface to a subsampling mixer are realized for demonstrating accoupling methods and efficient resonator structures for the LNA load. The two last sections contain the design and experimental results of a direct conversion receiver for WCDMA applications. The chipset and single-chip versions are presented separately. Both are implemented using the same BiCMOS technology.

System Requirements for Radio Receivers in Wireless Communications

The development of the mobile communications systems has come to the era when most of the signal processing is performed digitally. The advantages of digital communications for current technologies and requirements are evident. The wildest fortune-tellers are already proposing so called direct digital front-ends for mobile communications. The radio architectures including the direct digital approach are discussed in the next chapter. The intention of this chapter is to describe the signal environment and the most important phenomena, which must be considered in the radio design. They are general requirements for all types of receivers in wireless communications. Of course, the desired system and choice of the radio architecture have different influence on these requirements. The emphasis of the text is to give a review of the whole field, but concentrate especially on the specific issues in spread spectrum communications and their effects on the analog signal processing. In this dissertation, the term radio receiver is designated for the traditional analog portion of the receiver including the A/D converters. The digital core of the system is called as a digital signal processing block. Also, the term baseband is often used as describing only some digital functions, and the whole analog part is called as radio frequency (RF) signal processing. This is misleading or at least not a very precise expression. Hence, the analog receiver is distributed to RF, intermediate frequency (IF), baseband and A/D conversion blocks in this context.

2.1

Mobile Communications

All wireless systems operate in a troublesome environment of the electromagnetic radiation. The radio path itself has the strongest effect on the performance. The distance from the transmitter, other transmitters and transmission conditions are variable parameters, which continuously, and sometimes very rapidly, change the signals coming to the receiver. Antenna technologies and digital estimation and detection techniques have been developed to tolerate the fading and multipath conditions in transmission. Even more sophisticated methods to maximize the system performance will be adopted when the next generation of cellular systems will be launched. Simultaneously, the complexity of the systems increases and their control becomes extremely difficult. Still the target is the same as in days of Marconi: To deliver information everywhere without any restrictions of wires. In the modern world, the efficiency and limited amount of cost-efficient radio spectrum forces to the strict control of the spectrum and to the methods maximizing the spectral efficiency in different systems. Partly therefore, the design of a radio is and will be a challenge still over a hundred years after its invention. A radio receiver selects a certain frequency band and detects the transmitted information at that band from noise and other unwanted components shown in Figure 2.1. Radio spectrum is occupied by different communications systems, which are divided to narrower radio channels. Each physical channel can contain one or several traffic channels depending on the multiple access method. The key issue in a radio receiver is to detect a weak traffic channel when other channels containing much more power are present. The antenna of the receiver has some frequency selectivity and sometimes also directivity. Although its performance is important for the whole receiver, the main function is to collect the electromagnetic information from a relatively wide band compared to a certain system. The actual frequency selection is performed later in the receiver. Also, the other parameters described in this chapter are typically specified

for the receiver without an antenna for two reasons. First, they are much more difficult to measure and define when the results depend on the air interface. Second, the antenna has only little effect on those parameters or the performance of the antenna can be specified separately. The antenna must be matched typically to impedance level, but that is the only parameter needed for the interface to the receiver. The development of the adaptive antenna arrays and beam forming techniques are changing this ideology. However, these issues concern mainly on the digital signal processing part of the receiver, and the analog portion can be specified as earlier.

The wireless communications are today dominated by the different digital systems. Only broadcasting, television, and some older cellular or cordless systems still use analog modulations. The advantage of coding the information efficiently and with high quality to the radio channel has promoted the digital applications, and enabled to transmit also other services than voice in cellular systems. The block diagram of the transmitter and receiver are shown in Figure 2.2. The input data stream is first coded and interleaved in the transmitter. The former codes each bit into a longer bit sequence, and the latter reorganizes the data stream to avoid the loss of two successive bits. Both techniques protect the transmission against the multipath fading in the radio channel. They are purely digital operations and improve the signal-to-noise ratio or tolerance against fading in the reception. Next, the signal is modulated and the digital pulses are shaped or rounded in the filter in order to limit the output spectrum. Although the modulation, and typically also the pulse shaping, are digital operations, they must be considered when receiver architecture and specifications are defined. The topic will be discussed later in this chapter, and also in connection with the direct conversion receiver architecture in the following chapters. Finally, the data is upconverted to the desired radio frequency, amplified and filtered. The duplex-filter prevents the transmitter power from leaking and compressing the

receiver. The upconversion, filtering and amplification can be distributed to several steps. However, the transmitter topologies are not included in this dissertation, and the simplified block diagram is sufficient to describe the behavior. The receiver selects the desired radio system with a duplex-filter. The receiver portion of the duplex-filter is often called as a preselection filter according to its function. This is actually the general expression, because sometimes the transmitter can be isolated with a switch or the receiver is a stand-alone unit. For example, in the positioning systems, like GPS, only the receiver is portable, and hence duplexing is not required. Immediately after the first filtering, the signal is amplified to prevent the noise of the successive blocks from deteriorating the reception. Practically all high-performance radio systems require a low-noise amplifier (LNA) in the front-end. The signal is downconverted in one or several mixers depending on the architecture, and the desired channel is filtered before digital demodulation, deinterleaving, and decoding. The channel filtering is performed at some intermediate frequency, at baseband or gradually along the chain, and it can be analog, digital or a hybrid of those. The alternatives of the channel filtering will be discussed later in detail.

The rapidly improved digital technologies and signal processing techniques allow more complex functions and applications in wireless terminals. The digital communication systems are evolving quickly away from pure audio services to full multimedia centers. The traditional receiver is sometimes called only as a part of the radio interface in the system. It should be almost negligible, and the interest is in the coding of efficient algorithms to improve the performance and new applications for cellular systems. However, this black box i.e. the analog receiver still makes it possible to detect weak signals and relax the digital processing by limiting the huge dynamic requirements of the cellular systems before the transformation to the digital domain. The large harmonic content of digital signals after conversion to the analog domain and strict requirements of spectral purity in the transmission call for an efficient analog processing unit both in the transmitter and in the receiver. Although the power consumption of the digital circuits is decreasing more rapidly than in analog processing, the reduced supply voltage limits the dynamic range in analog-to-digital conversion, and part of the advantage is

lost due to increased parallel processing. The key analog functions will be needed in the future, but partitioning of different functions between the analog and digital domain can be changed.

2.1.1

Wireless Systems

The wireless systems vary from broadcast and television transmission to cellular telephones and wireless local area networks (WLAN). The coverage area or in cellular systems the cell size has reduced when personal messaging and rising data rates have been adopted. The individual needs and different services mean that the capacity must be shared to small units with various methods. The trend is towards the terminals, which can utilize different services and frequency ranges. The services can be divided at least to cellular phones, cordless phones, pagers, positioning systems and local area data networks. The cellular phones are the market drivers, but currently they provide not only voice services. Data services are increasing for example in GSM, and GPS-positioning will be installed to the same terminal quite soon. Finally, the third generation systems will try to combine the voice and different multimedia services directly under the same platform. The harmonization of the final specifications is still under discussion in the Third Generation Partnership Project (3GPP). The system uses direct sequence spread spectrum multiple access. Often, the system is called Universal Mobile Telecommunications System (UMTS), which has been actually the name for the European proposal. Table 2.1 collects some examples of the current wireless systems and different proposals for third generation systems are given in Table 2.2. For example, the chip rate of WCDMA has been changed later to 3.84 Mcps.

2.2

Multiple Access Methods and Duplexing

The multiple access method defines how the information in a single traffic channel is organized with respect to the other transmitted channels at the same band or elsewhere. The traffic channel means here the information of a single connection between two users in the system. In communications terminology, the traffic channel is normally called as a physical channel, which can contain one or more separate traffic channels. However, the traffic channel is a more descriptive term in this context to describe actually a physical channel and it is used later in this meaning. The multiple access gives a frame for the radio design, and it has a strong influence on the choice of the radio architecture and on the specification of the analog receiver. In this section, the different methods are compared when a fixed amount of information is transmitted, and also when flexible data rates are required. The multiple access can be done in the frequency, time or code domain, and the different principles are illustrated in Figure 2.3. The alternatives of the duplexing between the transmission and reception are briefly discussed in the end of this section.

2.2.1

Frequency Division Multiple Access

Frequency division multiple access (FDMA) is the basic form of the multi-band radio communications. The band is divided only to narrow frequency slots, and every transmitterreceiver pair has its own designated band. Pure FDMA is still used in broadcast and TV transmission, for example. In digital cellular communications, tens or hundreds of users must operate in a relatively small frequency band. It would require very narrow passbands and sharp transition bands for the channel filters if every unit has an own frequency slot. The capacity of a traffic channel could be increased only if several adjacent frequency slots are reserved. This would require reconfiguration of the hardware. In digital communications, the system would be also very sensitive to fading. It is not either practical to keep the whole cellular band in one system as a single frequency slot, and hence the FDMA is typically at the background of other access methods. The capacity of a radio channel, which is practical for implementations, can be divided to several users either in the time or code domain.

2.2.2

Time Division Multiple Access

In time division multiple access (TDMA), each frequency channel is divided into time slots, and every nth slot is reserved for a single traffic channel. For example in GSM, a 200 kHz radio channel consists of eight time slots. Hence, every frequency channel can contain eight different transmissions, which relaxes the frequency allocation and re-use. In a TDMA system, the synchronization of different mobile transmitters at a single carrier is required to prevent the traffic channels from overlapping in time. There are however transients in the power level of the reception band all the time due to the switching of the TDMA channels. They may occur also during the received burst because the different radio channels are not necessarily synchronized. This must be taken into account in the design of a receiver. In a TDMA system, the available capacity for a single user is defined well, but limited to a single time slot at a certain band. The capacity can be increased either when more than one slot is reserved for a single user or by improving the efficiency of the data transfer. These methods are adopted, for example, in cellular specifications including high data rate extensions for the GSM, which will come to market soon. However, the signal must be a certain amount above the noise and distortion at the reception band, and during the transmission no other traffic channel lies at that frequency simultaneously.

2.2.3

Code Division Multiple Access

The code division multiple access (CDMA) systems are based on the pseudorandom sequences of orthogonal codes. The code can be either a digital bit stream or a frequency pattern. The former method is called direct sequence spread spectrum (DS-SS), and the latter frequency hopped spread spectrum (FH-SS). Also, time-hopping (TH-SS) is a possible coding method. Here, the discussion concentrates to the direct sequence, because it will be used in the third generation cellular systems and the integrated circuits presented later are designed for that application. The basic principle of the frequency hopping is explained in the end of this subsection. The time-hopping approach is rarely used and therefore not discussed in detail. The CDMA principle relies on the set of known codes, which can be generated with controllable and relatively easy methods. These pseudorandom sequences resemble digital noise to each other, and in the analog domain they have sinc-type of spectrum, which is defined by the modulation and pulse shaping filter of the transmitter. The orthogonality between the codes

means that they have ideally no correlation with each other, and therefore other code channels except the correct one behave like white noise at the reception band. When specifying the analog functions of the receiver, it is appropriate to assume that there is no cross-correlation between the codes at any condition. The principle of the direct sequence is shown in Figure 2.4. The transmitted data is multiplied with the spreading code i.e. the pseudorandom sequence, which is at a higher data rate than the information. The ratio between the transmission bandwidth, which is inversely proportional to period of each pseudorandom symbol, and information bandwidth is called either spreading factor or processing gain, It is defined in [5] as

where and are the transmission and information bandwidths, respectively. The scrambling of the data spreads the information over a much wider band than necessary. In the receiver, the radio channel is multiplied again with the same code. The transmitted data correlates with the code, and the narrow-band information is recovered. All uncorrelated information i.e. noise and other code channels are scrambled again, but their spectral response remains unchanged. Therefore the processing gain describes the improvement of the signal-to-noise ratio in the despreading process as

where

is the signal-to-noise ratio of the correlated information after the despreading and is the signal-to-noise ratio of the scrambled channel to any other signal, noise or distortion at the transmission band. It should be notified that after the despreading, the describes only the signal-to-noise ratio at the narrow signal band, and noise outside the band must be filtered out. This property makes it possible to place different channels at the same frequency band and detect the information, which is buried in the noise and other code channels. To distinguish the information and spreading codes, the units of the information and the spreading sequence are called a bit and a chip, respectively. The CDMA systems can be designed less sensitive to multipath interference, and they have tolerance against narrow-band interferers [1]. The latter means that any narrow-band interferer is scrambled in the despreading. Hence, it can be considered as noise in the detection at least in the simplified analysis, which is typically an appropriate first-order estimate. The military CDMA systems also benefit from the capability to transmit information below the thermal noise floor when the existence of the transmission is difficult to detect by the enemy. Also, it is more difficult to jam the opponents radio connections. The chip rate is typically fixed, which defines a certain bandwidth of the radio channel. The data rate does not depend only from that bandwidth. By changing the bit rate, the processing gain varies but the signal at the radio band remains unchanged if we consider only the spectral behavior. Hence, no reconfiguration of the hardware is required when variable data rates are transmitted. Therefore, it is straightforward to provide services at different data rates in a DSCDMA system. However, the number of orthogonal codes is limited, and the jamming has also effect on the maximum number of traffic channels at the same band. The information at a high data rate reserves several code sequences, and due to the smaller processing gain, a larger power is required for the transmission at equal conditions.

10

In spread spectrum communications, the required output power of the transmitter does not depend only on the distance and conditions at the radio path. The existence of other transmitters at the same band requires careful and continuous control of all power levels simultaneously. The power of each traffic channel should be minimized to avoid the jamming of the other channels. On the other hand, the connection must be insensitive to varying conditions, and new channels at the band. Therefore, some jamming margin is always required, and the power competition of different transmitters should be avoided. Compared to the other access methods, the control of a CDMA system is dynamic and much more difficult to administrate. The power control of the CDMA is the key element for the functionality and spectral efficiency of the system. At the system level the control is performed digitally, and the gain of the analog blocks both in the transmitter and in the receiver are tuned according to that scheme. The properties of the spread spectrum communications with respect to the radio receiver design are discussed at the end of this chapter.

In the frequency hopped CDMA communications, the spreading of the information is performed with pseudorandom jumps of the transmission frequency inside the total system band. One or more bits are transmitted at a certain radio channel, and then the oscillator moves the transmission to another frequency. The time-domain frequency pattern of the oscillator corresponds to the bit code in the direct sequence CDMA. In a frequency hopped system, the bandwidth of a radio channel can be narrower than in the direct sequence, but the jumping between the frequencies set strict requirements for the frequency synthesis. In principle, the multi-carrier approach can be used with both CDMA techniques to increase the capacity, but it requires also extra hardware. In TH-SS, the spreading in the time domain is performed with random changes of the time slots in the transmission. However, in the conditions of multiple transmissions at the same band, the time hopping requires very efficient error correction and interleaving schemes [1],

11

2.2.4

Duplexing

In all two-way communications with only one antenna, which is practically always the case in mobile terminals, the transmitter and receiver must be isolated from each other. Otherwise, the output power of the transmitter would saturate the sensitive receiver. Depending on the system requirements the duplexing is based either on frequency or time division. The frequency division duplexing (FDD) means that the transmission and reception are accomplished at different frequencies. This is done with a duplex filter, which has different transfer functions from the antenna terminal to the receiver and transmitter. FDD is typically used in cellular systems, because the filter attenuates also the transmitted powers from other near-by terminals [4], and the control of the system is easier when the forward and reverse paths are at different frequencies. High operation frequency and a relatively small space between the transmission and reception bands restrict the available technologies for the implementations. The problems for the receiver design are also the limited isolation between the transmitter and receiver ports and the inevitable loss at the passband of the filter. The cordless phones, like DECT, use often time division duplexing (TDD). The transmission and reception are at the same band but they do not overlap in time. In that case, a switch instead of a filter is a sufficient component to split the two paths. Because, the transmission and reception are not enabled at the same time, the transmitter power does not corrupt the reception. In GSM, both FDD and TDD are used simultaneously. However, a duplex-filter is typically used in mobile terminals instead of a switch, due to the better immunity against signals from other mobiles.

2.3

Digital Moduation

The increased capacity at a certain frequency band and a better accuracy in the presence of noise and distortion have changed the cellular communications from analog to digital since the early 1990s. The characteristics, and especially the capacity requirements, of the different systems define how efficient modulation is needed. The spectral efficiency is typically improved when complexity of the modulation increases. Except of the stricter requirements in digital signal processing and its timing, the design of the analog receiver becomes also more complicated. This section covers a brief introduction to digital modulations and their properties, which have effect on the analog circuit design. The main focus will be in the Quadrature Phase Shift Keying (QPSK) because it will be used in the traffic channels of the WCDMA systems. Some other methods are selected to introduce different aspects in their behavior. In the following chapters, some properties of the modulations are discussed with respect to the receiver architectures and their specifications. The modulation codes the information at the radio carrier. In the case of one traffic channel at a single frequency carrier in one time slot, the modulation in the radio channel is defined only by the transmitted information, which is under reception. This is valid for other multiple access methods except for the CDMA. In the spread-spectrum communications, a certain traffic channel has always a specified modulation, but each radio channel contains several traffic channels, which can have non-equal powers. Hence, the received radio channel has different modulation characteristics than the traffic channel of interest, and former has actually more influence on the analog performance. The complete analysis would require the knowledge from the statistical properties of the total radio channel rather than an analysis of a single modulation. However, the applied modulation can be used to model basic characteristics and estimate the worst case conditions.

12

The digital modulations are divided into phase and frequency modulations. Some of the advanced types have also amplitude shifts to improve the spectral efficiency. The shape of the spectrum and amplitude characteristics must be taken into account in the analog design. The modulation can contain amplitude-modulated (AM) term even though the detection is not based on the amplitude shifts. Also, the angle of the smallest phase shift defines accuracy requirements to some components. The modulation can transmit one or more bits at the same time. The simultaneous bits form a symbol. Most of the modern cellular systems have two bits in one symbol, which is a compromise between the spectral efficiency and accuracy requirements. In that case, the capacity in the radio channel is doubled compared to the one bit case. The quadrature modulator and two constellation diagrams are shown in Figure 2.5. The constellation describes the location of the symbols i.e. bit pairs with respect to the amplitude and phase shifts. The in-phase (I) and quadrature-phase (Q) bits are distinguished with a 90 angle at RF. If the symbols are organized in the way that only I- or Q-bit can change at a time, the constellation never crosses the origin and amplitude is almost constant. Hence, the amplitude-modulated term is very small in the modulation with a constant envelope. The two forbidden shifts in the constellation decrease the spectral efficiency or at least complicate the channel coding. A quadrature modulation with a variable envelope allows all bit transitions at the cost of a relatively large AM-term. If the absolute phase of the constellation must be known in the receiver, the system has coherent detection. However, in the case of oversampling, the clock recovery can be done digitally, and a non-coherent analog part of the receiver is possible. Before the modulator the bits are filtered to smooth the bit transitions. Without the pulse filtering the spectrum of the modulation has the shape of a sinc-function with relatively high side lobes. The pulse shaping filter removes the side lobes, which would otherwise disturb weak adjacent channels. It has also effect on the AM-term and on the intersymbol interference (ISI), which will be discussed later in this chapter.

13

2.3.1

Binary Phase Shift Keying (BPSK)

In the digital phase modulations the phase angle of the carrier changes according to the transmitted symbol. BPSK is the simplest form of the phase modulation. The symbol has only one bit, which rotates the phase by 180 when the input changes. The BPSK signal can be generated in a mixer when the data is multiplied with the square wave at the carrier frequency as in Figure 2.6. The constellation crosses always the origin when the data changes. This means a large AM-component in the modulation and sharp transitions, which produce a wide spectrum relative to the bit rate. For a non-return-to-zero (NRZ) data, the input changes randomly between the two logic levels. The random fashion in the signal means that instead of discrete lines as is the case with periodical signals, the spectrum smoothly follows the sinc-shape. The power spectral density of the NRZ baseband signal is given as [2]

where A is the amplitude of the signal and the bit period. The bit period is inversely proportional to the bit rate At the carrier frequency the power spectral density is

where is the carrier frequency. Only the fundamental mixing product is included in the equation. The other replicas will be filtered out in the transmitter. The power spectral density of an unfiltered BPSK signal is presented in Figure 2.7.

14

2.3.2

Quadrature Phase Shift Keying (QPSK)

In the QPSK, two bits are modulated to the same carrier simultaneously as presented in Figure 2.5. The data rate per symbol is doubled, and therefore the QPSK spectrum is condensed to half of the BPSK when the same amount of data is transmitted as seen in Figure 2.8. All transitions in the constellation are possible. Hence, the envelope is not constant, but the AM-component compared to the BPSK is much smaller, because the 90 phase shifts produce less amplitude distortion than 180 transitions.

The performance of the modulation is evaluated with the probability of an error in the detection. The required energy per bit versus the noise power spectral density is compared to the probability of a bit error The characteristic curves can be plotted for different modulations based on the statistical analysis. It is possible to estimate the effects of the different unwanted

15

properties when they are compared to the ideal curve. The is actually the same both for BPSK and QPSK modulations. The simulated curve is given in Figure 2.9. In wireless communications the required bit error rate (BER) for speech transmission is typically i.e. one error in one thousand transmitted bits. In that case the must be about 6.7 dB for the QPSK. However, that performance is not sufficient for the data transmission, where the BER must be in the order of in wireless connections. The BER is actually defined after decoding of the transmission. The channel coding has effect on the required For example, in WCDMA systems different coding methods will be used for speech and data transmissions. As described later, the coding can be estimated as a gain parameter like the processing gain when analog performance is calculated, and is useful also when certain parameters in analog implementations are simulated. Unfortunately, in continuous-time systems the BER simulations are heavy and time consuming, and therefore simplified behavioral models must be often used. In analog circuit design instead of the the signal-to-noise ratio (SNR) is a practical measure when performance is estimated. The relation between these two is given in

where S/N is the signal-to-noise ratio, is the effective noise bandwidth of the receiver, and is the bit rate of the data. Theoretically, is equal to SNR when noise bandwidth is the same as the data rate. Although the noise bandwidth is often somehow wider than the bit rate in the implementation, it is an appropriate estimate for the hand calculations, which can be confirmed with more accurate system simulations.

The pulse shaping filter removes most of the energy from the side lobes of the QPSK modulation in practical systems to minimize the channel bandwidths and distances between adjacent channels. Simulated examples of unfiltered and filtered QPSK spectrum are given in Figure 2.10. Except of improving the spectral efficiency, the filter smooth out sharp transitions in the time domain, which increases amplitude variations of the signal envelope [4]. The limiting amplifiers, which are desired due to their better efficiency as power amplifiers, tend to reduce the amplitude variations and hence destroy the band limitation. This is called spectral

16

regrowth. Therefore a linear power amplifier is typically needed in the systems with variable envelopes. On the other hand, the small AM content is beneficial in some receiver architectures. The spectral efficiency of a PSK modulation can be increased when the unit circle is divided into more than four possible sections. The angle between constellation points reduces, and hence a better phase accuracy is required. 8-PSK and higher order multiple phase shift keying (MPSK) modulations require theoretically larger for a certain than BPSK and QPSK.

2.3.3

Frequency Shift Keying (FSK)

Instead of abrupt changes between fixed phase angles, the bits can be coded as linear phase shifts. Because frequency is the time derivative of the phase, the linear change in the phase means a constant frequency. Hence, the methods based on that principle are called digital frequency modulations. In the simplest form of FSK i.e. binary FSK (BFSK or 2-FSK), the 1 and 0 bits have their designated continuous phase shifts, which modulate the carrier frequency. When the value of the bit changes, the sign of the phase variation is inverted. At the output of the modulator this can be seen as a change in the carrier frequency. However, the phase shift at the carrier is smooth and the amplitude does not change. Hence, the envelope of an FSK modulation is constant. If a symbol includes more than one bit, each symbol has a designated frequency around the carrier. The frequency spurs occur at the modulation frequencies around the carrier. In addition to a constant envelope, the small power spectral density around the carrier frequency compared to the spurs is of importance in the design of a FSK receiver. Frequency shift keying is the digital counterpart of the analog frequency modulation (FM). The difference is that the input of the modulator is binary data instead of analog information. The BFSK is used for example in paging systems, but its efficiency is not sufficient for the highperformance cellular communications.

17

2.3.4

Gaussian-Filtered Minimum Shift Keying (GMSK)

The minimum shift keying modulations are actually hybrids of phase and frequency modulations. They do not have narrow frequency spurs at the spectrum or rapid changes in phase. The carrier of a MSK signal changes phase gradually by during one bit period. The phase shift is linear and advances by 90 if the bit is 1. When the bit is 0, the phase returns back by the same amount. The 90 phase shift is organized in the modulator by delaying the Q-data by a half symbol period compared to the I-data. Hence, the I- and Q-bits are never changing simultaneously, and the modulation has a constant envelope. Compared to QPSK, the MSK has a wider output spectrum for the same data rate. To limit the spectrum without destroying the good time domain response, a Gaussian filter can be adopted for pulse shaping. A reasonable Gaussian filter does not have the best possible stop band attenuation, but the filtered signal is not very susceptible to spectral regrowth or intersymbol interference either. Due to the compromising properties, the Gaussian-filtered Minimum Shift Keying (GMSK) is used in GSM.

2.3.5

Quadrature Amplitude Modulation (QAM)

To increase the spectral efficiency, the modulations with more than two bits per symbol can be used. In PSK and MSK modulations, the phase differences at the unit circle become smaller, which increases the susceptibility to errors due to noise and distortion. A hybrid of phase and amplitude modulations is an alternative method. The quadrature amplitude modulations divide the constellation points evenly, and every transition is possible. Hence, they are very efficient. The constellation for a 16-QAM modulation, which carries 4 bits in a symbol, is shown in Figure 2.11. QPSK is actually the same as 4-QAM. The complexity and accuracy requirements of the hardware limit the use of QAM, and if the distance between adjacent points is constant, the transmission power of the higher-order QAM modulations is larger. Hence, the spectral efficiency trades off with the power. In CDMA communications, each radio channel contains non-equal powers at different phases from various transmitters. Hence, the received information behaves more like multi-symbol QAM rather than a QPSK signal before the despreading.

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2.3.6

DS-CDMA QPSK Transmitter

A block diagram of the QPSK direct conversion transmitter for direct sequence spread spectrum communications is given in Figure 2.12. The input data is split into parallel branches. Both Iand Q-branches have different spreading code sequences. This is a very simplified version of the actual CDMA communications systems. However, it is a sufficient model when the analog performance of the receiver is estimated. Because the interest is in the receiver implementations, the transmitter performance is assumed ideal including a linear power amplifier. Figure 2.12 does not indicate the border between analog and digital signal processing. Typically, the pulse shaping filter implementation is digital, which requires an analog postfiltering after the DA-conversion to remove the digital replicas at the harmonics of the clock frequency. Alternatively, the upconversion of the transmitted signal can be performed in several steps or the signal can be translated before the D/A conversion directly to some intermediate frequency with a direct digital synthesizer (DDS). Some parameters concerning the modulation and pulse shaping will be discussed later.

2.4

Design Parameters for Radio Receivers

The function of a radio receiver is to detect the desired signal among noise and other sources of electromagnetic radiation. Here, the discussion will be limited inside any specific communications system. It is assumed that the preselection filter removes the power outside the system band completely. This assumption is necessary to restrict the environment. It is also valid if the known large out-of-band interferers are considered separately. In the tranceivers, the parasitic coupling of the transmitted power to the receiver input, which lies relatively close to the reception band, is one of the most harmful sources of unwanted power. It must be remembered that within one system there are typically more than one operator controlling the traffic. Therefore strict rules must be obeyed to maximize the traffic at the system band. Typically, the specifications of different communications systems give fixed tests to characterize the functionality of the receiver at different conditions. The basic parameters of the receiver can be calculated or simulated straightforwardly giving the block specifications for the circuit designer. The intention of this section is to characterize different nonidealities at a more general level with respect to the system behavior for two reasons. First, the final specifications

19

for the third generation cellular systems are still under negotiations, and the prototype design is based on a rough frame of some basic properties. Second, traditionally the interferers are located at different radio channels, but in the CDMA communications the other in-band traffic channels have also effect on the design of the analog radio part. The numerical examples in this section are based on the measured performance of the WCDMA prototype receivers, which will be described later in detail. Depending on the distance to the transmitter and conditions at the radio path, the power of the desired channel varies at the input of the receiver. The ratio between the highest and the smallest possible input power can be in the order of 100 dB. The total dynamic range of the receiver can be defined as described in Figure 2.13. However, as large variations in power levels as that are not allowed instantaneously. The instantaneous dynamic range describes the worst case conditions at a certain moment. Typically, the instantaneous dynamic range is specified close to the sensitivity level of the receiver, but occasionally there are specifications for higher input power levels as well. There are several characteristics, which complicate general analysis. First, the instantaneous dynamic range does not depend only on the ratio of the largest possible interferer to the desired channel but on the several different parameters which concern filtering and linearity. Besides that different radio architectures have different limitations. Second, the instantaneous dynamic range is hardly the same at the different power levels of the desired channel in cellular systems. For example when the mobile terminal is far from the base station, there can be much stronger signals from other base stations. On the other hand, the own base station can transmit to another distant terminal with much higher power when operating close to it. Third, at low power levels noise and other channels limit together the dynamic range while at higher power levels the unwanted channels produce much stronger interferers. Hence, the dynamic range of the receiver is a combination of controllable parameters and unavoidable characteristics of the system, which vary as a function of time. For example, the total dynamic range is typically optimized with an adjustable gain in the receiver. Then, the instantaneous dynamic range is defined for short time periods, which are determined by the speed and efficiency of the system gain control.

2.4.1

Sensitivity

Sensitivity is the basic parameter in the radio design. It defines the minimum signal level, which can be detected, when there are not any interferers present and the performance is limited by the noise. The total noise power is a combination of the thermal noise within the channel bandwidth

20

and the internal noise of the receiver. The noise factor of the receiver defines the ratio of the internal noise to the thermal noise at the input.

Here, and are the signal-to-noise ratios at the input and output of the receiver, respectively. G is the total gain of the receiver and the internal noise of the receiver referred to the input. The noise factor in decibels is called the noise figure (NF). The thermal noise at the input is

where k is the Boltzmans constant T is the temperature in Kelvins, and is the noise bandwidth of the channel selection filter. At the room temperature of 290 K, the thermal noise in decibels is

In the receiver design, the conditions at the receiver input define the overall system performance. The internal partitioning is only a method to meet these requirements. Therefore it is practical to refer all parameters to the input. It can be seen from Equation (2.6) that the input referred noise floor can be given in decibels as

In digital communications systems, the Minimum Detectable Signal (MDS) i.e. the sensitivity of the receiver is the smallest possible signal, which has a certain bit error rate (BER) in the presence of noise. For example in QPSK, the typical BER specification of is achieved with of 6.7 dB as shown earlier in Figure 2.9. can be approximated equal to SNR, which is often called the carrier-to-noise ratio (C/N) in communications. Hence, the minimum SNR depends strongly on the required BER and the used modulation. The minimum detectable signal can be given in decibels as

where is the minimum signal-to-noise ratio for a certain BER. The parameter describes the improvement of the system performance due to the digital signal processing (DSP) methods like convolutional coding or interleaving. Also the processing gain in the CDMA systems is included in the The simplified description of the DSP functions is shown in Figure 2.14. Hence, the improvement of the DSP can be given as

21

where presents all digital functions except of despreading, and is the required implementation margin for digital algorithms. Combining Equations (2.9), (2.10) and (2.11) the sensitivity of the receiver can be given as

The effect of the convolutional coding can be a couple of decibels, for example [6]. Both the coding gain and implementation margin are not related to the analog processing, and it is not possible to estimate the effect without the knowledge of the particular DSP architecture and signaling conditions, which are not discussed here. Therefore they are neglected when the performance is evaluated. In the CDMA systems, the processing gain can be in the order of tens of decibels, and a weak desired signal is buried totally below the noise. It must be taken into account every time in the system calculations and simulations. With other multiple access methods the processing gain is always unity. Figure 2.15 describes the sensitivity in two different cases. The input signal is presented in the left, the amplified output signal in the middle, and finally the input referred performance of the receiver in the right.

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The noise contribution of different blocks to the total noise factor of the receiver is given in the Friis formula [7]:

where are the noise factors of the successive blocks from the front-end of the receiver, and are their power gains. Because the noise contribution of each block is divided by the preceding gain when referred to input, the noise figure requirements are relaxed in the backend of the chain. The noise performance must be considered typically only close to the sensitivity level. In principle, it is possible to decrease the gain and simultaneously increase the noise figure in the front-end when the input power rises. However, such situations should be avoided in the radio system design, because other parameters dominate the performance, and the optimized noise figure does not necessarily give significant advantage in the power consumption or overall performance. The Friis formula is defined for the available signal and noise powers. However, in the integrated circuit design the power-matched interfaces are often not necessary. They are practically needed only in the external connections. For example, the interfaces to the off-chip filters, which require certain characteristic input and output impedances to maintain the shape of the transfer function, must be matched carefully. Instead, the distances between the on-chip blocks are so short at the 1-2 GHz frequency range compared to the wavelength that the matching is not necessary and the wires can be modeled with lumped elements. Also, the integrated filters can be designed to an appropriate impedance level. The signal is typically transferred in voltage mode, and in the ideal case the zero impedance source drives directly infinite impedance. Therefore, the conversion gains and noise levels should be defined with voltages and impedance levels rather than power throughout the receiver. The cascaded stages of the receiver with arbitrary input and output impedances are shown in Figure 2.16. In the following analysis, it must be taken into account that it is only valid when the noise components follow the gain behavior if the impedance levels are changed. Especially, the noise matching in the RF circuits limits the validity of the analysis to the impedance levels, which are close to the point where the noise is defined. Therefore, the noise of each individual block should be defined with the source impedance, which corresponds to the output of the preceding stage. However, if the assumption is valid, the loss in the interface is almost insignificant in this approximation.

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The maximum voltage gain of each stage is given to the open load as

where and are the input and output voltages of the mth stage, respectively. It is noted that the voltage gain is equal to the square root of the available power gain, if the both interfaces are matched to the same characteristic impedance. If the input and output levels are different but still matched the square of the voltage gain must be multiplied by to get the corresponding power gain. In the radio receiver, the circuits in the back-end of the receiver have typically higher input impedances to reduce the current drive to the load. Therefore, the power gain is much smaller than the voltage gain, which actually defines the performance. It should be also noticed that the impedance values are real and independent of the frequency in the simplified notation. Especially in RF design, the amount of mismatch at the frequency of interest should be defined more accurately with reflection coefficient or scattering parameters, and transform the scalar value to impedance mismatch given below. The interfaces between the stages degrade the maximum voltage gain according to

where and are the output and input impedances of the cascaded stages. The noise factor of an individual stage can be calculated to the open load from Equation (2.6) as:

where and are the total signal and noise voltages at the output, and are the signal source and the noise from the source resistance, and is the internal noise of the block referred to input. If both the input and output are matched, Equation (2.16) is equal to the corresponding noise factor using power quantities. The last expression in Equation (2.16) is practical in the simulations because the total noise power and voltage gain from the source to the output can be defined directly. In the matched conditions is 0.5, but it will depend on the impedance mismatch as given in Equation (2.15). However, the mismatch reduces the amplified noise from the source to the output accordingly, but the input referred noise of the block is independent of the mismatch as defined earlier. Therefore Equation (2.16) is valid as long as the impedance mismatch does not change the internal noise properties of the block. Hence, the variations of the voltage gain due to impedance mismatch changes the noise contribution of the following stages to the input, not the noise figure of the stage itself, if the assumptions given above are valid. The noise contribution of the source and each stage in Figure 2.16 are combined at the output as

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Hence, the Equation (2.16) can be rewritten for the receiver chain as

The equation resembles the original Friis formula, but it is valid only if the same source impedance has been used when the noise factor is calculated from the input referred noise voltages at each stage, and the loss due to the finite source impedance when defining noise is close to the situation in the actual receiver i.e. For example, the noise factor is typically defined with a source impedance in the receiver calculations, which is small compared to the typical input impedances of the baseband blocks in the system as desired. Hence, the conversion from power to voltage mode signal processing in the receiver complicates the noise figure calculations to some extent, but the Friis method is still applicable for the definition.

2.4.2

Intersymbol Interference

The maximum capacity of the pulsed communications systems depends fundamentally on the bandwidth of the system according to the Nyquist bandwidth constraint [8]:

where is the bandwidth of the single sideband signal at baseband, and and are the symbol period and rate of the transmitted information, respectively. Below that limit, the energy of the preceding and following pulses or bits inevitably distort the detection of the bit. This crosstalk between the successive bits is called intersymbol interference (ISI). However, the bandpass-modulated radio signals, as QPSK, occupy twice the baseband bandwidth given above. Those are typically called double-sideband (DSB) signals, and the maximum capacity of the transmission is 1 symbol/s/Hz. The Nyquist constraint limits the number of symbols, not the number of bits, at a certain bandwidth. Hence, the use of more than two amplitude levels or different phase angles to present several bits at a time improves the spectral or bandwidth efficiency as discussed earlier. The maximal bandwidth efficiency requires a rectangular shape from the baseband filter i.e. H(f) is 1 when and zero elsewhere. Such a filter has a sinc-type impulse response [2]:

The impulse response describes the energy spread as a function of time. The maximum is reached when and at the multiples of the symbol rate the function crosses the x-axis.

25

Hence, the ideal moment for detection is at the maximum point, and if the data stream is sampled exactly at the symbol rate, the energy of the other pulses is zero and no crosstalk occurs as shown in Figure 2.17. The first zero is at the symbol period defined by the Nyquist bandwidth constraint.

The ideal brick-wall filter for Nyquist signaling is not realizable. The other problem is the slow damping of the impulse response. A relative steep slope when crossing the x-axis makes the detection sensitive to timing errors. A special class of Nyquist filters can solve the problem with a cost of extra bandwidth. The impulse response of a Nyquist filter is zero at each multiple of the symbol period, which is a necessary and sufficient condition for transmission without ISI. A raised cosine filter meets this criterion, and it is used in many communications systems. The transfer function of a raised cosine filter can be given as

where is the roll-off factor (marked sometimes with r). The roll-off defines the required excess bandwidth for the transmission as seen in Figure 2.18. The minimum channel spacing between two adjacent channels is then

Practically, the spacing is slightly larger to allow feasible requirements for limiting the transmitted power spectrum and for filtering the stronger adjacent channels in the receiver.

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The impulse response of the raised cosine filter is defined in [9]:

The response is plotted in Figure 2.19. The roll-off value zero presents the ideal brick-wall as seen in Figure 2.18. The fundamental trade-off between the time and frequency domains is observed. The fastest damping is achieved with the widest bandwidth. The type of the filter and the roll-off are fundamental system specifications and the actual filter implementation should resemble the contradictory requirements with sufficient accuracy. Some of the trade-offs are discussed and analyzed later. Often, the raised cosine filter is distributed between the transmitter and the receiver. Each unit contains a root raised cosine filter, which transfer function is a square root of the raised cosine response. The impulse response of the root raised cosine filter does not have zeros spaced at the symbol period. At the system level, the signal passes through two filters, which form the desired raised cosine response.

Instead of Nyquist filters, some systems like GSM use Gaussian filtering. Both frequency and impulse responses follow the Gaussian bell-shaped curve, and hence there is no overshoot in the time domain. However, the Gaussian filtering is spectrally less efficient than the raised cosine approach. Another dimension of the signal detection in the communications systems is the concept of the matched filters. The impulse response of a matched filter is a delayed version of the mirror

27

image of the signal [10]. A matched filter optimizes the signal-to-noise ratio at the sampling instant but the maximum SNR does not depend on the shape of the pulse or the occupied bandwidth [4]. The matched filters are related to the optimum detection of the signal, which is not discussed here in detail.

2.4.3

Selectivity

While sensitivity describes the performance in the noisy environment and ISI the crosstalk between consecutive symbols, the selectivity defines the tolerance against other radio transmissions. There are several different sources and methods of disturbance. First, the unwanted power at the nearby channels can not be filtered out because it is located too close to the desired channel. Second, the power can alias to the same frequency with the desired channel due to nonlinearities or sometimes due to the fundamental nature of the particular radio architecture. Third, the large interferer can saturate the gain of the receiver, which prevents the detection of a weak signal. In addition to the previous, the other CDMA channels at the same band and imbalance at the quadrature demodulation must be considered. The given topics will be discussed in separate subsections. The selectivity parameters are typically specified in each individual case for the signal, which is 3 dB above the sensitivity level in the wireless systems. Hence, the interfering power can be equal to the noise power to meet the specification. This assumption is often appropriate, but actually it is valid only if the spectral distribution or other properties of the interferer do not vary the vs. curve.

2.4.3.1

Adjacent Channel

The power at the adjacent channel is filtered out with the channel selection filter. The distance between the adjacent channels, difference in power and the power spectral density of the modulated channels define the specifications for the filter. The adjacent channel power after the filtering can be calculated as

where H(f) is the transfer function of the channel selection filter, S(f) the power spectral density of the modulated channel and the spacing between adjacent channels. The transmitter filtering is included in S(f). The filtering requirement is typically defined with a mask, as shown in Figure 2.20, which covers a larger band than only the adjacent channels. For example, in GSM the neighboring cells never transmit at adjacent radio channels, and therefore the attenuation requirement of the adjacent channel is considerably easier than the other radio channels. However, due to the efficient use of the spectrum the channels are located as close as possible, which leads to a complicated optimization process in the signaling environment of the modern wireless systems. The implementations of the channel selection filters trade off with available technologies, accuracy requirements, and contradictory performance criteria.

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2.4.3.2

Transfer Function of the System

Two theoretical aspects, which define the filtering requirements of the transmission in the communications system, are discussed so far. The system specifications define the filter type and roll-off for the system level filtering in the transmitter and in the receiver, and the level of the adjacent channel power at certain conditions. However, the realization of the given filter with high precision may require excessive amount of hardware especially in the power limited mobile terminals. On the other hand, several other filters and devices, which have band-limiting property, are practically always needed in the system before the detection of the signal in the receiver. Therefore the system transfer function as a combination of different band-limiting blocks is discussed here. The system performance is finally defined for the transmission of certain number of bits at an acceptable bit error rate, and the system transfer function can vary from the ideal response within the BER limitation. Of course, the base station and mobile terminal must meet certain criteria separately because they should be compatible with all different devices operating in the same system. The given discussion is mainly intended to help the optimization of the analog baseband filtering in the receiver treated in the next chapter. The transfer function of the system is drawn at the block level in Figure 2.21, and it can be given as

where the subscripts T and R indicate that the block is located in the transmitter and receiver, respectively. P is the subscript for the pulse shaping filter, D for the duplexer, C for the channel selection filter, and L for the band limitation of the LNA. All transfer functions are assumed to locate at the baseband, which means that if any filtering is performed at an IF or RF frequency, like the duplexing, the actual response must be transformed first to the baseband. The frequency responses of the duplex filters and LNA are assumed to be wide-band compared to the channel bandwidth. In that case, the amplitude and phase responses over one channel can be considered constant with a sufficient accuracy. The worst case estimate for the system simulations can be found from the point where the combined gain of the duplex filters and LNA is at minimum

29

within the system band. Typically, the duplex filters have slight rippling at the passband and steep transition bands especially between the transmission and reception bands. Hence, at least the outermost channels are potential candidates to cause problems. They are also susceptible to the worst in-band phase variations. In the wide-band systems, there are only few channels within the passband of the duplex filter. For example in the UMTS, only 12 channels occupy the 60 MHz band. The assumption of the invariable conditions at the RF within a single traffic channel is not necessarily valid anymore. Except of the last comment, which is not analyzed here in detail, the RF filters can be excluded when the adjacent channel and intersymbol interference are calculated.

The channel selection and pulse shaping are drawn as separate blocks in Figure 2.21. It is assumed that the function of the channel selection filter is to remove the power from all unwanted traffic channels, and the pulse shaping filter, which is typically matched with the transmitter filter, is modifying information at the desired channel. The division is done only to distinguish the two separate tasks of the receiver filter. The channels are practically always so close to each other that the channel selection and pulse shaping must be considered together. It is more appropriate to distribute the filtering between the analog and digital domain due to different characteristics of the signal processing and define the combined transfer function. The topic will be discussed in the next chapter with respect to the number of bits required for the A/D conversion. The filtering functions of a single channel can be performed either at the RF, IF or baseband depending on the receiver architecture. However, the RF filtering is not a feasible solution because a high Q-value channel selection filter with sufficient linearity, tuning range, accuracy and low noise is not realizable with current technologies. The adjacent channel attenuation can be calculated directly from the amplitude response of the system transfer function. It is practical to normalize the total gain of the system to unity in the calculations. The intersymbol interference is much more complicated to estimate at the system level. Earlier in this chapter, the conditions for operation without ISI were defined. The synthesis of an almost ideal filter would be difficult especially if a power efficient structure with a limited number of bits and a relatively slow clock rate is desired. The implementations of the different filters typically trade off with the adjacent channel attenuation and ISI both in the digital and analog domain. There are several methods to define how accurately the implementation should resemble the ideal filtering without producing too much ISI. If a large amount of computing power and the knowledge of the digital back-end of the receiver are available, it is possible to simulate the whole system and define BER as a function of the SNR. The method is very slow if several options should be analyzed, but necessary for the confirmation of the correct operation after the optimization. Also at the research phase, the back-end might not be available, and therefore other methods are required to estimate the deterioration of the performance for different structures. Of course, the filtering simulations can be performed only at the baseband with few blocks. Still the simulation of sufficient number of bits to achieve reliable BER estimates is time consuming.

30

The effect of the ISI can be observed from the eye diagram of the signal. A modulated bit sequence with no additional noise is passed through an ideal system filter to define the optimal behavior. Then the frequency response of the filter is changed or other filtering blocks added to the chain. The signal degradation because of the ISI is seen from the closing eye pattern in the diagram. The cost in the overall performance is calculated at the instants of the optimal detection by comparing the amplitude of the opening to the ideal case. The sensitivity to timing errors increases when the width of the eye reduces. The simulations can be performed in a relatively simple environment, and a smaller number of bits is required than in the case of BER. The method is used for calculating the effect of the highpass filtering in the direct conversion receiver, for example [11]. Group delay is a common specification for analog filters to describe the time domain behavior especially in the pulsed mode communications [12]. The voltage transfer function of the continuous-time analog filters can be given under steady-state conditions as

where is the magnitude and frequency as

the phase. Group delay is defined as a function of

It is a practical quantity for simulations and measurements, because of the easy access to phase data either in the ac simulations or frequency response measurements. Group delay expresses the delay of different frequency components in the system. If the phase changes linearly, delay is constant for all frequencies, which is one characteristic property of an ideal Nyquist filter. Hence, large variations at the group delay increase the susceptibility to ISI. The poles and zeros define the phase changes in the analog filters, and therefore the edges of the passband are critical for the group delay behavior. The different filter prototypes have different group delay characteristics, and the filters with sharp transition bands tend to have the highest peaking. The same is valid also when the order of the filter increases. The problem with the group delay is that it does not give a direct definition for ISI or its deterioration. According to other methods large peaking at the edge might be less severe for the ISI than the small rippling at the passband. Hence, the definition of group delay is usable mainly when optimizing and checking the implementation of a certain filter prototype during the circuit design, or in the comparison of measured data to the simulations. The impulse response was used earlier to describe the optimum detection without ISI when no signal energy of other symbols is obtained at the multiples of the symbol rate. The same approach can be used to estimate the amount of ISI in the circuit implementations. The impulse response of the system transfer function is defined and the square of the difference from zero at each multiple of the symbol rate is summed. The result is compared to the maximum value of the response. Hence, the effect of ISI can be given as

31

where S/ISI is the signal-to-ISI ratio and is the impulse response of the system. The nonideal impulse response is shown in Figure 2.22. It is assumed that the maximum is always when Otherwise, the impulse response should be shifted in time to meet the criteria, because the clock recovery of the receiver detects the optimal sampling instant. To estimate the effect of the analog baseband filtering only the filter itself and the ideal system filter should be included in the transfer function. On the other hand, the optimization of the receiver filtering can be performed using an ideal filter in the transmitter and a combined transfer function of the analog and digital filters in the receiver. The adjacent channel attenuation and the accuracy of the digital filter depend on the number of bits and taps in the implementation and the oversampling ratio, which must be taken into account in the optimization. A corresponding method as described here has been used earlier in the optimization of digital filters with the maximal error [13], and with the rms error [14].

S/ISI describes the ratio of the detected bit energy to the unwanted bits. Actually, the unwanted energy is a sum of previous and successive bits at the moment They can be either 1 or 1 giving a positive or negative impulse. Therefore the rms-value is used in the definition. In the worst case, all impulses sum at and the absolute values instead of their squares should be summed in Equation (2.28). Equation (2.28) can be modified to define the deterioration due to ISI at the optimal sampling moment by comparing the rms-value of the unwanted impulses to the ideal performance as

The result in Equation (2.29) is comparable to the method with the eye diagram, but no bit level simulations are required. The unwanted impulses describe the closing of the eye compared to the optimum. With both methods a sufficient number of samples, either clock periods or unwanted impulses, should be included to achieve reliable results. However, in the impulse response method the summation converges quickly to zero, which restricts the number of terms and makes it easier to define the limits for the calculation.

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So far, a perfect synchronization has been assumed. If the timing error is known, for example the clock jitter at the sampling instants of the A/D converter, Equation (2.28) can be rewritten in the form

where is the jitter of the clock. A similar expression can be written for Equation (2.29) as well. Equation (2.30) may lead to different results in the optimization because with rapidly damping responses the timing requirements are relaxed. Unfortunately, a new parameter i.e. the jitter, which is not related to the filter itself, should be known or evaluated in advance. The equation also assumes a fixed jitter and neglects the statistical properties. Therefore it can be used only for the comparison of different prototypes. All the given definitions for the intersymbol interference of the different filters should be considered as figures of merit, which help the designer to choose an appropriate prototype for the implementation. They should be used only for comparison. Group delay is maybe the easiest but also the least descriptive definition. The S/ISI is illustrative for the radio designer, but somehow misleading. It has a similar definition with the signal-to-noise ratio (SNR). However, a straight comparison to the required SNR value for a certain BER can propose an optimistic result. Hence, ISI should not be treated as a noise parameter even in the simplified analysis. Therefore defined either from the eye diagram or from the impulse response is probably the most accurate description for ISI. Typically, the deterioration of the performance must be almost negligible, and it should be related to the optimum detection of bits at the system level. Some simulated examples of ISI performance will be given in chapter 4.

2.4.3.3

Nonlinearity and Distortion

The nonlinear phenomenon in the radio receivers is connected to the aliasing of the power from unwanted channels to the passband of the system. Before all other signals than the desired traffic channel are attenuated to a sufficiently low level, the linearity of the signal path is critical for the system performance. In that case, only weakly nonlinear structures are allowed in the receiver with a large dynamic range. The manifestation of the nonlinearity is totally different in the transmitter, because only internally controlled signals are processed with smaller instantaneous dynamic range. The characterization of the distortion can be typically limited to second- and third-order products in weakly nonlinear receivers. However, the transmitted power levels are typically so high with simultaneous requirements of power efficiency that a much larger number of harmonics must be modeled and controlled properly. Here, the discussion is focused on the system performance and dynamic range requirements in the receiver based on the common block level parameters. The origin and modeling of the nonlinearity in analog integrated circuits is a very complicated issue from the transistor level to the system performance [15]. Typically, only very simple structures can be calculated in the closed form, and simulations, which are confirmed with measurements, are needed in the circuit level design. Hence, it is important to understand the basic properties of distortion both from the circuit level and system performance points of view.

33

Although the signal path of the received signal should be very linear, at least two fundamentally nonlinear operations are performed in the receivers used in the digital communications. The frequency translation in the mixers, either in one or several stages, and sampling in the continuous- to discrete-time or analog-to-digital conversion are both based on the switching of the signal path. However, the signal should experience a linear operation in the vicinity of the actual translation. The nonlinear characteristics of a memoryless system can be given in power series as

where is the excitation for the output and describe the coefficients of the different orders of nonlinearity. Harmonic distortion is a measure for a single-tone excitation. In frequency selective receivers the concept of harmonic distortion is not a sufficient definition. The components of the harmonic distortion fall rarely at the passband of the filter if the system is properly designed. Instead, the intermodulation components of different excitations will inevitably alias at the passband at certain frequency combinations. Therefore a two-tone excitation

serves the purpose better. The power series presentation gives a useful method to estimate the ratios of different nonlinearities in the system [16]. The frequency components up to third-order intermodulation products are collected to Table 2.3. The potentially detrimental products fall at the passband of the system transfer function. Hence, they are inseparable from the desired channel in the frequency domain, and the total distorting power must be below the signal at least by the minimum required SNR. The formation of different spurious tones is described for the receivers with one and two downconversion stages in Figure 2.23. Only the thick lines are falling at the passband of the channel selection filter because they are close to dc or LO frequency, which converts the signal to baseband. Most of the products in Table 2.3 will be upconverted, and therefore they may cause problems only if they will be mixed with higher harmonics of the LO frequency. Those components are not significant because they will be attenuated due to parasitic effects at high frequencies, and the conversion efficiency is much smaller with a harmonic of LO, which has lower power than the fundamental. As seen from Figure 2.23, the third-order harmonics can fall in the passband of the system at any stage before sufficient filtering of the interferers. On the other hand, the second-order distortion will always produce a harmonic close to baseband when characterizing a relatively narrow system passband at a high radio frequency. The second-order intermodulation product can be filtered out before overlapping with the desired channel if it is far from that frequency. Therefore, the second-order distortion should be taken into account only with certain radio architectures. And as the effect of the third-order intermodulation is quite similar in all architectures, the second-order characteristics are different depending both on the radio architecture and on the signaling in the system. The second-order intermodulation will be discussed later in detail.

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35

The linearity performance in radio receivers is typically specified with the input referred intercept points shown in Figure 2.24. The third- and second-order input intercept points (IIP3 and IIP2) are defined in the two-tone test when operating at the weakly nonlinear region. It means that second- and third-order nonlinearities dominate, and if the input power or amplitude is increased by 1 dB, the second- and third-order products rise 2 and 3 dB, respectively. This is a valid approximation at low signal levels when clearly one nonlinearity dominates. Above a certain signal level, different nonlinearities, which can be either higher order or from different sources, begin to sum or cancel each other. Power amplifiers are typically designed at that region, which is not suitable for receiver operation. IIP3 and IIP2 are defined at the points where the nonlinear product would be equal to the signal level if the components rise like at the weakly nonlinear region. The theoretical intercept points can be defined according to Table 2.3 as

and

where iip3 and iip2 are absolute values. Typically they are given in decibels and the notation with capitals is reserved for that. These hypothetical measures give unambiguous definition for the selectivity against unwanted signals. The power levels of the intermodulation products can be calculated from

36

and

where

is the input power of one tone, the output power, G the power gain, and and the respective powers of the intermodulation products at the output. The corresponding power levels are referred to the input as and and are the differences between the input power and the intermodulation product. All values are given in decibels. The definition needs information only at one signal level, but to ensure the weakly nonlinear conditions several points should be used both in the simulations and measurements.

It is not just a common habit but also practical to refer all signals to the input of the receiver and convert the voltage values to power levels, because the actual signal interface operates in the power matched environment, and the impedance level is typically However, in the design of integrated receivers the input interface might be the only point where the definition makes sense and the rest of the analog signal processing is performed for voltages. As described in the context of noise figure, different impedance levels should be taken into account in the conversion. Later, even the bit patterns of the ADC are sometimes converted to input power levels for the purpose of the complete analysis.

37

The connection between voltage and power values can be given by modifying Equation (2.35) as

where are rms voltages, the voltage gain and and the impedance levels at the input and output, respectively. The impedance levels need not be real values as given here. It is necessary to convert all voltage levels to powers by using the same input impedance as a reference when applying the voltage gain in the calculations. Also, the voltage gain should be defined using real impedance values as earlier with the noise figure. The expression is rewritten for voltages as

The input intercept point of the cascaded stages can be calculated with an equation, which resembles the Friis formula for noise performance as

where and are the input intercept point and power gain of the nth cascaded stage as absolute values. The power gain should be replaced with the square of the voltage gain when necessary. As the first stages dominate noise behavior, IIP3 becomes more critical when the gain in the chain increases. There are two design aspects, which must be taken into account. First, the external passive filters and other structures have almost infinite IIP3 compared to active circuits. Therefore they can be omitted except of the contribution to the cascaded gain. Second, the filtering attenuates the interferers along the chain. Traditionally, all stages after the passive channel selection filter can be neglected, because the unwanted tones are filtered sufficiently. This is not the case with active baseband filters, and when optimizing the filtering functions between the analog and digital domains a signal, which can produce unacceptable intermodulation products even at the input of the ADC, can exist. The spectral selectivity invalidates the use of Equation (2.39) as it. Initially, two specified test frequencies located at

38

some distance from the desired channel should produce an unwanted tone at the passband. They will experience different amplifications in the filter, and the worst case estimate includes the larger value in Equation (2.39) when evaluating the contribution of the following stages. This means that will be replaced with a product of where is gain at passband and is the gain difference of the larger test tone compared to This notation is useful if the transition- or stop-band attenuation is alleviated. Linearity is typically inversely proportional to the power consumption. Therefore trading the linearity with the supply current along the cascaded stages as a function of the reduced dynamic range is a possible optimization approach. It should be presumed that at least approximate transfer functions can be defined for different blocks and that the other properties of the filter are not changing during the optimization. The method can also lead to increased design complexity. At system level, it is practical to define a linearity specification, which is required at the input of the first filter stage, and optimize the filtering as a function of power, linearity, gain and noise separately. This method is used in the design of the WCDMA direct conversion receiver, for example. If necessary the above discussion is valid for the second-order intermodulation as well with certain exceptions. The IIP2 products do not fall directly at the signal band. Instead, they convert down to the baseband. Therefore the cascaded gain of an IIP2 product is different compared to the actual signal path. In differential circuits the prediction of the second-order nonlinearity is difficult, because theoretically the components cancel each other and the performance depends on the symmetry. Finally, the sensitivity to IIP2 depends not only on the total power but also on the modulation, multiple access and other signaling conditions. Hence, the characterization of the IIP2 is much more complicated issue than the third-order effects.

2.4.3.4

Blocking

The gain of the system begin to vary at a certain signal level when nonlinear components at the fundamental frequency have risen to the same order with the output amplitude The 1 dB compression is defined at the point when the gain is dropped by one decibel from the first-order behavior. The input compression point (ICP) is often used for the same meaning. ICP can be given for a single tone as

when the amplitude of the second tone is set to zero in Table 2.3. Comparing the ICP to Equation (2.33) the well-known approximation that ICP is 9.6 dB below the IIP3 is observed. However, the ratio depends only on a single nonlinear term, which is the same in both cases. In practice, several different components and their nonlinearities dominate the behavior, and already by definition iip3 is measured at the signal levels, which are well below the compression. Therefore the given value is only a rule of thumb, and the typical ratio in communication circuits is 5-15 dB. ICP gives an approximate upper range for the highest possible signal, but it does not necessarily prevent the detection of a strong channel itself. That happens only after the internal crossmodulation i.e. spectral regrowth or some other phenomena prevents the demodulation and decoding of the channel. Once again, the main concern should be paid to detection of weak signals in the presence of strong channels. The behavior can be observed with a blocking test, in which the desired weak channel should be detected when a strong signal lies at some offset

39

from the weak channel. In cellular systems, the test is typically defined at several different offsets. The unwanted strong signal can be a sinusoid or carry a modulated channel. Two different mechanisms for signal corruption can be found: desensitization and cross-modulation. In mixed-mode receivers where a sensitive RF front-end is on the same die with the digital signal processing, crosstalk should be considered as a third parameter in the blocking test. This will be discussed later in connection with single-chip receivers. The gain of the signal at given as in the presence of a high blocker, i.e. in Table 2.3, can be

Hence, the performance is violated due to third-order nonlinearity also when a strong signal at any possible frequency compresses the gain. If the signal is located 3 dB above the sensitivity level in the blocking test, the -3 dB compression point is an appropriate measure rather than the -1 dB compression. Another effect, which should be considered, is the desensitization when the low-frequency components are upconverted in RF amplifiers around a high frequency blocking signal due to the second-order nonlinearity [17]. Although the out-of-band signals are filtered before the gain block, the upconversion of the internal low-frequency noise including the flicker noise of an RF amplifier might rise the noise to an unacceptable level. This can be tested with a two-tone measurement when a high-frequency blocking signal and a low-frequency excitation generate a beat at the desired radio channel The both desensitization effects, gain compression and upconverted noise, are illustrated in Figure 2.25.

If another of the two interfering signals in the two-tone test carries a modulation, a part of it can be transferred to the other carrier. The phenomenon is called cross-modulation. The transformation of the modulated channel to the other frequency can be formulated by adding a sinusoidal modulation to the second term in Equation (2.32), as where m is the modulation index [4]. The fundamental frequency term can be rewritten as

40

The last term in Equation (2.42) indicates that the cross-modulation due to the third-order nonlinearity may double the occupied bandwidth of the modulated channel, and therefore it can cause similar effects as spectral regrowth in power amplifiers. The IIP3 test should model the worst case behavior of the third-order nonlinearity for in-band signals. However, if there is a strong out-of-band tone, like power leakage of the power amplifier in simultaneous reception with the transmission, it may cross-modulate with an in-band blocker, which is close to the desired channel. A part of the cross-modulated spectrum is susceptible to spread over the weak desired channel, and hence deteriorate the performance. In some receiver architectures, the cross-modulation requirement may lead to a situation where LNA dominates the IIP3 performance of the front-end rather than the downconversion mixer because the image filter between the two blocks attenuates the out-of-band blocker [18]. Compression and IIP3 depend on the total power level and therefore they can be defined straightforwardly. The specification for the cross-modulation requires again more detailed information on the signaling conditions in the system. Although in most cases the cross-modulation does not dominate the third-order nonlinearity in the receivers, the unexpected behavior might be possible to recognize by studying the interaction of different modulated traffic channels.

2.4.4

Dynamic Range

It is not possible to give a single unique parameter, which defines the dynamic range of the radio receiver as seen from a number of different nonidealities described in this chapter. Maybe the most objective measure is the instantaneous dynamic range close to the sensitivity level of the receiver. This can be given as a spurious-free dynamic range (SFDR) or as a blocking dynamic range (BDR) at the input of the receiver [6]. The former, which is based on the thirdorder intermodulation and noise figure, is the most widely used. The definition omits the role of the gain control as a function of the incoming signal level. Therefore the total dynamic range of the receiver can be much larger. The instantaneous dynamic range for the signals well above the sensitivity level is restricted only due to large interferers but their contribution is worse because of the cubic dependence of the signal level in the IIP3 test. The total dynamic range and the instantaneous dynamic range at large signal levels are discussed in the end of this subsection. It should be noticed that the gain control is significant for the unwanted channels, and hence for the dynamic range, only before the channel selection. After that, the gain control is needed for an appropriate level shift. Therefore we limit the discussion here only to the previous. The weakest possible signal is defined by the sensitivity of the receiver. Sensitivity is determined when only one channel is fed to the receiver. Hence, it is limited due to noise and detection with a matched filter including proper timing, frequency response and ISI. In

41

principle, digital channel coding is required as well. However, the detection is typically assumed ideal in the discussion of the dynamic range. The minimum required SNR to detect bits at certain BER depends on the modulation, not on the properties of the receiver. Also, the changes in the noise level typically dominate the deterioration of the performance rather than nonidealities in a properly designed DSP block. Finally, the optimization of the decoding is an independent task in most cases, and therefore insignificant for analog designers. Hence, the input referred noise defined with the noise figure in Equation (2.9) is appropriate for the analysis. The input referred noise depends on the bandwidth, and therefore the transmitted bit rate should be taken into account when different systems are compared. The spurious-free dynamic range is defined at the point where the third-order intermodulation products are equal with the noise power shown in Figure 2.27. This is actually the same definition, which is typically specified for the system i.e. the signal is 3 dB above the minimum SNR in the two-tone test, because the combined noise and distortion is now 3 dB above the noise floor. It is assumed that the IIP3 limits the dynamic range in the test. The other selectivity parameters, like IIP2, should be checked separately. Another example given in Figure 2.27 is the blocking dynamic range.

SFDR can be calculated directly from Equations (2.35) and (2.9) in decibels as

Similarly BDR is

SFDR rises slower than BDR when the linearity of the receiver is improved. Therefore the spurious-free dynamic range becomes more critical compared to the blocking test when a large dynamic range is required. For example, if the approximately 10-dB theoretical difference between IIP3 and ICP is assumed, a 60 dB SFDR corresponds BDR of 80 dB. It means that a single blocker can be 20 dB higher than two tones generating IIP3. For a 80 dB SFDR, the difference is already 30 dB. Hence, the direct comparison between different definitions does not give much insight on the system performance. However, they can be used to estimate what is a
42

realistic ratio of signal levels in the two-tone and blocking tests. If not specified otherwise, the dynamic range refers always to SFDR hereafter. The concept of the dynamic range in the radio receivers has significance only after the bandwidth, modulation, multiple access and a certain reference level, which is typically the sensitivity, are known. Sensitivity should be based on a realistic noise figure specification. Two plots are given in Figure 2.28 to visualize the different constraints. In Figure 2.28(a), the IIP3 requirement is given for two different noise figures in a narrow-band system, and separately for a wide-band system. The effect of the system bandwidth is described in Figure 2.28(b). In principle, wide-band systems require a significantly higher IIP3, but the claim neglects the difference in capacity according to the Nyquist bandwidth limitation and the fact that the wideband systems are typically based on CDMA. Hence, the processing gain boosts the signal, which is buried in noise. Therefore, the actual dynamic range is improved by the amount of processing gain compared to the definition of SFDR.

For the reasons given above, SFDR is not a very useful parameter to compare different receivers operating in different systems. The SFDR performance should be normalized to a fixed bandwidth for the fair comparison because the inclusion of the bandwidth in the definition of SFDR misinterprets the ratio of the circuit oriented parameters NF and IIP3. Also, when specifying the limits for a system, the characteristic differences between wide- and narrow-band systems must be taken into account. A feasible approach is to estimate the realistic performance for the implementation, and limit the allowed power levels within the optimal limits. If we assume that NF is in the limits of 5-10 dB and IIP3 between 20 and 10 dBm, which are typical numbers for current IC implementations, the SFDR is according to Equation (2.43) 6171 dB for 200 kHz and 52-62 for 4 MHz bandwidths, respectively. The specification of the power levels at a system requires knowledge both of the system characteristics and available technologies. The specifications are based on exact power levels at certain conditions, which define the required circuit performance. Hence, the dynamic range is only a secondary parameter, which reflects the fundamental or natural limits of the system capacity rather than gives a universal method to compare receiver implementations in different systems. The required dynamic range of different blocks in the receiver can be defined with the preceding gain and total NF and IIP3 of the receiver. The contribution of different blocks to NF and IIP3 are given as a function of the preceding gain in Figure 2.29. The total NF and IIP3 are summed from different terms in Equations (2.13) and (2.39). Therefore the partial contributions

43

are also given at the levels of 50 %, 10 %, and 1 % of the total value. The total NF and IIP3 of the receiver are assumed to be 5 dB and 10 dBm, respectively. The gain in the case of IIP3 is not necessarily the same as for the signal, because the high intermodulation products must be attenuated before unreasonable linearity requirements. Figure 2.29 is a map for the receiver design rather than a behavioral model of the signal path as a function of gain.

By far, only the instantaneous dynamic range close to the sensitivity level has been covered. The realistic dynamic range is about 60-70 dB for current technologies. This meets the typical specifications of the current systems. However, the required total dynamic range is typically larger than that. This can be achieved with a proper gain control. The definition of the spuriousfree dynamic range is not valid anymore because the SNR is larger than the minimum required value for the modulation. If it is assumed that the intermodulation product has approximately the same properties as noise in the detector, the signal-to-noise+distortion ratio (SNDR) can be used to estimate the required IIP3 for a certain dynamic range. The assumption is simplifying, because the modulated channel including digital information has not similar statistical properties as white noise. However, the first-order estimate gives quickly an initial value for more accurate system simulations. The definitions of SFDR and SNDR, which are given here, are not directly comparable to corresponding terms used in connection with A/D converters because of different methods to determine the measures. However, in both cases they indicate the dynamic range, and later indirect comparison will be performed when the receiver dynamic range is referred to the required number of bits.

44

The problem at high signal levels is the cubic ratio between the third-order intermodulation product and the interfering tone when the power level is increased. Therefore if the same instantaneous dynamic range is required at high signal levels, IIP3 must be increased as well. This can be formulated by keeping the minimum required SNR constant when the power level is increased as given in a linear scale as

where is the power of the minimum detectable signal and the relative input power compared to MDS. The factor two is added because by the definition of the SFDR, the reference signal is 3 dB above the sensitivity level because the third-order product is equal with the noise power. When this is applied to Equation (2.35) IIP3 can be given in decibels as

where means the required IIP3 at high signal levels. as a function of is given in Figure 2.30. There is only slight bending due to noise when operating close to the sensitivity level. It is evident that the dynamic range is dominated purely by the nonlinearities at high signal levels. However, the linearity requirements become rapidly unreasonable when the power level is increased. Therefore in the front-end of a receiver a large gain step is often available to achieve a better linearity in the reception and lower signal levels in the rest of the receiver. Then the noise figure should be estimated again, because the noise figure is hardly constant after the gain control close to the input of the receiver. If it is acceptable to reduce the instantaneous dynamic range at high signal levels, the SFDR term can be reduced in Equation (2.46). The relaxed dynamic range is multiplied with factor 1.5 when specifying IIP3.

45

In the case of a constant dynamic range requirement at all signal levels, the total dynamic range is the sum of SFDR and This is typically not the manner how the existing systems are specified. In some cases intermodulation tests have been defined at different power levels, which is an indication that an improved linearity is required at high signal levels. The purpose of the linearity characterization at high signal levels was to highlight the problems, which exist outside the range, which is often considered as the only significant limitation for performance, i.e. close to sensitivity. The optimization of the total dynamic range should not neglect that fact.

2.4.5

Gain and Interface to Digital Signal Processing

The maximum required analog amplification depends simply on the desired level in the detector and the smallest possible input power of the receiver. In digital communications systems, the signal level in the detector is practically the appropriate level either at the input of the comparator or multi-bit A/D converter. First, it is assumed that all other signals except of the desired channel and the in-band noise are filtered out in the analog domain. Also, the signal should be sufficiently above the noise floor when the bits are determined. This means that the system does not use spread-spectrum techniques or the despreading is performed in the analog domain, which is normally not the case at least in direct sequence. The typical input levels of the comparators with current technologies are in the range of which mean 2 to +10 dBm power levels in the environment. For example, a system with a -100-dBm sensitivity requires a 98-110 dB maximum analog gain. A certain amount of clipping is acceptable, and even beneficial, at the comparator input to improve the tolerance against offsets, which may vary the optimal 50 % duty cycle. A larger gain than given above also ensures that the bit stream is a rail-to-rail signal in the single-bit A/D conversion. However, some received signal strength indicator (RSSI) and analog gain control mechanism is often needed to optimize the dynamic range before the channel selection. In the one-bit case, the difference between the strongest and weakest received signal gives an estimate for the gain control range. The use of a multi-bit A/D converter changes the analog gain specification of the receiver. An ADC can be utilized to improve the dynamic range in the digital domain when the channel

46

selection or a part of it is performed digitally, or to relax the analog gain control requirements. Of course, this increases the complexity and power consumption of digital circuits, but with modern digital technologies it may be acceptable to some extent. The slow evolution from analog wireless communications to completely digital structures is still on the way. Even more functions can be performed digitally than 5 or 10 years ago, but optimization due to different characteristics of analog and digital signal processing is a complicated challenge. To investigate the effect of the number of bits in the ADC on the gain specification, it can be assumed that the signal at the level of the least significant bit (LSB) provides the same performance as the maximum input of the comparator in the one-bit case. Also the maximum ADC input, is similar to the comparator i.e. Hence, the voltage of the LSB can be given as

where m is the number of bits. Hence, the voltage gain of the receiver can be reduced approximately by So far, the effect of the quantization noise is neglected. If the quantization noise is assumed to have uniform distribution between which is independent of the input signal, the quantization noise can be given as [19]

This expression is not valid generally, and as an approximation inaccurate at a small number of bits. However, it is used here for a simple first-order evaluation, and the results match well with some earlier reported simulations for DS-CDMA, which are discussed in the last subsection of this chapter. If the input signal is a sinusoid with as a peak-to-peak voltage, the SNR due to quantization can be written as

which can be given with a well-known expression in decibels as

Next, the quantization noise and noise at the input of the ADC are combined assuming that they are uncorrelated. The SNR at the output can be given as

where and are the signal and noise at the input of the ADC, respectively. Again, this is an approximation, and the direct summation of different types of noise is not statistically accurate. Still the following results give reasonable numbers and simple expressions to understand the requirements in the system design of the receiver. They should be confirmed with careful system simulations. Quantization noise depends always on the full-scale voltage and number of bits, but the desired channel is at that level neither in CDMA systems with

47

digital despreading nor when the channel selection is performed digitally. Therefore the input level of the desired channel can be given as

where is the ratio between the full-scale input and the desired channel. It corresponds the dynamic range when the amplitude of the strongest unwanted channel is adjusted to the fullscale. Equation (2.51) can be rewritten as

At minimum, is actually the same as the when the minimum detectable signal was defined earlier. Hence, the implementation margin, due to quantization is the difference between the input and output SNR of the ADC. SNR at the output and implementation margin are given as a function of the bits for two different input SNRs of 6.7 dB and 11 dB when dB in Figure 2.31. They correspond the required SNR for bit error rates of and in the QPSK modulation.

The quantization noise correlates with the incoming signal with a small number of bits. A correction factor is defined in [20] to estimate the effect as

48

where the correction factor achieves values between 0 and 1. In the single-bit case, for a sinusoidal input. More than a single-bit conversion, and the random nature and different statistical properties of the input signal prevent the accurate calculation of Hence, system level simulations are required. However, the can be rewritten for simplified analysis as

The result is applied to Equation (2.53) and the effect is shown for with dashed lines in Figure 2.31. Even a larger implementation margin is required than earlier at a small number of bits. The output SNR is given for different dynamic ranges without the correction factor in Figure 2.32. The curves follow exactly the earlier claim that the dynamic range increases by when the number of bits is increased. Hence, the gain of the analog part can be reduced by the same amount because of the increased dynamic range. What is then the point of the previous analysis? In the case of a one-bit detection clipping was considered to improve the performance because of the better precision in the duty cycle. Also, if the preceding gain is larger than necessary the signal is clipped but the quantization noise is smaller compared to the input noise, and it is possible to operate with a smaller number of bits than predicted in Figure 2.31. On the other hand, if other channels are present clipping is probably not acceptable. Otherwise, two unwanted strong channels may produce an intermodulation product at the frequency of the desired channel. Although the total harmonic distortion (THD) of the ADC meets the requirement of the dynamic range for a certain number of bits, the unacceptable intermodulation product can not be separated from the desired channel when the signal is filtered and decimated in the digital domain. Therefore the linearity requirement in the A/D conversion does not allow overshoot from the which means about 2-4 extra bits. As seen from Figure 2.32 the instantaneous dynamic range of 60 dB requires 12-14 bits for the conversion in the case when a comparator might be a possible converter if the channel selection is performed in the analog domain. It means that the should be 74-86 dB, which is much higher than the dynamic range of the input signals.

49

The above discussion is actually not valid generally because the effect of oversampling is neglected. Except of the CDMA systems, each traffic channel has a separate band for the operation during the transmission. When several channels or the whole system band is sampled to the digital domain, the desired band occupies only a part of it. Therefore the desired channel and also the quantization noise is oversampled although the total input bandwidth ranges up to the Nyquist frequency. This can be understood by averaging of the quantization noise when the signal is decimated after the appropriate filtering. Each sample contains correlated information of the desired channel, which has an effect on the digital code in the ADC. The quantization noise is averaged by the amount of oversampling when several samples are summed to one symbol after the filtering. The same is valid also when only the desired channel is converted to digital. The oversampling in the Nyquist rate converters can be utilized to reduce the quantization noise contribution compared to the incoming signal, and hence diminish the implementation margin of digital circuitry significantly. The effect of oversampling to can be given as

where is the Nyquist rate or frequency of the ADC, the sampling frequency, and the bandwidth of the desired channel at the baseband, which is half of the RF bandwidth. The oversampling ratio is or but it should not be directly compared to oversampling in because the quantization noise is not shaped in Nyquist rate converters. The effect of oversampling is included in Equation (2.53) and the results are given for various oversampling ratios at two different dynamic ranges in Figure 2.33. The correction factor has not been included in the plot. Equation (2.56) and Figure 2.33 indicate that oversampling by factor of 4 corresponds one extra bit in the converter. According to Figure 2.33 oversampling is an efficient technique in the Nyquist-rate converters with small oversampling ratios but the benefit is vanished at larger ratios because of the relationship to the power of 4. The 60-dB dynamic range still requires 10-12 bits at the oversampling ratio of 16. A reasonable compromise is that an analog filter does not perform a complete channel selection but reduces significantly the required total dynamic range. The sensitivity to the third- and second-order intermodulation also reduces when the dynamic range between input tones is smaller. The 30-dB curve in Figure 2.32 is an example of it. The cost of using multi-bit ADCs is the fact that the power consumption increases quickly to unreasonable values especially for mobile terminals when the number of bits is increased. The evolution of IC technologies allows faster operation with a smaller current consumption, but also reduces the supply voltages, which makes the signal range even smaller than earlier. In chapter 4, some examples of the reported multi-bit ADCs will be given for comparison. Another limitation is the increased clock rate when the channel selection is performed digitally. Two ultimate alternatives are the conversion of a single channel or the whole system band at the baseband. In GSM, the sampling rates for a Nyquist rate converter are 200 kS/s for a single channel and at least 25 MS/s for the whole band. The 25 MS/s sampling rate corresponds an oversampling factor of 125. The frequency allocations for GSM have been increased and therefore at some bands the latter number can be even higher. In WCDMA, the corresponding numbers are 5 MS/s and 60 MS/s, respectively.

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The above discussion gives a very simplified analysis on the required dynamic range of an A/D converter. All signals are sinusoids in the mathematical representations, and clipping or modulated channels are not taken into account in the calculations. Also, only Nyquist rate converters are considered. However, the given numbers form a base for the system simulations. The instantaneous dynamic range is discussed so far, which means that the analog gain control should detect the power level and adjust the gain precisely for the converter. Otherwise, some extra bits should be reserved at least for quick changes in power levels. The nonidealities of the ADC implementations have also been omitted. The standard linearity tests of the ADCs, which confirm the sufficient operation for a certain number of bits, are not necessarily the only linearity tests needed in the systems sampling complete system bands. A similar two-tone test than for analog blocks may give a more realistic value for the attainable dynamic range, and ranges for the acceptable clipping in different conditions, for example.

2.4.6

Image Rejection Ratio

An image rejection mechanism is needed in the most radio systems. For bandpass signals, the image or mirror frequency is located on the opposite side of the LO either at RF or any possible IF. Image frequency is mapped to a negative frequency in the signal downconversion, and it will alias into the same band with the desired channel if not removed properly. In downconversion to the baseband, the concept of signal image relates more likely to the demodulation of the symbol, which includes phase-dependent information. The different receiver architectures are actually defined based on the different ways to cancel the image. The image can be removed either by filtering or using appropriate phase shifts. For historical reasons, the origin of the image rejection concept comes from the modulation and demodulation of single-sideband (SSB) signals. Here, the focus is on the requirements for different receiver architectures and demodulation of digitally modulated signals. In digitally modulated channels, which carry a phase dependent component like QPSK or GMSK, the bits

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from a symbol must be detected with appropriate phase shifts. Therefore, the signal must be divided into quadrature branches at the latest when converting the signal down to baseband. With that perspective, they are considered SSB modulations although the energy of the bandpass signal is located at both sides of the final center frequency at dc. The in-phase (I) and quadrature (Q) components containing different bit streams are unwanted images to each other in the demodulator. The available technologies and the frequency where either the filtering or phase shifting is performed are the practical constraints for implementations. The image rejection by filtering refers to the superheterodyne principle. The image is removed with a bandpass filter before the downconversion to avoid the spectral overlap as shown in Figure 2.34. The image rejection ratio (IRR) is simply the difference of the passband and stopband amplifications in decibels. Especially, the stopband attenuation varies at different frequencies, and the worst-case estimate should be used in the system characterization. If the downconversion to baseband is done in several stages, the image frequency changes at each IF and a separate image rejection filter is needed in front of every mixer. On the other hand, at any stage the image cancellation can be changed to phase shifting techniques having different constraints. As described above, filtering techniques are not generally suitable for demodulation after the conversion to baseband, and quadrature downconversion should be done before the detection.

Two alternative methods, widely called as image-reject receivers, to remove the unwanted image channel without filtering have been developed. Both use quadrature LO signals in the first downconversion, but they should not be mixed up with a quadrature demodulator. The demodulator suffers from similar phase and amplitude errors, but the restrictions are different. They will be discussed in the end of this subsection. The phasing method, which is also known as Hartley receiver or architecture according to its inventor, is shown in Figure 2.35 [21]. The signals at the upper sideband i.e. above the LO are added at the summed output where as the image at the lower sideband cancels itself. If both sidebands are of interest the subtraction instead of summation recovers the lower sideband and cancels the upper one.

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The perfect cancellation of the unwanted sideband is achieved only if the amplification is equal in both branches, and all phase shifts are ideal. The image rejection ratio for both sidebands can be given as [22]

where and are the output powers of the image and wanted sidebands, respectively. The real factors A and B describe the proportional gains of two branches. The angle is the error from the 90 shift in the quadrature LOs, and is the phase error after the downconversion. The upper and lower signs in the cosine term present the upper and lower sideband signals, respectively. It means that if either of the phase errors dominate, IRR is equal for both sidebands. Otherwise, the upper and lower sidebands experience different image rejection. When defining the gain error as IRR can be rewritten as

The image rejection ratio at different gain errors is given in Figure 2.36 when either or is zero. The combined effect is shown in Figure 2.37 for two different values when is swept and As seen from Figure 2.36 both an excellent gain and phase balance are required to achieve good image rejection. The system requirements of an image rejection receiver are discussed later in this subsection. In the case of an ideal amplitude balance, large differences in the image rejection of the upper and lower band can be obtained if phase differences before and after the frequency conversion can boost or cancel each other. The effect will be cancelled out if amplitude errors dominate. In analog structures, the achievable IRR has been typically in the range of 30-40 dB if special techniques have not been adopted.

53

It is difficult to generate an accurate 90 phase shift for a modulated channel, which has a relatively wide bandwidth compared to the signal frequency. The problem exists at the downconverted output of the Hartley receiver. Another issue is the variations of component values in passive RC networks, which can perform an exact phase shift only at a fixed frequency. To overcome the problems a third method for image rejection has been developed by Weaver [23]. The first method refers to filtering and second to phasing in this context. Instead of the phase shift network in the signal path, the appropriate phase shifts are generated using a second quadrature LO as shown in Figure 2.38. Now all necessary phase shifts are done only for narrow-band LO signals, and relatively coarse lowpass filters are needed to remove the upconverted replica after the first mixers. The phase responses of the filters can be designed

54

insensitive to process variations at the relatively low frequency band of interest compared to the cutoff. Weaver architecture still suffers from the insufficient image rejection similarly as Hartley receiver, but the analog implementation is somehow easier because all phase shifts are performed for narrow-band signals. If the signal is not converted to the baseband after the second mixing stage, a secondary image can fall at the same band with the desired channel without any relative rejection [4]. It is located on the same side with the LO in the first downconversion and at the image frequency of the desired channel in the second downconversion. In that case, bandpass filters should be used instead of lowpass structures. The bandpass filters can be also used to remove different dc offsets of the preceding stages, if the second downconversion produces a baseband signal. The baseband signal is often named also as zero-IF in the discussion of radio architectures.

The idea of using image rejection architectures to replace high-frequency image filters in the receivers has been unattainable before the evolution of integration technologies. The improved matching properties and increased possibilities to use digital signal processing are reasons for the recent development. For example, the 90-phase shift can be performed almost ideally in the digital domain with a reasonable amount of oversampling compared to the input signal. Hence, the low-frequency phase shifting problem of the Hartley receiver is avoided. Still the gain and phase accuracy in high-frequency circuits is the limiting factor in image rejection architectures. Some reported implementations, which are based on the image rejection, are discussed in the next chapter. The requirement for the image channel rejection depends on the system and the intermediate frequency after the first downconversion. If we assume that the IRR specification can be calculated like the other selectivity parameters, which means that the desired channel is typically 3 dB above the sensitivity level, the IRR can be given in decibels as

where is again the dynamic range i.e. the ratio of the unwanted image frequency to the desired channel. In the test, the noise level compared to the signal is 3 dB below the minimum required, and the image must be attenuated to the same level with the noise to meet the BER requirement. Therefore the 3-dB term is needed. The IRR requirement depends on the selected intermediate frequency if the spectral mask of the unwanted channels is not flat. Three different cases are shown in Figure 2.39. The maximum power at the adjacent channel is typically smaller than at the other channels in most of the systems, which relaxes the IRR specification. If the image channel is located outside the system band, the attenuation of a duplex or preselection filter attenuates the image, which comes from another system. In that case, the radio spectrum

55

of the image must be carefully examined in the frequency plan, because it may contain high power levels and the attenuation of a preselection filter might be only in the order of 25-30 dB.

2.4.7

Quadrature Demodulation

Both image rejection architectures require a separate demodulator at the output of the structure. It means that the input is not a baseband signal, and the output should be divided again into quadrature if needed in the demodulation. Therefore the quadrature downconversion in the direct conversion or zero IF receiver should not be compared to the first downconversion stage in image rejection topologies. The direct conversion is the only architecture, which does not suffer from the unwanted image problem. The RF downconversion stage is already a demodulator. The amplitude and phase accuracy is still critical, and more difficult to implement than at low-frequency demodulators, but the specifications are significantly relaxed compared to image rejection topologies. The demodulation process is basically similar in all receivers. A high operation frequency and analog implementation increase the sensitivity to errors, but sufficient performance can be often achieved with a more efficient structure if power consumption or silicon area is compared. The faster development of digital technologies and hence processing capabilities gives a floating goal for optimization. The limitations for phase and amplitude errors of a quadrature demodulator in digital systems can not be given easily with a simple analysis. The accuracy requirements depend on the modulation and the complete implementation of the demodulator, which usually consists mainly of digital structures. Therefore, a detailed analysis is often unattainable for an analog designer. However, some main concepts should be taken into account and the required performance for the analog circuits should be defined based on the applied demodulator structure of the system. A block diagram of the QPSK demodulation principle is shown in Figure 2.40. For example, a digital signal processor can perform clock recovery and correct certain imperfections afterwards, which changes the structure of the implementation significantly. The implementations of different demodulators or detectors are not discussed here any further.

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The phase and amplitude errors cause relative shifts between the locations of different symbols in the constellation diagram. The variable errors caused by noise, nonlinearities and other timevariant measures are often given with the concept of error vector magnitude (EVM) shown in Figure 2.41. It gives the rms variation of the symbols from the ideal constellation points, typically in percents. EVM is the summation vector of different nonidealities. It is commonly used especially when estimating the performance of the transmitter.

In the receivers, the fixed amplitude and phase errors between the channels in the quadrature demodulation do not modify the magnitude of the error vector. Instead, the shape of the constellation is changed. The effects of fixed amplitude and phase errors are described in Figure 2.42. They bring certain constellation points closer to each other, which increases the probability to false detection. Hence, the constant error vector can not be compared directly to EVM, because the effect on the BER is not necessarily the same as in the case of noise and distortion. The error vector magnitude is useful when the effect of different nonidealities on the receiver performance is measured, and the properties of the specific modulation are taken into account. It can describe combined behavior, which is difficult to determine otherwise, but with little insight on the problems if the different phenomena are not studied also separately.

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The effect of fixed phase or amplitude errors in the demodulator should be studied with BER simulations rather than with EVM. Hence, it is not possible to determine initial estimates for the same parameters with as simple analysis as in the case of IRR for image rejection architectures. The simulated effect of fixed phase error on BER for a WCDMA receiver is given in Figure 2.43. In the simulations, an integrate-and-dump circuit with ideal sampling times has been used as a detector. A phase error of 1 causes practically negligible deterioration on the performance and with 5 error the degradation is less than 1 dB even at a low BER of The required performance is significantly relaxed compared to image rejection receivers. Similar results are given for a direct conversion receiver operating in a paging system in [24]. The system simulations with an interpolation demodulator allow 10 phase errors with a 0.1-dB degradation in the performance for BER values down to The balance requirements should be met over the total system band, which often requires special techniques to produce sufficiently wide relative band widths for structures generating the quadrature phases at RF.

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2.4.8

Special Topics in CDMA Communications

As discussed earlier, the most distinct characteristics of a CDMA system are the simultaneous transmission of several traffic channels at the same radio band, and the capability to detect signals, which are buried in noise. Both properties are based on the coding of the transmitted information with a pseudorandom sequence, and on the effect of the processing gain in the despreading with the same sequence. This subsection compares the CDMA communications to other methods and alleviates the trade-offs in the receiver design. The numerical examples are based on the original WCDMA proposal given in Table 2.2. If not otherwise noted, the I- and Q-channels of the QPSK modulated signal are spreaded with two independent 4.096 Mcps code sequences. Hence, the 64 ksymb/s nominal symbol rate gives an 18-dB processing gain. The basic property in third generation systems is the flexibility to use variable data rates in the transmission. The multirate services can be provided in CDMA systems either by a variable spreading factor (VSF) or multicode [1]. The former means that the spreading factor, and hence the processing gain, changes when the data rate is varied and the chip rate is constant. In the multicode scheme, the high-speed data is first divided to parallel branches, and each branch is spreaded with an individual code before summation. Hence, the spreading gain of each branch is larger. Neither of the methods is superior to each other, but they have different benefits and drawbacks in comparison of signaling, power control and complexity. It is proposed that the multicode transmission is preferred for the forward link while variable spreading factor has more advantages in the reverse link [25]. The analog receiver is basically insensitive to the differences because the chip rate, and therefore the channel bandwidth, is constant with two precautions. The envelope variations with a large number of different code channels are increased compared to a single spreading code. This is of importance especially for the linearity of a power amplifier in a mobile terminal. It can also increase linearity requirements in some receiver architectures, but they are probably less significant, because the reception contains several independent traffic channels at the same band in all cases. The other implementation constraint is the need of several parallel fingers in the despreading process of the multicode transmission. However, the multiple fingers are typically implemented with digital techniques in the direct sequence systems. Fundamentally, the higher data rates reserve more capacity from the radio channel in both cases, which means less users per channel. All wireless communications using CDMA can be considered as wide-band systems because they occupy wider bandwidth for the transmission than required by the Nyquist constraint. Hence, the term WCDMA in connection to the third generation systems refers only to the fact that the radio channel is even wider than in the earlier commercial CDMA systems, and that the system is designed to provide also high data rate services besides of speech. The principle does not change, and the wider bandwidth allows only a reasonable processing gain for high data rates as well. Despreading recovers the transmitted narrow-band information and improves the SNR compared to all other signals by the amount of processing gain according to Equation (2.2), because the out-of-band signals can be filtered out afterwards. Besides that the narrowband interferers will be spread over the whole band defined by the chip rate. Hence, their power averages, and can be compared to white noise. The effect of despreading in the presence of noise and a narrow-band interferer is visualized in Figure 2.44. Also, some implementation constraints have less severe effects, because the wide-band channel is less sensitive to the frequency dependent nonidealities, which average after the despreading over the bandwidth limited by the chip rate. They will be discussed later in this subsection. To some extent the effect of despreading can be compared to oversampling in the discrete-time signal processing. The other traffic channels at the same band use orthogonal codes, which means ideally that they do not correlate, and therefore behave like noise to each other. In the following analysis, perfectly orthogonal codes are assumed in all cases, and also that a sufficient number of

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orthogonal codes is available at any moment. Both issues are important and critical for the radio system design. The capacity of a single radio channel is the key issue in CDMA communications. First, it is discussed for a single traffic channel with different data rates, and after that several code channels are adopted at the same band. It should be remembered that the given equations are based on simplified assumptions, which do not take the properties of digital signals into account. However, in most cases this is sufficient, and gives enough information for the specification of an analog radio interface in the digital receiver.

The sensitivity specification for a CDMA receiver can be defined uniquely only at one reference point with fixed data rate and bit error rate requirements. In multirate, multiservice systems, all other cases are defined according to Equation (2.12). For example, if it is assumed that the noise bandwidth is equal with the data rate, the 4.096 Mcps transmission with a 5-dB noise figure of the receiver corresponds to a 103-dBm total input referred noise power. The 18-dB processing gain and BER requirement for a QPSK signal gives the sensitivity of -114 dBm. The sensitivity as a function of different data rates and BER values is given at this reference point in Figure 2.45. The dependence on the data rate is modeled with a variable spreading factor as described above. Over 30 dB variations in sensitivity can be obtained between different services. Typically, reasonably low quality and low bit rates are accepted for speech transmission compared to data. Hence, both extremes are theoretically possible. The effect of coding gain is neglected in Figure 2.45. WCDMA system uses different coding schemes for data and speech [1], which can have different influences on the sensitivity.

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The selectivity both in the case of adjacent channel and other interferers can be defined similarly as with other systems. Again, it is assumed for convenience that the signal is 3 dB above the sensitivity level when all selectivity parameters are defined. Hence, it is still buried in noise. The interfering signals can be equal with the noise level to cover the 3-dB margin as earlier. It means that the adjacent channel or other interferer can be at much higher level compared to the desired signal still at the input of a decorrelator. Therefore, the spurious-free dynamic range as given in Equation (2.43) is not an appropriate definition for the dynamic range at the system level for two reasons. The narrow-band systems benefit from the bandwidth dependent term and the capacity of the system has not been taken into account. Hence, the SFDR should be rewritten for the receiver as

This gives an interesting result of the fundamental difference in the performance of CDMA systems. In the comparison the same data rate is transmitted in the conventional TDMA or FDMA system and in a DS-CDMA channel. The data rate is 64 ksymb/s and the expected receiver performance, which is relatively independent of the system, is defined with parameters and The required is 7 dB, which corresponds to a -11 dB SNR requirement for the CDMA channel at the 4.096 Mcps rate. The thermal noise floor is at the -126-dBm level in the narrow-band transmission if an ideal filtering is assumed, which gives a 67 dB SFDR. The CDMA channel with a 108-dBm thermal noise achieves a 73 dB SFDR with the same parameters. The improved SFDR indicates better immunity against out-of-band interferers. However, it is not achieved for free, because there are several transmissions simultaneously at the same band, which provides different restrictions for the implementations. They will be discussed below with respect to analog circuitry. Also, the coding efficiency, which describes the ratio of the actual information to the additional coding needed for the system management, is neglected. It is out of the scope in this context. Another system management issue is the efficient use of potentially available performance, which is discussed in [26] from the UMTS perspective, for example. The comparison between SFDR values in different systems is shown as a function of the symbol rate in Figure 2.46.

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The required IIP3 value for a CDMA system can be calculated from Equation (2.35) when the test signal is 3 dB above the sensitivity level. The interfering signal is above the test signal by the amount of The factor is now the dynamic range, which is actually the same as the SFDR for the CDMA system in Figure 2.46. The IIP3 value as a function of the dynamic range is given for two different processing gain values in Figure 2.47. The above discussion considers only the instantaneous dynamic range at low signal levels. When the power level rises, the IIP3 requirement behaves similarly as given earlier in Equation (2.46). The given analysis has shown that the direct sequence CDMA systems have fundamentally a higher dynamic range in the presence of out-of-band interferers than the other access methods when the transmitted data rate and receiver parameters are equal. However, this a conflicting argument to the fact that the existing IS-95 system using DS-CDMA has probably the most stringent linearity requirements of all cellular systems [27]. This is mainly due to a hostile signal environment rather than the CDMA characteristics. The existence of narrow-band high power signals, often called as jammers, define the most stringent linearity characteristics, which is the case both in [18] and [27]. The jammers come from other cellular systems, which exist at the same band close to the received radio channel. They can have larger, uncontrollable power levels, which increase the linearity requirements. For example, if two systems are operating at the same band with different noise figure but similar dynamic range requirements, the system with a lower average and peak power levels suffers from the stronger one. The fact that 2-dB of added dynamic range requires a 3-dB improvement of IIP3 at high power levels is inevitable. Therefore, the compatibility in power levels is maybe the most efficient way to optimize the system performance. The cross-modulation problem, described in [18], practically rules out all architectures without an image rejection filter after the LNA in IS-95. The cross-modulation of the leaked transmitter power around a jammer specifies IIP3 value of +4 to +5 dBm at the input of the LNA. The IIP3 requirement would be multiplied with the LNA gain if the leaked power from the transmitter can not be filtered efficiently after the LNA. In that case, LNA has more stringent IIP3 specification than the total IIP3 of the receiver.

So far, only the out-of-band interferers have been considered. They can be specified quite similarly as with other systems. However, the performance is referred only to a single traffic channel at the desired band. It is a practical definition for sensitivity or selectivity, but not sufficient in the case of in-band interference in CDMA. First, the capacity is discussed based on

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the number of different traffic channels at the same band. Later, some other limitations are described. To simplify analysis, it is assumed that all different traffic channels have equal data rates, which is defined by the corresponding processing gain. They have also equal power levels at the input of the receiver. The total number of traffic channels including the desired one is marked with Now, the interference power due to other traffic channels can be written as

where is the power of each individual traffic channel. The smallest detectable channel in the presence of noise and other traffic channels can be evaluated in absolute values as

is the in-band noise power including the thermal noise floor and the input referred noise figure of the receiver. The required channel power as a function of total number of channels is given in Figure 2.48 (a). The limited capacity of a CDMA channel can be defined when axis are changed and the maximum number of channels is calculated from Equation (2.62) in absolute values as

The plot of as a function of the channel power is shown in Figure 2.48 (b). The curves are saturating to a fixed value after the signal power is sufficiently above the sensitivity level. In that case, the last term of Equation (2.63) is negligible, and the maximum number of channels gives the capacity of the system [28]. The maximum capacity and the summed symbol rate of different traffic channels are given in Figure 2.49. The definition of capacity is inaccurate at low processing gain values, which can be seen as a violation of the Nyquist bandwidth constraint in Figure 2.49. Another important fact is that if the maximum capacity, i.e. the number of different users, is transmitted simultaneously, the total symbol rate at the radio channel is far from the maximum because the different transmissions interfere with each other. On the other hand, the same frequencies can be used already in the adjacent cells, which increases the efficiency of the frequency reuse compared to other multiple access methods. The high-speed transmission can be performed with low processing gains, but they reserve practically all the available capacity of the radio channel. Only one channel can be transmitted at the sensitivity level. Higher power levels must be used when several traffic channels are applied at the same band. The available capacity for the signals, which are a certain amount above the sensitivity level, are given in Figure 2.50. The channel power, gives the sensitivity when The power of each traffic channel is multiplied by p, which indicates the level above the sensitivity. The new channel power is placed in Equation (2.62), and the maximum number of channels can be rewritten as

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The 20-dB curve follows the ideal with a good accuracy, and the loss is relatively small at the 10-dB curve. However, this indicates that the average transmitted power is probably significantly larger than might be assumed according to sensitivity. Hence, the linearity may become a serious problem. It is evident that if one traffic channel has more power compared to the others, the capacity will be limited. The efficient power control mechanism is critical for the optimization of the CDMA system performance. However, the topic is not considered here any further. The gain control is assumed ideal, and the loss of performance is included in the digital implementation margin. Analog gain control techniques are probably needed, but the control at the system level is most likely digital. More important in the context of radio receiver design is the much wider in-band dynamic range than in the systems having only a single simultaneous traffic channel at the input of the receiver. Some issues will be discussed next. The complexity of the system increases significantly, because the radio environment is changing rapidly, and static conditions can not be allocated for each traffic channel. For example, the sizes of individual cells may vary as a function of time depending on the current traffic in the cell and in its neighbors. However, the effects of loading, voice activity etc. should be considered at a higher hierarchy level.

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Only noise and other channels are considered so far with respect to the capacity of a CDMA radio channel. A deeper insight of the limitations can be given with an equation, which is modified from the forward link budget calculations in [28]. The signal-to-interference ratio of a traffic channel can be given as

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is now the power of the desired traffic channel. The signal-to-interference ratio is used instead of SNR only because naming of all interference sources as noise is confusing. Still, the S/I must be at minimum the same as to allow detection with the required BER. and are the interferences of overhead channels from the own and other near-by base stations, respectively. The overhead channels contain for example pilot, possible paging and synchronization channels at the same carrier. They are needed for system level control, and inevitably decrease the capacity of actual information channels. describes the other in-band traffic channels in the same cell as earlier, and is the total interference from the traffic channels in other cells. The non-CDMA transmissions or jammers at the same band are marked with The first five terms in the denominator are marked with but all values in the following analysis are based on the calculations of as given earlier. The other terms degrade the performance, but the actual values can be estimated only with a careful network planning. Therefore optimal performance is a better reference in this context. is the sum of thermal noise and noise figure of the receiver as given in Equation (2.9). The last term, is of interest for an IC designer because it contains all implementation-oriented nonidealities, which are typically assumed negligible at the system level. Other terms in the denominator except of the noise figure and are system parameters, which can not be optimized in the analog design. As seen from Equation (2.65) the capacity is a complicated function of implementation and traffic related factors. They are not totally independent of each other. In the optimal case, each individual channel transmits only minimum power, which is required to detect the channel at a certain BER. For example, if the noise figure of a receiver is low, less transmission power is needed to detect the signal, which lowers the interference not only inside the current cell but also in neighboring cells. Hence, all transmitters can lower their power. On the other hand, the opposite situation may lead to power competition. Inside the cell, the worst terminal limits the capacity besides of the traffic, and the performance reflects to other cells as well. However, the complexity of fading radio paths, variable distances of terminals from the base station and other environmental issues probably dominate the performance more than the circuit implementations if they follow certain limits. Therefore too detailed optimization between different restrictions is impossible, but the understanding of different phenomena is still necessary. The above discussion considers the forward link and thus the performance of the receiver in a mobile terminal. In the reverse link, the overhead channels are not necessary because the base station does not need system control signaling from the mobile. Otherwise, the same criteria as earlier are valid. The effect of the implementation-oriented in-band interference can be divided at least to following terms:

comes from the quantization noise, from intersymbol interference, from nonlinear effects of other traffic channels, interference from the transmitter, and from phase noise. Next, each of them will be discussed separately. Some of them depend on the traffic in the radio channel. If the value of the parameter is a function of the total traffic, the worst-case conditions should be estimated. The in-band dynamic range of a CDMA radio channel is plotted as a function of processing gain. Dynamic range is the difference between the processing gain and the minimum SNR in the simple analysis. At sensitivity level, it is purely defined by the noise, but at higher signal levels by other interfering sources given in Equation (2.65).

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The effect of quantization noise was analyzed earlier with respect to the dynamic range in the presence of signals at other radio channels, which can be filtered out in the digital domain. The number of bits, which is required for the demodulation of the received signal was neglected or actually assumed that a one-bit comparator is sufficient and the threshold is optimized. In CDMA systems, the signal characteristics have significant effect on the required number of bits. The input signal of the ADC consists of the desired traffic channel, additive white Gaussian noise, and signals from other users, which have propagated through a multipath radio channel. Therefore, a simple approximation is not possible. It can be intuitively claimed without a proof that the signals with a large amplitude envelope require larger word lengths in A/D-conversion. Hence, the problem is not limited only to CDMA systems and must be studied separately with a realistic signaling in each system. The required word length is analyzed based on theory and defined with simulations for two different DS-CDMA systems in [29]. The optimum threshold level compared to the maximum input voltage of the ADC is first analyzed at constant conditions for different number of bits. In the multibit case, the optimum signal level is 6-12 dB below the maximum and less with a two-bit word because LSB limits the dynamics, and the quantization noise is not distributed uniformly. At the optimum threshold, 4-6 bits is simulated to be sufficient when ideal raised cosine filtering and synchronization is used. The performance degradation is 0.5 dB or less with 4 bits and less than 0.1 dB with 6 bits in both cases. The results depend on the signaling, but the degradation is referred to a despreaded signal. Therefore the given numbers can not be directly compared to in Equation (2.66). Similar results are given for a WCDMA system in [1]. The above characterization is valid only for one radio channel. If out-of-band signals are not filtered in advance, the required dynamic range must be added to the word length taking into account that the threshold voltage, to which the dynamic range is referred, is not the full-scale input of the ADC. The theoretical analysis of intersymbol interference is also complicated in a DS-CDMA system. The traffic channel is filtered in two stages. First, the wide-band radio channel is selected, and after the despreading, the desired narrow-band data is filtered again. In principle, this can be understood as a chain of two matched filters with different bandwidths as shown in Figure 2.52. Only the first filter is typically of interest for an analog designer. The use of digital detectors in DS-CDMA systems, adopting several RAKE fingers etc., will be not discussed here. The wide-

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band input signal should be synchronized to the spreading code, but this can be also done with digital techniques in the receiver. The wide-band channel selection filter has different ISI requirements than the narrow-band matched filter in the detector. The numerator in Equation (2.28) depends on the power of the desired traffic channel while the ISI term in the denominator is a function of all in-band traffic channels. Hence, the denominator should be multiplied with the in-band dynamic range On the other hand, the signal-to-ISI ratio improves by in the despreading process, which means that the performance is improved by the of the modulation if the whole capacity is used and even more otherwise. The given argumentation is valid assuming that other in-band traffic channels can be considered as pulsed data, and therefore do not behave like noise. In principle, this would give slightly relaxed requirements for the wide-band matched filter specifications because of the averaging effect in the despreading. However, complicated system simulations, which include appropriate signal statistics, are required to confirm the claim.

The transmission in a CDMA channel contains several modulated signals. The required dynamic range of a radio channel is small compared to out-of-band interferers as shown above, and the processing gain raises the signal above the interferers after the despreading. It may not be necessary to characterize the in-band linearity requirements especially because the nonlinear products should never reach the signal power of the fundamental tones if the signal path is not totally compressed. Hence, at least the signal compression should be avoided in the analog back-end. However, a receiver with an analog channel selection filter and ADC with a minimum number of bits for the signal detection, requires a large gain to achieve an appropriate signal level at the input of the ADC. The last analog stages should handle large signal amplitudes with a relatively large dynamic range. Also, wide-band stages at the linear back-end may consume a significant amount of power, which should be minimized without a degradation of performance. When operating at full capacity, there is practically no headroom available for nonidealities, and hence second-order effects should be probably 10-20 dB below the total interference level. Therefore some comments about in-band linearity will be given. The modulated channel is described with as earlier in the discussion of cross-modulation in Equation (2.42). The model is useful in theoretical calculations, but specific results would require system simulations and careful characterization of the modulation properties. The interest is in the baseband signal processing, and the potential problems exist in the stages just before the ADC. Therefore, the reactive elements can be neglected and the use of power series analysis instead of Volterra series is sufficient [30]. The power series according to Equation (2.31) is calculated for the modulated baseband signal i.e. The output is then

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The nonlinear products are located at the modulation frequency, and its harmonics. The different terms according to their frequency are collected in Table 2.4. The components due to the second- and third-order nonlinearities are calculated separately. The different harmonics actually describe the spectral regrowth. If we assume that the modulation consists of different independent frequency components from 0 to having equal amplitudes, where presents the channel bandwidth, the rms-values of the spectral components can be integrated over the bandwidth. In that case, only half of the second harmonic and third of the third harmonic components are located at the passband. This is simplifying but a descriptive presentation.

The dc term is neglected in the calculations. The cross-modulation because of the third-order linearity can be written as

The second and third harmonics of the are practically insignificant. The cross-modulation result is compared to the desired signal given by in Table 2.4, and to the iip3 of the twotone test calculated in Equation (2.33). The ratio between signal and the cross-modulation can be given as

The terms

and are practically the same in the previous equation, but in different roles. describes the required ratio between the maximum signal and cross-modulation. If

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it is desired that the cross-modulation power should be 10 dB below other interferers i.e. and the modulation index is between 0 and 1, the ratio between iip3 and the signal level must be 22-24 dB. The earlier estimate of optimal input level for ADC corresponding -1 to +10 dBm power levels referred to gives virtually a +20 to +35 dBm IIP3 requirement at the ADC input. Assuming that the number of bits is defined for a sufficient dynamic range otherwise, the IIP3 of the ADC can be considered more likely as an OIP3 requirement of the analog back-end. Although the given numbers may give a pessimistic or too stringent requirement for the back-end, it alleviates importance of a linear signal path before the despreading. More accurate analysis and exact values are out of the scope in this presentation. However, it should be taken into account that the in-band linearity either specified as IIP3 or ICP is of importance in DS-CDMA systems. A similar characterization can also be given to the second-order nonlinearity as

and the ratio between the signal and cross-modulation is

The characterization of the cross-modulation gives an observation, which is actually a selectivity issue. The higher-order components of the adjacent channel i.e. the spectral regrowth can be significant if the adjacent channel power is much higher than the detected signal. The problem is definitely not as serious as in power amplifiers, but not necessarily negligible either. In CDMA systems both reception and transmission are typically continuous. Hence, the transmitted power can be coupled to the receiver through the antenna or parasitic effects. For example, the isolation between transmitter and receiver ports in a duplexer is not infinite. The isolation should be better than the difference of the maximal transmitted power and the ICP of the receiver to avoid the desensitization due to compression. Another problem, crossmodulation of the transmitter power with blocking signals at the reception band is described earlier. The leakage power is typically an issue only in the first amplifying stages and filtered out to a negligible level immediately after that at the baseband. The large frequency offset between transmission and reception bands relaxes the filtering requirements. The transmitter has also a wide-band thermal noise floor at the output. Noise at the reception band is inseparable from other sources, and therefore decreases the sensitivity. The noise of the transmitter is negligible if

where is the thermal noise of the transmitter, is the isolation between the transmitter and the input port of the receiver, and the total noise figure of the receiver. The characterization of phase noise in wireless communications is of importance and a detailed description of different aspects is given in [31], for example. Here, only some brief comments are given on the system requirements when narrow- and wide-band systems are compared. The discussion covers the possible degradation of signal-to-noise ratio due to phase noise. The timing accuracy issues are not treated. The reciprocal mixing in the receiver is compared in Figure 2.53 (a) and (b). In narrow-band receivers, the oscillator phase noise mixed with higher

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near-by channels may alias an unacceptable amount of noise on the reception band of a weak channel. In a wide-band receiver with the same phase noise performance, the effect is much smaller. The phase noise requirement is typically one of the most stringent specifications for the monolithic implementations. Hence, the specifications are relaxed in wide-band receivers. If the narrow-band channels are located next to the wide-band channels, like typically in IS-95, most of the benefit is lost. The phase noise of the transmitter has different characteristics in forward and reverse links. The phase noise of different mobile terminals operating at the same CDMA channel is summed in the receiver of the base station as shown in Figure 2.53 (c). Therefore the maximum phase noise power of the receiver in the base station can be given as

where is the phase noise power of each individual mobile transmitter, and the phase noise of the receiver in the base station. The phase noise of different transmitters is assumed equal. Hence, the LO of the mobile transmitter has probably the most stringent phase noise requirement in the CDMA system with respect to SNR. There are only two independent sources of phase noise at each mobile receiver assuming that the phase noise of the transmitter in the base station is dominated by the LO of the last upconversion stage, and that the different traffic channels are combined on the same signal path before the conversion. The factor is then one when calculating the phase noise in the mobile receiver based on Equation (2.73).

The effect of despreading has been discussed several times earlier. The significance in protection against multi-path or fading effects in wireless transmissions is appreciated by the communications literature. In the receiver design, there are also some obstacles, which can be avoided or effect can be reduced when a wide-band channel is processed. The following comments apply only before the despreading of the wide-band channel. For example, if the frequency hopped CDMA is used and the first downconversion mixer changes the frequency according to the spreading sequence i.e. despreads the signal, all stages after that process contain narrow-band information and the possible advantages are lost. The disadvantage of the wide-band channel is naturally larger power consumption because of the high speed and larger parasitics. However, the scaling of the analog circuits does not obey the same laws as a standard digital CMOS logic, and the current technologies allow the MHz-range channel bandwidths at the baseband with a reasonable power consumption.

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The despreading can be considered either as oversampling or averaging, because one symbol is coded into a longer sequence, and an error in a single bit averages out when the information is recovered from a long bit sequence. Many digital modulations recover the information from the phase shifts, which can be understood as transformation from positive to negative frequencies, or vice versa, at baseband. Often, the maximum average power is at dc if the channel response is presented as a double-sided spectrum in the frequency domain. Hence, the removal of the information around dc is even more critical than elsewhere. Unfortunately, some fundamental constraints in circuit implementations produce noise or distortion exactly at dc or around it. They are of special importance in the receivers, which have much gain at analog baseband stages, like in the direct conversion architecture. Flicker noise and static dc offsets due to circuit mismatches are both critical. The dc error averages efficiently out in a CDMA system because the detected BER does not depend on a single incorrect transmission over dc. Different techniques can be used to remove the dc component. At the system level, the appropriate model for offset removal with capacitive coupling is a first-order highpass filter. Estimates for an unspreaded QPSK signal are given based on BER simulations and eye diagram in [32] and [11], respectively. Both suggest that only 0.1 %, or even less, can be removed from the spectrum without deteriorating the reception significantly. The percentage describes the ratio of the bandwidth to the total symbol rate. Because the notch removes both positive and negative frequencies the notch bandwidth is twice the 3-dB bandwidth of the highpass filter, which is another typical parameter to specify the filtering. The effect of despreading requires heavy simulations, because a much larger number of clock cycles must be simulated to recover the final data. The performance is shown without the effect of despreading and with processing gain of 6 dB in Figure 2.54. The SNR is defined at the input, and the x-axis of the 6-dB curve is scaled according to the processing gain. The simulations for larger processing gains are unattainable, but the low processing gain indicates already improvement in performance. The different curves are closer to ideal when spreading is used, and a 2 kHz cutoff frequency gives negligible degradation in performance. A 2 kHz cutoff corresponds to 0.1 % removal of the spectrum when compared to the chip rate. If the same data rate is transmitted without spreading, the filter would remove 0.4 % of the total band, which would degrade the performance significantly. The benefit of the high cut-off frequency is the smaller component values, which are easier to implement, although even a 10 kHz notch would require special techniques if implemented on-chip [11].

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Flicker or 1/f-noise contribution is reduced in a wide-band channel. The flicker noise is compared to thermal noise in [11] as

where is the thermal noise of the system, is the cutoff frequency of the highpass filter, is the corner frequency of the flicker noise, and is the noise bandwidth of the system. At corner frequency flicker noise is equal with the thermal noise, and hence the factor A narrow- and a wide-band receiver are compared in Table 2.5 with two corner frequencies of 20 kHz and 200 kHz, which present typical values in monolithic receivers. The reference is calculated by integrating the thermal noise from dc to and the noise degradation due to flicker noise is given in decibels. The cutoff frequency of the highpass filter is set to 0.1 % of the noise bandwidth in both cases. The benefit of wide-band signal processing is evident when the immunity against flicker noise is estimated.

The implementation of a CDMA system is a complicated challenge, because the proper operation requires dynamic control all the time and the efficient use depends on the careful frequency allocation. Most parameters concerning the analog radio receivers are similar in different systems if the scaling of the bandwidth is taken into account. The special topics covered in this subsection give a frame to estimate the differences from the implementation point of view. There are clear benefits but also new restrictions when the CDMA is adopted. Many aspects are definitely not discussed, and more new challenges will be found when the new systems are launched in few years.

References
[1] T. Ojanper, R. Prasad, ed., Wideband CDMA for Third Generation Mobile Communications, Boston, London: Artech House, 1998. [2] L. E. Larson, ed., RF and Microwave Circuit Design for Wireless Communications, Boston, London: Artech House, 1996. [3] D. K. Shaeffer, A. R. Shahani, S. S. Mohan, H. Samavati, H. R. Rategh, M. d. M. Hershenson, M. Xu, C. P. Yue, D. J. Eddleman, T. H. Lee, A 115-mW, CMOS GPS receiver with wide dynamic-range active filters, IEEE J. Solid-State Circuits, vol. 33, pp. 2219-2231, December 1998. [4] B. Razavi, RF Microelectronics, Upper Saddle River, NJ: Prentice-Hall, 1998.

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[5] R. C. Dixon, Spread Spectrum Systems With Commercial Applications, York: John Wiley & Sons, 1994.

ed., New

[6] A. Rofougaran, G. Chang, J. J. Rael, J. Y.-C. Chang, M. Rofougaran, P. J. Chang, M. Djafari, M.-K. Ku, J. Min, E. W. Roth, A. A. Abidi, H. Samueli, A single-chip 900-MHz spread-spectrum wireless tranceiver in CMOS---part I & II, IEEE J. Solid-State Circuits, vol. 33, pp. 515-547, April 1998. [7] H. T. Friis, Noise Figures of Radio Receivers, Proc. of the I.R.E., vol. 32, pp. 419422, July 1944. [8] H. Nyquist, Certain Topics in Telegraph Transmission Theory, Trans. Am. Inst. Electr. Eng., vol. 47, pp. 617-644, February 1928. [9] [10] A. B. Carlson, Communication Systems, Singapore: McGraw-Hill, 1986. B. Sklar, Digital Communications, Englewood Cliffs, NJ: Prentice-Hall, 1988.

[11] B. Razavi, A 2.4-GHz CMOS Receiver for IEEE 802.11 Wireless LANs, IEEE J. Solid-State Circuits, vol. 34, pp. 1382-1385, October 1999. [12] R. Schaumann, M. S. Ghausi, K. R. Laker, Design of Analog Filters, Englewood Cliffs, NJ: Prentice-Hall, 1990. [13] H. Samueli, An Improved Search Algorithm for the Design of Multiplierless FIR Filters with Powers-of-Two Coefficients, IEEE Trans. on Circuits and Syst., vol. 36, pp. 10441047, July 1989. [14] J. Vankka, M. Kosunen, K. Halonen, Multicarrier QAM Modulator, in Proceedings of the IEEE Int. Symp. on Circuits and Syst., vol. 4, pp. 415-418, June 1999. [15] P. Wambacq, W. Sansen, Distortion Analysis of Analog Integrated Circuits, Boston, Dordrecht, London: Kluwer, 1998. [16] K. A. Simons, The Decibel Relationships Between Amplifier Distortion Products, Proceedings of the IEEE, vol. 58, pp. 1071-1086, July 1970. [17] R. G. Meyer, A. K. Wong, Blocking and Desensitization in RF Amplifiers, IEEE J. Solid-State Circuits, vol. 30, pp. 944-946, August 1995. [18] B.-K. Ko, D.-B. Cheon, S.-W. Kim, J.-S. Ko, J.-K. Kim, B.-H. Park, A 1.8 GHz BiCMOS RF Receiver IC Taking into Account the Cross Modulation for CDMA Wireless Applications, in Proceedings of the European Solid-State Circuits Conf., pp. 346-349, September 1999.

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[19] 1995.

B. Razavi, Principles of Data Conversion System Design, Piscataway, NJ: IEEE Press,

[20] R. van de Plassche, Integrated Analog-to-Digital And Digital-to-Analog Converters, Boston, Dordrecht, London: Kluwer, 1994. [21] R. Hartley, Single-Sideband Modulator, U.S. Patent 1,666,206, April 1928.

[22] D. E. Norgaard, The Phase-Shift Method of Single-Sideband Signal Reception, Proceedings of the I.R.E., vol. 44, pp. 1735-1743, December 1956. [23] D. K. Weaver, A Third Method of Generation and Detection of Single-Sideband Signals, Proceedings of the I.R.E., vol. 44, pp. 1703-1705, December 1956. [24] Z. Chen, J. Lau, Circuit Requirements of a Direct Conversion Paging Receiver, IEEE Trans. on Circuits and Syst.II: Analog and Digital Signal Processing, vol. 46, pp. 802807, June 1999. [25] E. Dahlman, K. Jamal, Wide-Band Sercives in a DS-CDMA Based FPLMTS System, in Proceedings of the IEEE Vehicular Technology Conf., vol. 3, pp. 1656-1660, May 1996. [26] T. Ojanper, J. Skld, J. Castro, L. Girard, A. Klein, Comparison of Multiple Access Schemes for UMTS, in Proceedings of the IEEE Vehicular Technology Conf., vol. 2, pp. 490494, May 1997. [27] W. Y. Ali-Ahmad, RF System Issues Related to CDMA Receiver Specifications, RF Design, pp. 22-32, September 1999. [28] S. C. Yang, CDMA RF System Engineering, Boston, London: Artech House, 1998.

[29] R. D. Gaudenzi, F. Giannetti, M. Luise, The Effect of Signal Quantization on the Performance of DS/SS-CDMA Demodulators, in Proceedings of the IEEE Global Telecommunication Conf., vol. 2, pp. 994-998, 1994. [30] R. G. Meyer, M. J. Shensa, R. Eschenbach, Cross Modulation and Intermodulation in Amplifiers at High Frequencies, IEEE J. Solid-State Circuits, vol. 7, pp. 16-23, February 1972. [31] B. Razavi, A Study of Phase Noise in CMOS Oscillators, IEEE J. Solid-State Circuits, vol. 31, pp. 331-343, March 1996. [32] A. A. Abidi, Direct-Conversion Radio Tranceivers for Digital Communications, IEEE J. Solid-State Circuits, vol. 30, pp. 1399-1410, December 1995.

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Receiver Architectures

The first radio receivers about a hundred years ago were detectors connected directly to the antenna [l]-[2]. The early coherers were replaced with crystal detectors, but the first separate component improving the sensitivity of the receiver was a vacuum tube rectifier with the property of amplification. Further improvements were achieved with tuned radio-frequency (TRF) receivers using self-oscillating detectors, and later with regenerative and superregenerative structures. In a regenerative receiver, a tuned positive feedback reduces the effective resistance of the signal path, and thus enhances the Q-value and amplification of the tuned input circuit. The superregenerative receiver has a separate quench oscillator controlling the effective resistance of the signal path periodically [3]. The feedback structures inherently suffer from stability problems, and careful adjustment was required to overcome the issue. The invention of the heterodyne principle by Fessenden in 1912 and further developments during 1910s by several people leaded into the superheterodyne receiver, which was completed to its final form by Armstrong [4]. The use of a separate local wave in the receiver producing a beat to an audible frequency with the input signal in a nonlinear element is the principle of heterodyne. The beat frequency is defined as an intermediate frequency (IF) in a superheterodyne receiver. Instead of direct detection, the signal can be amplified more at IF, and select a limited band with fixed filtering. The distributed amplification to more than one frequency made it possible to have more gain, because the cross-coupling between stages did not cause instability when operating at different frequencies. Also, the isolation between the amplifying stages is much easier at IF. Another, significant benefit is the narrower noise bandwidth after the IF filter. Due to these properties the superheterodyne receiver was the most sensitive structure for radio reception. According to Armstrong the major advantage of the superheterodyne for commercial applications was the much simpler required tuning by an unskilled user than in any other architecture rather than a superior performance. The superheterodyne receivers displaced all other structures almost totally by the early 1930s, and became the only practical alternative for systems requiring high sensitivity. The automatic volume control, nowadays more likely called as automatic gain control (AGC), was another major invention improving the performance and usability of radio equipment during 1920s. Transistors replaced vacuum tubes as active elements in the radio receivers slowly during 1950s and 1960s. It was not until 1980s when the IC technologies developed to the level when aggressive integration of different radio parts was possible. Starting from baseband, the evolution has brought integrated circuits to the most of the IF and RF blocks today. The rapid growth of the cellular systems has been the driving force of the receiver implementations through 1990s. The concept of radio receiver has been estimated again because of the distinct characteristics of IC technologies [5], and superheterodyne is not anymore the only potential candidate to implement high performance radios. However, it is still the most common architecture with significant advantages. A small size and power consumption are key specifications in mobile terminals, and the current demands can not be met without extensive integration. Almost all architectures in recently published academic papers, and high-end industrial products rely on heterodyning, because the receivers use one or several internal LO signals for downconversion. As an interesting exception, a superregenerative receiver has been reestablished using BiCMOS technology and operating at 1 GHz [6]. The heterodyne architectures can be divided into four categories based on the image and its suppression. The following subsections cover the basic advantages and drawbacks of superheterodyne, direct

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conversion, low-IF and wide-band IF receivers with references to reported implementations. The low-IF and wide-band IF receivers are often called as image-rejection architectures. In the end of the chapter, aspects of direct digitization or IF digitization are discussed. It can not be considered as an individual architecture, because any architecture can be basically implemented with digital instead of analog signal processing if a sufficient number of bits with a high sampling rate is available. Hence, the given discussion will focus on the new requirements of an RF front-end and some specific techniques. The main emphasis is in the direct conversion, and the specific issues will be discussed in detail in the next chapter. In the early advent of the radio receivers, the nonlinear devices in the RF front-end captured the whole radio spectrum. The detectors were tuned to a specific channel manually, but interference from other radio sources was not limited otherwise. Sensitivity was the main concern, and the filtering at IF in superheterodyne gave a significant improvement in performance by limiting the noise bandwidth before the detection. It also removed out-of-band interferers, but only after the signal downconversion. After the discovery of basic bandwidth constraints of the radio communications the spectral efficiency has been a key issue in the radio design. The growing demand of radio spectrum has increased the operating frequencies, and decreased the frequency allocations for each individual system. Also, the different channels are located almost at the minimum theoretical distance from each other. Practically all systems require some frequency selectivity against incompatible systems before active elements. In transceivers, this is typically done with a duplex filter. The main emphasis is to isolate transmitted power from leaking to receiver if operated simultaneously. Other requirements are low loss to minimize the degradation of sensitivity in the receiver and to avoid unnecessary power losses in transmission, and small size in handsets. Besides that, the filter attenuates out-of-band systems, but the attenuation may be only in the order of 25-30 dB at certain frequencies. Hence, it is assumed that such a filter precedes all different receiver architectures having equivalent properties. In the reception, the duplexer should provide sufficient out-of-band attenuation to confirm that the inband interferers dominate the degradation of performance due to nonlinearity. With this precaution the out-of-band interferers carry less power in the receiver chain than in-band components. However, their contribution can still be detrimental if located at the image frequency. It is fair to assume that out-of-band interferers have in the worst case 10-15 dB less power than the largest in-band components after the preselection. Of course, it depends much on the system itself. The duplex filters can not be implemented with modern IC technologies, and the currently available devices have fixed responses and require a certain impedance termination, typically to to maintain the response. This gives a similar RF interface to all architectures. More generally, the component in the receiver should be called as a preselection filter, because the duplexing property is needed only in the two-way terminals using the same antenna. Both terms are used here alternatively when speaking about the signal processing in the receiver.

3.1

Superheterodyne

A superheterodyne receiver removes the image by filtering before each downconversion stage as described in the previous chapter. A block diagram of the superheterodyne receiver with a quadrature demodulator is given in Figure 3.1. The first mixer converts the desired channel down to a fixed IF. The first LO signal is tunable over the system bandwidth, giving the smallest possible relative tuning range for the oscillator. The implementation of voltage controlled oscillators (VCO) and complete synthesizers at RF has been difficult for IC technologies due to stringent phase noise requirements. The recent results indicate improved performance and integration level, but the topic is not included here any further. It can be

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assumed that all architectures using a tunable first LO at RF require an equivalent phase noise behavior. The first IF frequency must be chosen such as the image at any possible LO frequency lies outside the system band, and hence is attenuated by the preselection filter. The fundamental limit for the first IF in a superheterodyne receiver can be given as

where is the bandwidth of a particular system, or in fact, the bandwidth of the preselection filter. The channel selection filter is located at IF. It attenuates all other channels to an insignificant level compared to the desired channel. After that the selectivity is not an issue anymore. The last downconversion stage in Figure 3.1 converts the modulated channel to baseband, and the gain depends on the appropriate level at the input of the detector. The lowpass filter at the baseband presents matched filtering in the detector. The previous is an idealistic view. The conversion to the baseband can be performed in several IF stages distributing the adjacent channel attenuation and interference cancellation along the chain. A part of it can be allocated also to the baseband or change the architecture to image rejection at any downconversion stage. The trade-off comes from the subject whether it is cheaper with respect to the fabrication cost or power consumption add another IF stage, including downconversion, amplification and filtering, than process the signal at a higher frequency with higher parasitics and narrower relative bandwidths.

Due to different characteristics of various technologies the optimization is a very complicated task. The position as the most common architecture is based on two facts. The long-term experience on the implementations of superheterodyne receivers for different systems is unquestioned. The reason for that is the capability to avoid the problems of the insufficient image rejection and the offsets or increment noise in the baseband processing if designed correctly. All other architectures try to circumvent one or both of them, and they are developed mainly because the superheterodyne is incompatible to full integration with current technologies. Due to the image frequency limitation, the first IF is typically at least 30 MHz, and sometimes over 100 MHz. The relatively narrow channel bandwidth requires selective and linear IF filtering, which is not feasible on-chip. The filter after the RF amplifier is needed if noise at the output of the amplifier is significant at the image frequency. The selectivity of the amplifier output is typically not sufficient for the noise reduction. Otherwise, noise from both sidebands folds at the same frequency in the

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downconversion, and can double the noise contribution of the low-noise amplifier (LNA) in the system. Therefore, the filter is called as an image filter. The attenuation in the image filter is not as critical for sensitivity as in the case of preselection because a substantial amount of gain in front of the filter compensates the loss. The external filter requires matching of the LNA output and mixer input. In some cases, the image filter must also attenuate some out-of-band interferers to avoid unreasonable linearity requirements of the mixer as discussed in connection with the cross-modulation in the previous chapter. The RF image filter can be replaced with an image-rejection front-end, which includes two mixers and appropriate phase shifters [7]. They cancel the image at the IF output of the mixer with the cost of extra hardware. An excellent matching is however required. The definition for the noise figure of a downconversion mixer depends on the architecture. If the signal is downconverted to baseband, the double sideband (DSB) noise figure should be used because the modulated signal and internal noise of the mixer are converted from the same band located at both sides of the LO. This can be applied only to the last downconversion stage in Figure 3.1, where noise figure is not so critical. When the downconverted frequency differs from zero a mixer converts its internal noise from both sidebands to the same IF. Hence, the single sideband (SSB) noise figure is an appropriate definition. The input bandwidth of a mixer is normally wide enough that noise at both sidebands is almost the same. However, the noise source at the input is only at one sideband, and therefore the difference between DSB and SSB noise figures is always less than 3 dB [8]. For example, the equivalent SSB noise figure is 12.8 dB if DSB noise figure is 10 dB and noise at the input of the mixer is flat. The use of two or more oscillators operating at the MHz or GHz range and the synthesizer producing a dense raster of high precision controls for a VCO at RF introduces the demand of a careful frequency plan. The internally generated signals also include the digital clock, and in the case of a tranceiver the synthesizer and oscillators of the transmitter. The internal signals and their harmonics can mix with each other or with strong input interferers, and generate spurs at the desired radio channel either at RF or any IF. The protection methods against mixing include isolation of different signals, as small signal levels as possible, a sensible choice of frequencies, a small number of internal frequency references, and different averaging techniques, like CDMA. The power levels or voltage swings of internal references can not be reduced significantly especially if compared to the supply voltage, which scales down along the technology. The reference signals are located closer to each other when the structures are miniaturized, which complicates the isolation. On the other hand, long interconnections with large inductive and capacitive coupling can be avoided. Hence, the problems are changing, but the frequency planning is still needed. The superheterodyne receiver is the most vulnerable architecture because of the use of more than one high-frequency oscillator. The art of frequency planning is not discussed in detail. It would require specific data of the internal structure of the receiver or tranceiver, and detailed knowledge of the signaling environment of the system. Only some comments on the so called half IF problem are given [9]. An interferer, which is located exactly between LO and the desired channel i.e. can fall at IF with two different mechanisms. It either mixes down with an LO and experiences second-order nonlinearity as or its second harmonic mixes down with the second harmonic of LO as Hence, the second-order nonlinearity may be significant also in superheterodyne receivers although rarely considered as an issue. The half IF problem can be reduced if the preselection filter attenuates the component in all cases. Then, the IF must be chosen as

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which is four times the minimum IF given in Equation (3.1). Some reported IC implementations of superheterodyne receivers or their front-ends are given in Table 3.1. It can be seen that the selection of the first IF is often based on the availability of certain commercial bandpass filters for channel selection. For example, all given DECT receivers use a 110 MHz first IF. On the other hand, a 71 MHz IF is a common design practice in GSM because it is larger than the original 70 MHz operation range from 890 to 960 MHz including both up- and downlink transmissions [10].

3.2

Direct Conversion

A direct conversion receiver converts the carrier of the desired channel to the zero frequency immediately in the first mixers. Hence, the direct conversion is often called also as a zero-IF receiver, or a homodyne receiver if the LO is coherently synchronized with the incoming carrier. The latter term is mainly historical in connection with the radio receivers. The synchronization of the LO directly to the RF carrier can be avoided with other techniques in

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current applications, and in recent literature, homodyne is actually used mostly in optical reception. Tucker proposed his own term synchrodyne to be used in the case of synchronization of an otherwise free oscillator to the incoming carrier [25]. However, Tuckers own doubts about the possibility to change terminology have proved to be real. Because the synchronization of the high frequency LO is not necessary, the direct conversion and zero-IF are more generic terms to be used in this context. The condition for the direct conversion can be defined uniquely as

The direct conversion reception has been initially considered already in the 1920s, but the first practical application was established in 1947 for a measuring instrument [25], [5]. The inherent imperfections of direct conversion, discussed later in this section and in the next chapter, prevented the use of the scheme in most applications. It was not until the development of the IC technologies, which made it possible to adopt the direct conversion architecture in certain portable receivers. The evident benefit of the potential increase in the integration level to reduce cost, and the rapid growth of the cellular market have been prominently focused the research and advanced the knowledge from the 1980s until today. The characteristic advantages and drawbacks of the architecture are already recognized and collected in [26], [27]. Unlike superheterodyne, the direct conversion receivers are sensitive to several system dependent issues like modulation or duplexing. Every application has different prerequisites and therefore the suitability and specifications must be considered in each case independently. This is actually true for all architectures, which do not filter out the unwanted channels sufficiently at high frequencies. Only the typical drawbacks vary between the different architectures. This section gives a general introduction of the characteristic properties in direct conversion receivers. In the next chapter, some aspects are analyzed in detail and available techniques to solve the existing problems are referred with special emphasis in wide-band CDMA systems. Also, different building blocks will be discussed. A block diagram of the direct conversion receiver is given in Figure 3.2. Two downconversion mixers must be used for demodulation already at RF if a signal with quadrature modulation is received. Otherwise, a single-sideband signal with suppressed carrier containing quadrature information, like QPSK, would alias its own independent single-sideband channels in quadrature over each other as discussed earlier. This can be understood as the signal contains different information below and above the carrier frequency, which should not interfere with each other. Hence, the RF mixers are already a part of the demodulator although several other processing steps are performed before the detection of bits. This is also a distinct benefit of the direct conversion scheme, because the information at both sides of the carrier comes from the same source having an equal power. Hence, the image power is always the same with the desired signal and the quadrature accuracy requirements are only moderate as given in the previous chapter. Thus, the required image rejection is realizable with IC technologies even at high frequencies. A lowpass filter with a bandwidth of half the symbol rate is suitable for channel selection. This can be implemented with an active on-chip structure. Because the signal power is located at both sides of the carrier a DSB noise figure is applicable in downconversion mixers. This gives a noise advantage over the other architectures, and also no image noise filtering is needed between the LNA and mixers. The external components in the signal path are now limited to the preselection filter at the input. Hence, only the input of the LNA must be matched in order to maintain the filter response unchanged. The interfaces between other blocks can be optimized during the design independently to optimize the performance with respect to noise, linearity and power. Of course, flexibility also increases the design complexity.

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The drawbacks of the direct conversion, which limit the dynamic range and hence use in many applications, can be divided into two main categories. First, the interference can be exactly at dc. It can be removed for example with a very narrow highpass filter discussed in the next chapter. Second, the distortion can be located around or close to dc but has a certain frequency response, which covers a larger portion of the spectrum at the same band with the received channel. The response can also vary in time, which makes it impossible or at least very difficult to separate from the desired signal. Direct conversion receivers suffer from the fact that the gain before the conversion to baseband is relatively small, which means that the amplification required at the baseband before the detector or ADC is large, typically in the order of 60100 dB. The gain at RF can not be increased arbitrarily, not only because of the unreasonable power consumption but also mainly due to the linearity constraint. Several different nonidealities are shown in Figure 3.3.

The constant dc offsets come either from the inevitable component mismatches in the differential signal path or from the self-mixing of the LO signal. The latter is caused by the leakage of the LO signal to the input of the mixers, which mixes then with itself and generates a constant dc offset. The coupling mechanisms include capacitive coupling, coupling through substrate and inductive coupling, for example through bondwires if the LO is brought from an off-chip source to the mixers. The LO can leak directly to the RF port of the mixers or to the input of the LNA. In the latter case, the leakage will be amplified by the gain of the LNA. The leaked LO signal can also propagate to antenna because of the finite reverse isolation of the LNA and preselection filter and reflect back from the interfaces having mismatch. Finally, if the LO radiates from the antenna and reflects from other objects back to the receiver, the offset due to self-mixing varies in time. Also, the dc offset varies if initial conditions in the receiver change. The abrupt change in the LO frequency or gain setting typically charges or discharges

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memory elements i.e. capacitors, requires a finite settling time, and defines a new level for the offset. The dc offset has two possible consequences. If not cancelled out, it will be amplified in the receiver like the incoming signal. In the worst case, the offset compresses the circuits at the back-end of the receiver and hinders the detection. If this is prevented by the automatic gain control, the amplification may be too low for the detection of a weak signal from the quantization noise of the detector. The offset component can be considered also as an in-band interferer if not removed with special techniques. Some cancellation techniques will be discussed in the next chapter. The settling time is a typical trade-off in those schemes. The possible offset due to self-mixing can be estimated using the LO level in the mixers, LO-to-RF isolation and gain of the receiver. A typical isolation is 60 to 70 dB, and the required LO level approximately 0 dBm from a source. Hence, the LO leakage at the RF input is from -70 dBm to -60 dBm. If the total gain is 100 dB from which 30 dB is at RF, the voltage swings at the input and output of the baseband are and respectively. The output values are definitely not acceptable, but in this example it was assumed that the signal would reflect completely back from the input of the LNA. The sensitivity to offsets is however evident, and some cancellation method is practically always adopted in analog circuitry. The spurious emissions from the antenna outside the transmission band are typically regulated in the system specifications to avoid the interference in other radio equipment. In direct conversion receivers, the radiation of the LO signal from the antenna is susceptible to produce interference because the leaked LO is attenuated only by the passband loss of the preselection filter between the input of the LNA and antenna. For example, in GSM specifications the maximal spurious emissions caused by the receiver are 2 nW i.e. -57 dBm at the band from 9 kHz to 1 GHz and 20 nW from 1 GHz to 12.75 GHz [29]. Those conditions are met in the example given above. The interference, which has frequency response around dc, has three main sources: flicker noise, envelope distortion and self-mixing of RF. They will be considered separately in the next chapter with respect to the circuit design issues. Flicker noise originates from the baseband circuitry, and should be taken into account already in the downconversion mixers. Especially in narrow-band receivers with a small RF gain, flicker noise can be the dominant noise mechanism as given in the previous chapter. RF self-mixing exists when an unwanted channel couples to the LO port of the mixer and modulates the LO signal. The signal mixes with itself producing a replica around dc at the passband of the desired channel. Another mechanism, which produces a signal-dependent component at or around dc is the second-order nonlinearity as described in the previous chapter. The source of the distortion in both cases can be located at any possible frequency passing the preselection filter, or actually it is a combined effect of all transmissions within one system. A conceptual view of the two different mechanisms and their sources in a direct conversion receiver is given in Figure 3.4. Ideal multiplication is assumed in the mixer. Linear and nonlinear signal processing paths are drawn in parallel only to distinguish the desired and unwanted functions. The LO-to-RF leakage is placed before the nonlinear elements, but the choice is arbitrary because it can be assumed that the products of higher harmonics are negligible compared to the fundamental self-mixing product. Before analyzing the different effects the concept of amplitude modulation must be reviewed briefly. In the previous chapter, an RF signal carrying an amplitude envelope was given as

where is the constant part of the amplitude and the amplitude envelope, which modulates the carrier. The input signal can also have phase or frequency modulated

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components, but they are neglected in the given equation. In the constellation diagram, they appear as a rotation of vector with a constant magnitude around the origin. If the modulated signal has a constant envelope, like GMSK, m is zero. Otherwise, the modulation caries a variable envelope, like QPSK, and the spectrum of the envelope spreads around the carrier of the modulated channel. Second-order nonlinearity generates two replicas of the modulated channel, one at dc and the other at as

Hence, a part of the envelope is converted down to dc due to the second-order nonlinearity and occupies a bandwidth relative to the modulation. A weak signal can be buried under the downconverted envelope preventing the detection. The channels having a constant envelope can produce only a dc component relative to the square of the input power as seen from Equation (3.5). A modulated channel is not the only possible source of envelope distortion. Timedependent effects like changes in the transmitted power, especially the power ups of new channels, establish amplitude variations although the envelope is constant during the transmission of data bits. Also, fading in the radio path should be considered as a source of envelope variations. Envelope distortion with respect to the circuit design parameters and selected modulations will be discussed in the next chapter.

The envelope distortion generated due to the second-order nonlinearity follows a different propagation path than the received channel because it is never at the same frequency except after the conversion to the baseband. Also, the baseband and double-frequency components should be considered separately in Figure 3.4. The received channel proceeds through the RF amplifier, downconversion mixer and baseband amplifier having a total gain of before the channel selection. The envelope distortion at RF is split into two blocks, because accoupling can be used to block the baseband part of the distortion before the mixers. However, there are often active circuits between the coupling capacitors and the commutating switches, like current sources or active input stages stacked in the same supply current path. They can not be removed before the conversion. An ideal mixer upconverts the components from the vicinity of dc and downconverts the distortion from the double-frequency to the LO. Hence, they can be

84

injected to the output only by secondary effects. The leakage of the baseband signal to the output is given with in Figure 3.4. It is caused by the deviation from the 50 % duty cycle in the commutating switches. The sources can be nonidealities in the switching device, in the LO signal or in the output load. The selected mixer topology determines the susceptibility to these issues. The switches contribute also second-order nonlinearity to the output. They are included together with the baseband circuitry. The envelope distortion is an issue at the baseband in before sufficient filtering of other channels. The double-frequency component generated at RF can convert down with the second harmonic of the LO signal. The second harmonic is however typically much smaller than the fundamental tone and it converts only the second harmonic of the desired channel directly down to the baseband. This is probably not a serious issue in the direct conversion scheme, but the conversion of noise from the second harmonic may degrade the sensitivity slightly. If the arbitrary time delay in Figure 3.4 is zero, the self-mixing behaves like envelope distortion. Only the term in Equation (3.5) will be replaced with The terms and describe the RF gain, conversion gain of the mixer and RF-to-LO isolation, respectively. The leakage must be small because the preceding gain is typically in the order of 25 to 30 dB. Hence, dominates the performance if it is not much smaller than in the given presentation because the signal is the same in both cases. However, the two measures are not directly comparable, and the argumentation alleviates only the significance of both parameters, which are difficult to distinguish in the practical implementations. The above discussion assumed correlated signals in the unwanted operations. It is true if the signal is squared in a nonlinear element. However, the time delay shifts mixed data streams with respect to each other. Hence, the information is not perfectly correlated any more in the case of selfmixing. Probably, this is not very significant if the consecutive symbols can be located at any possible constellation points with an equal probability. However, in the transmission of a constant envelope signal all transitions are not possible. The time shift can spread the envelope spectrum from a fixed dc offset in the case of self-mixing because different relative transitions in the time-domain are possible. The type of modulation and its filtering in the transmitter not only define the bandwidth of the channel selection filter, but also give specific requirements for the downconversion mixers and the analog baseband processing in direct conversion receivers. The spectral shape of the modulated channel has a direct impact on the possibilities to remove dc offsets. This has been utilized in paging systems, which use binary frequency-shift keying (BFSK). The notch in the power at the carrier frequency allows significantly relaxed highpass filtering possibilities for example compared to QPSK or GMSK discussed in the previous chapter. The systems using modulations having a constant envelope are basically insensitive to wide-band envelope distortion, but this does not guarantee the protection against envelope problems. A third factor is the filtering of the modulated channel in the transmitter. For example, the envelope of a QPSK signal transmitted using root-raised cosine filtering differs from the system level raised cosine filter, which is a combination of the transmitter and receiver filters. This must be taken into account when envelope distortion is evaluated. Examples of amplitude envelopes in different cases will be given in the next chapter. Another parameter, which limits the RF-to-LO leakage besides of self-mixing is the LO pulling. It means that a strong near-by interferer, for example an adjacent channel, leaks to the oscillator and injection locks the VCO to a slightly different frequency. The LO pulling must be prevented almost perfectly because of the tight frequency stability requirements in cellular systems.

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3.3

Low-IF

A low-IF receiver violates the first IF selection criteria of the superheterodyne receiver given in Equation (3.1), but does not convert the signal directly down to baseband either. Hence, a lowIF receiver can be defined based on the first IF as

Frequency is the center frequency of a modulated channel. To avoid the self-aliasing of the radio channel due to the conversion on the both sides of the dc, the lower limit in Equation (3.6) should be Two different choices of the IF are given in Figure 3.5. If the lowest IF next to dc is chosen, flicker noise, self-mixing and envelope distortion should be considered. Those topics will be discussed in the next chapter, which describes the direct conversion architecture in detail. In the discussion of low-IF receivers, especially the effects of amplitude envelope and self-mixing are often totally neglected. The power maximum is not at dc after the downconversion, but the spectrally efficient modulations, like QPSK with a roll-off 0.22 in WCDMA, do not allow much space between dc and the lower edge of the modulated channel. The flicker noise contribution is probably negligible at least in wide-band systems, but the signal envelope and self-mixing are of interest. A distinct benefit of low-IF compared to direct conversion is the insignificance of the static dc offset component, which can be removed without severely deteriorating the modulated channel. If the maximal power of the adjacent channel is much smaller than the other in-band channels, like in GSM, the lowest possible IF is a sensible choice, because the image rejection requirements are relaxed. It does not suffer from the half IF problem either. Flicker noise, self-mixing and envelope distortion can be avoided if a higher IF is chosen. It has two significant drawbacks compared to previous. Half IF is a potential problem due to the second-order nonlinearity, and the image rejection requirements can be much higher as shown in Figure 3.5. A strict image rejection requirement is the major drawback of the architecture, which speaks for the choice of IF next to dc. Another option is to select a LO which has the image between two adjacent channels. This gives a significant advantage in the systems, which have a relatively loose channel spacing and smooth pulse shaping filters.

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A block diagram of the low-IF receiver is given in Figure 3.6. The signal is divided into quadrature branches in the first downconversion. Otherwise, the unwanted image is inseparable from the desired channel. The channel selection is performed with a bandpass filter. Because of the low frequency operation it can be integrated if the IF is located close to dc. In principle, a lowpass response is sufficient for the IF next to dc, but a bandpass filter removes also static offsets and is therefore preferable. The unwanted image can be cancelled and I/Q data detected either with complex filtering at the low IF or with real filters and four mixers at the final conversion to baseband [28]. These blocks are not shown in Figure 3.6. The background of the complex signal processing is described in [29]. Passive sequence asymmetric polyphase filters are examples of analog filters, which are suitable for selection of positive and negative frequencies in the processing of complex signals [30]. At low frequencies, a complex filter can be synthesized with any available implementation technique, like an active-RC or switchedcapacitor (SC). The digitization of an analog signal does not require extra bits or increased oversampling if the image is cancelled before the A/D-conversion. The dynamic range between the desired channel and the image should be added to the digital word length if cancellation is performed digitally. The image noise at the output of the LNA is damped like the image channel, and therefore practically negligible. However, the SSB noise figure is a correct definition for the two independent downconversion mixers at the system level.

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The specification of the image rejection ratio is not unambiguous, because it depends on the chosen IF and the system requirements. The system specifications cover the spectral mask, but do not give direct values for acceptable image levels, because they are not a problem in a standard superheterodyne reception. Therefore, the specification must be calculated from several independent prerequisites, and select the worst case condition. In the previous chapter, one possible method was given. It assumed a 3-dB rise of the signal level compared to the sensitivity specification and allowed that the image can contribute an equal amount of in-band interference as noise. An example is taken from the GSM specifications. The signal must be approximately 9 dB above all unwanted in-band interferers in all cases, and the maximum power levels at one, two and three channels away are 9, 41 and 49 dB above the desired channel, respectively. Hence, the IRR must be 18 dB to attenuate the adjacent channel to the acceptable level if it is located at the image frequency. In that case, the signal located two channels away from the desired is adjacent to the image. If required that it should be only 9 dB above the desired channel IRR must be 32 dB, which dominates the performance. Other channels are not significant with this selection. If the image is two channels away from the desired, the IRR specification is 50 dB using the same argumentation. Constant IRR curves are plotted in Figure 3.7. They indicate the acceptable amplitude and phase errors for fixed IRR requirements. The equation is given in the previous chapter.

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Mismatches in analog circuits are inevitable and limit the image rejection. A high IRR performance is not possible without special techniques even in modern IC processes. The mismatch due to cut-off frequencies in analog filters is possible to circumvent with wider bandwidths than necessary and adding extra bits in the A/D conversion. In the digital domain the critical operations can be performed with a higher precision. The gain mismatch between low frequency signal paths can be compensated with AGCs, but the phase and especially amplitude errors in high frequency structures need special attention in the low-IF architecture. With a double quadrature downconverter in Figure 3.8, a phase error less than 0.3 and an amplitude error of 0.5 dB is achieved from 500 to 900 MHz without any external tuning or trimming [31]. Also, digital techniques using reference signals or blind adaptive cancellation are developed [32], [33], [34]. They compensate the I/Q imbalance in the digital domain. The reported schemes predict 15 to over 20-dB improvement in the image cancellation. A modification of the low-IF is the double-low-IF architecture [35]. It uses the Weaver architecture, but converts the low-IF signal up to a fixed IF in the second pair of mixers and subtracts the I and Q branches before the channel selection. Hence, the image frequencies are located again around both sides of the LO, but instead of RF, at a relatively low frequency, and the desired channel can be separated with a bandpass filter. The topology requires quadrature LOs for both mixers, and a lowpass filter to remove the image of the second LO before upconversion. At the output of the second IF, a 50-dB image rejection was reported although the same group has given conflicting results of only 23-dB IRR for a slightly different setup in [36]. However, they claim that the performance meets the GSM specifications. The same approach has been earlier proposed for the direct conversion [37]. The signal is first converted down to a zero IF and then upconverted using a Weaver architecture to a low IF.

A DCS-1800 front-end using CMOS has been developed based on the low-IF topology [38], It includes the LNA, quadrature mixers, lowpass filters and AGCs in the signal path, and VCO, synthesizer and quadrature generation structures. Also, a modulator and an RF preamplifier for a direct conversion transmitter are implemented on the same die. The lowest possible IF, i.e. 100 kHz, was chosen and the reported phase and amplitude accuracy of the I/Q branches is 0.6 and 0.4 dB, respectively. A new version of the receiver is given in [39]. The reported worst-case IRR was 32.2 dB and the power consumption excluding synthesizer was 113 mW from a 2 V
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supply. The noise figure of 8.2 dB still suffers strongly on the flicker noise at 100 kHz. The 10bit ADCs, final digital channel selection and demodulation are placed on a separate chip. Another example of low-IF is a GPS receiver implemented also with CMOS [40]. In GPS, the CDMA transmissions using consumer and military codes are broadcast at the same 20 MHz band around 1.57542 GHz. The consumer code occupies however only 2 MHz of bandwidth, and no other interferer than the military GPS exists at the same band. The military code uses larger bandwidth and therefore smaller power spectral density. Hence, the image includes only a side-lobe of the modulated consumer channel and a portion of the military channel if a low IF, like 2 MHz, is chosen. Therefore, the low-IF architecture is a sensible choice without the image rejection problem for commercial GPS applications.

3.4

Wide-Band IF

An image-rejection receiver suitable for integration, which utilizes two consecutive downconversion stages but performs the channel selection completely after the second downconversion, is proposed to reduce the problems of image signal or direct conversion to the baseband [41]. Actually, the same idea has been given already in [42]. The first LO was set to or In the former, the second stage uses the same LO in quadrature. The latter generates the second quadrature LO of from the first with two flip-flops and an inverter. The background for the proposal was to avoid the LO-to-RF leakage and self-mixing problems of direct conversion. However, no experimental results were given on the paper. The second approach is reported recently for a paging receiver in [43]. Originally the topology was called as a dual-conversion or quasi-IF and later as a wide-band IF. The architecture, which has been implemented with CMOS, is given in Figure 3.9 [44]. It is actually the same architecture as invented by Weaver with the exception of the quadrature information recovery in the second downconversion stage. The arrangement of the second downconversion is however the same complex mixer as can be used in the back-end of a low-IF receiver instead of a complex filter as mentioned in the previous section. The difference with the low-IF and a distinct benefit of the architecture is the adaptation of such a high IF that the image is outside the passband of the preselection filter. Hence, the image is an out-of-band signal, which is attenuated before the active circuitry. This allows feasible specifications for the IRR in a wider range of applications. The wide-band IF architecture follows exactly the same frequency selection criteria for the first IF as superheterodyne including the half IF issue. If the second mixer stage does not convert the signal directly down to baseband, the secondary image is a potential problem [9]. Also, the inband image channel is then a problem in the second downconversion, like in the low-IF. However, all designs except of one referred in this section use a zero IF after the mixers. The channel selection filters are placed after the second downconversion. The lowpass filters between the mixers are only needed to suppress the upconverted product generated in the first downconversion. Typically, the limited output bandwidth of the RF mixers together with the interconnection to the second mixing stage attenuate the high-frequency products sufficiently without any extra components. The desired sideband can be easily chosen when the polarities of the signals are reversed before the summation at the baseband [44]. The property has been adopted using carefully selected frequencies to minimize the hardware in a dual-band receiver [45]. The wide-band IF does not necessitate the Weaver architecture. A single mixer can be used to convert the signal to the first IF, and quadrature mixers perform the final downconversion [46]. The structure saves three mixers, but mandates all image rejection to the selectivity of the preselection filter and the LNA load, which has a high Q in this case.

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A fixed first IF was proposed in [44], which relaxes the phase noise requirements of the highfrequency LO. A wide-band phase-locked loop (PLL) can be used to suppress the phase noise to an acceptable level, because no fast settling times are required. Instead, the second LO must have higher relative tuning range, and the spurs from the PLL may mix with undesired strong signals at IF producing distortion at the channel of interest. The fixed first IF is however not a necessary condition for the wide-band IF. The desired channel can be converted to a fixed IF with the VCO at RF as well. The use of two high-frequency LOs rises in any case the demand of a careful frequency plan discussed for example in [45]. The LO-to-RF leakage is however less important, because the first LO is outside the passband of the preselection filter like in superheterodyne. Both the low-IF and direct conversion architectures can produce unacceptable emissions to the antenna due to the insufficient LO-to-antenna isolation. The wide-band IF topologies transfer the typical downconversion problems of a direct conversion into the second mixer stage. The only difference is that the critical operation frequency is scaled down by a factor of 2 to 20. The distortion generated around dc in the first mixers is not significant because the portion, which passes the possible ac-coupling between the stages, is mainly upconverted in the second mixers. Hence, the most critical blocks are the second mixers. They must handle all radio channels passing the preselection filter, which means that the linearity is a major concern. The lower operation frequency allows some more flexibility in the transistor sizing, a smaller parasitic loading of different nodes, and possibly better matching between components. Otherwise, the problems are equivalent with the direct conversion. The second-order nonlinearity causes envelope distortion around dc, and flicker noise can degrade the sensitivity at the output of the baseband. Therefore the benefit of the wide-band IF architecture compared to the direct conversion is subject to the fact whether it is possible to increase the gain before the conversion to the baseband without degrading the overall linearity or at least perform the same amplification with a smaller power consumption. Linearity becomes more critical when the gain increases, and the characterization should include both IIP3 and IIP2. It means that the wide-band IF trades-off with the similar problems as the other receivers suitable for full integration having a slightly different prerequisites. Neither the possibilities to optimize the performance using a controlled gain at RF or IF change significantly because all interfering channels are present before the final conversion down to dc. The different recently reported implementations are compared in Table 3.2. The total voltage gain before the conversion to the baseband including the gain of the second mixers is in the range of 23-35 dB, which is comparable to the typical values in direct conversion receivers.

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At the baseband, the signal must be amplified to the appropriate level for the detector or ADC, which means that the overall gain of the analog receiver should be the same as with any other architecture using a similar interface to DSP. Hence, the problems of static dc offsets due to mismatches are not avoided if the combined RF and IF gain is not increased compared to the RF gain in direct conversion. The self-conversion of the second LO is however less significant if assumed that the parasitic coupling to the input of the mixer is smaller at lower frequencies. The same applies also for the self-mixing of the input signals. The correct definition for the noise figure of different mixers is of importance. The first mixers convert only one sideband down to IF while both sidebands carry information in the downconversion to the baseband. Therefore, the SSB noise figure is correct for the first mixing stage while DSB should be used in the second stage. The LNA contributes noise only from one sideband if quadrature downconversion is used or the selectivity of the LNA load suppresses the other sideband sufficiently. Recently, dual conversion and low-IF are combined in [47]. The out-of-band image rejection for a 190 MHz first IF is 75 dB including 40 dB in the preselection filter. The in-band image rejection at a second IF of 5-15 MHz is 55 dB. The high numbers have been achieved using altogether 11 polyphase stages at both LOs and IFs. Five of them are located at the second LO providing the in-band IRR.

3.5 Direct Digital And Digital IF

Digital signal processing would provide significant benefits compared to analog circuitry if the conversion to digital will be brought closer to the antenna. The matching problems of quadrature branches are avoided as well as dc offset and flicker noise when the downconversion to baseband is performed digitally. However, the problems associated with the analog-to-digital conversion and downconversion of the IF or RF signal are difficult to solve even with submicron technologies. The increased resolution and speed requirements to the power consumption of the A/D converters will be discussed in the next chapter. Also, the increased complexity of digital circuitry should be considered carefully in the implementations. To

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achieve the benefits mentioned above a higher speed, better resolution and more digital gates are needed, which means at least a larger chip area and higher power consumption. Whether the trade-off is reasonable or not using current technologies will not be considered here any further. In this section, different approaches of digital receivers and general limitations of subsampling techniques in radio receivers will be discussed. Subsampling can also replace a conventional RF mixer, but the fundamental restrictions are basically similar compared to the digital approach. An RF subsampling mixer will be described in the two following chapters. In principle, the digital receivers can follow any of the architectures discussed above with respect to the frequency planning or filtering arrangements. Here, the alternatives are limited only to the digital IF in superheterodyne and digital RF in direct conversion. Hence, both include only one digital downconversion stage. Block diagrams of the digital IF and RF receivers are given in Figure 3.10. Later the term digital baseband will be used in connection with the A/D conversion. It means that practically all filtering except of antialiasing is performed digitally, but the desired channel is downconverted either at the baseband or at some low IF in the analog domain. The both topologies in Figure 3.10 actually assume that the Nyquist-rate sampling is adopted in the ADC. Hence, especially at RF digitization the sampling rate must be unreasonably large i.e. 2-4 GHz in typical cellular systems, but aliasing at the input of the ADC would not be a problem. There are no reported Nyquist-rate ADCs capable of RF reception and only few converters operating at or above 100 MS/s with 10 to 14 bits resolution [48], [49], [50]. Those are capable of digital IF reception if their resolution is sufficient for the specific application. In wireless systems, the band of interest is much narrower than the Nyquist rate in sampling. Hence, the bandpass converters are more suitable for digital receivers in cellular applications [51]. They provide a large resolution only at a narrow band, but can tolerate large interferers within the Nyquist rate. Extensive research effort has been paid recently on those systems. For a 200 kHz radio channel an 11-bit ADC has been reported using 200 MHz IF [52]. For larger bandwidths, a 58-dB dynamic range is achieved in modulator using 85 MHz IF and 1.25 MHz input band [53]. A flexible input bandwidth up to 70 MHz using 55.5 MHz IF and 4 GHz sampling rate is reported in [54]. The feasibility of a digital RF receiver using modulator is studied in [55]. The modulator converts 200 kHz bandwidth at 950 MHz using 3.8 GHz clock frequency. These examples show that digital IF receivers are already potential candidates in some applications, but ADC connected directly to RF front-end is still a futuristic vision.

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Instead of sampling at twice the RF or IF frequency, a bandlimited signal can be also sampled at a lower rate. The information will not be aliased when the sampling rate is higher than twice the signal bandwidth at the input of the sampler. Such a block is often called as a subharmonic sampler or a subsampling mixer. Subsampling allows a significantly lower clock rate, and hence potentially a lower power consumption. This discussion is limited only to mixing in an RF front-end, but subsampling can be adopted also in the downconversion from IF with less stringent requirements [51]. Subsampling mixers have been used especially in microwave test instruments [56], but several experiments have also been established for wireless receiver applications. The subsampling mixer has been used as a stand-alone RF downconverter block in [57] and [58]. Higher linearity has been reported compared to a Gilbert-cell bipolar mixer. However, noise behavior is fundamentally poorer in bandpass sampling applications because of aliasing [59]. This is clearly a dominant problem, and in both cases the reported noise figure is higher compared to more conventional mixer structures. The subsampling mixer is also a passive structure and does not provide any gain, which would protect the receiver from noise of the successive blocks. A discrete-time analog front-end consisting of a downconversion stage using subsampling and a narrow-band filter suffered from the 47 dB noise figure, which is absolutely too high despite of any realistic RF amplification [60]. Subsampling is also used in a RF demodulator for a short-distance portable terminal [61]. Direct digitization using a subsampling ADC has been shown to be suitable for GPS reception in [62] and [63]. Noise aliasing is the most severe problem in the subsampling RF front-end. A simple model to estimate the performance is given in Figure 3.11. In the case of a wideband input, noise is limited by the first-order RC lowpass network consisting of a hold capacitor and a switch resistance in the conduction state The total noise of the sample-and-hold structure in the

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discrete-time signal processing is at the output All that noise will be aliased within the Nyquist rate in the sampling. Hence, the spot noise at the baseband can be written as

Noise figure of the subsampling mixer can be calculated from that by comparing the sampling noise to the noise spectral density of the source resistance Thus, the noise factor is

The formula assumes that the gain of the desired signal is unity. It means that the RF signal is well below the cutoff frequency of the sampler input bandwidth. Otherwise, the attenuation of the RF input signal degrades the noise figure. Hence, in the case of RF subsampling the pole of the sampler must be at the GHz-range. Basically, sampling rates of 50-100 MHz are sufficient to prevent aliasing of the signals after the preselection filter, but the noise figure is still unreasonably high at that range as shown in Figure 3.12(a). The possible capacitor values for RF subsampling are around 1 pF, because the series resistance of the sampling switch can not be made infinitely small with any applicable technology. Hence, the realistic noise figures for RF subsampling mixers range between 15-25 dB. This may be acceptable in some cases. However, the noise from the preceding stages will also alias in the subsampling process. It means that noise should be bandlimited before the mixer. This can be done either with a RF bandpass filter or a narrow-band LNA. The external RF filters require typically matched interface to the sampler to maintain the frequency response. A separate buffering stage is probably needed for matching, which on the other hand produces additional wide-band noise. A narrow-band LNA may not be as efficient as a filter but the hold capacitor can be a part of the resonator. A method to optimize the interface between the LNA and a subsampler is given in [64]. The structure will be described in detail in chapter 5. Here, an estimate for the noise figure of the front-end will be given based on the equivalent noise bandwidth, of the LNA. It can be calculated separately from the transfer function of the LNA. The presentation is simplifying because it assumes that the noise spectrum is flat within the Nyquist rate at all frequencies. For example, with high-Q resonators this is not the case. However, a practical estimate for the noise factor of a subsampling front-end can be given as

where is the voltage gain of the RF amplifier and the voltage gain of the matching network, which is ideally 0.5. The noise figure of the front-end is plotted as a function of the ratio between the noise bandwidth and Nyquist rate in Figure 3.12(b). Matching is assumed to be ideal, and the noise figure and voltage gain of the LNA are 3 dB and 20 dB, respectively. Three curves are plotted describing the noise figures of a subsampling mixer including the internal noise aliasing. It is evident that a subsampling front-end would be feasible for wireless applications only if the filtering is very sharp or the noise figure requirements very loose. The aliasing of the input noise is clearly the dominant source in the noise figure rather than the internal noise of the mixer in most cases. An efficient technique to reduce noise aliasing due to LNA but to maintain a relatively slow sampling speed in a CMOS track-and-hold circuit is described in [65]. The technological limitations including restrictions in high-speed sampling

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and high-Q RF resonators limit the possibilities to utilize the subsampling approach. Hence, it can not compete with conventional RF front-ends, but the same principle applied to IF signal processing is more realistic. A schematic of the subsampling front-end with all required functional blocks is given in Figure 3.13. In principle, the following signal processing can be digital after an immediate A/D conversion, analog discrete-time or continuous-time. In the latter case, the clock harmonics should be filtered out like double LO components in a traditional mixer.

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The subsampling concept is mainly limited by noise, but there are other important differences as well compared to traditional receivers or mixers. The noise analysis presented above is simplifying and takes only the noise of the sampling switch and LNA into account. Other noise sources like the LO noise coupled to the output due a to time-varying channel conductance in a MOS switch is analyzed in [66]. As discussed earlier a higher linearity can be achieved than with other mixer topologies. A thorough analysis of the distortion in CMOS RF and IF samplers is given in [67] using time-varying Volterra series, and the results are utilized in an IF digitizer [68]. The clock jitter in high-speed systems is a distinct problem and comparable to the phase noise in oscillators controlling switching mixers or multipliers. Fundamental requirements for high-speed sampling are analyzed in [69]. In the case of a subsampling mixer, jitter requirements for the clock come from the high frequency input signal rather than from a slower sampling rate [51], [60]. Hence, the requirements resemble RF oscillators and differ from the Nyquist rate sampling. In a commutating mixer, the signals at dc or close to it will be ideally upconverted around LO, and only a small portion will leak through switches into output. In a sampling mixer this is not the case. All signals located at the baseband at the input of the mixer will not be attenuated compared to the downconversion product at the output. Therefore especially in the direct downconversion, the LNA and mixer must be only ac-coupled. The coupling scheme must block all components effectively over the desired signal band around dc. Otherwise, the secondorder intermodulation of the LNA would be also critical for the performance. A coupling method, which is capable to suppress MHz-range baseband signals using a small capacitor is given in [64] and discussed in chapter 5. Small coupling capacitor values are important in a standard CMOS process because the bottom-plate parasitics would otherwise limit the RF bandwidth significantly. Division into quadrature is also problematic in the case of subsampling because the 90-phase shift at RF can not be performed with a comparable phase shift at the sampling rate i.e. at LO. Naturally, the phase shift can be done for the RF signal, but due to the loss and inaccuracy in the operation it should be avoided. The required phase shift for the LO reduces when the subsampling ratio increases and may be difficult to implement accurately. Two different sampling arrangements have been proposed, which can solve the problem without increasing the complexity significantly [70], [71].

3.6

Comparison of Architectures

A summary of the characteristic benefits and drawbacks of the different radio architectures are given in Table 3.3. Sometimes two alternatives are given, because different precautions may apply depending on the design choices. Benefits are marked with plusses and drawbacks or challenges with minuses. The table should be considered only instructive, and it reflects the discussion given in the earlier sections. The digital receiver approaches are not included because they are merely technological possibilities to perform some functions digitally, which have been traditionally done in the analog domain. The digital signal processing has different prerequisites, and therefore the comparison would not be objective. It is not reasonable to make any order between different architectures either. The choice is always a complex function of the earlier experience and the characteristics of the specific system.

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[22] F. Piazza, Q. Huang, A 170 MHz RF Front-End for ERMES Pager Applications, IEEE J. Solid-State Circuits, vol. 30, pp. 1430-1437, December 1995. R. G. Meyer, W. D. Mack, J. J. E. M. Hageraats, A 2.5-GHz BiCMOS Transceiver [23] for Wireless LANs, IEEE J. Solid-State Circuits, vol. 32, pp. 2097-2104, December 1997. [24] J. A. Macedo, M. A. Copeland, A 1.9-GHz Silicon Receiver with Monolithic Image Filtering, IEEE J. Solid-State Circuits, vol. 33, pp. 378-386, March 1998. [25] D. G. Tucker, The History of the Homodyne and Synchrodyne, J. of British Inst. of Radio Engineers, vol. 14, pp. 143-154, April 1954. [26] A. A. Abidi, Direct-Conversion Radio Tranceivers for Digital Communications, IEEE J. Solid-State Circuits, vol. 30, pp. 1399-1410, December 1995. [27] B. Razavi, Design Considerations for Direct-Conversion Receivers, IEEE Trans. on Circuits and Syst.II: Analog and Digital Signal Processing, vol. 44, pp. 428-435, June 1997. [28] J. Crols, M. S. J. Steyaert, Low-IF Topologies for High-Performance Analog Front Ends of Fully Integrated Receivers, IEEE Trans. on Circuits and Syst.II: Analog and Digital Signal Processing, vol. 45, pp. 269-282, March 1998. [29] J. Crols, M. Steyaert, CMOS Wireless Transceiver Design, Boston, Dordrecht, London: Kluwer, 1997. [30] M. J. Gingell, Single Sideband Modulation Using Sequence Asymmetric Polyphase Networks, Electrical Communication, vol. 48, pp. 21-25, 1973. J. Crols, M. S. J. Steyaert, A Single-Chip 900 MHz CMOS Receiver Front-End with a [31] High Performance Low-IF Topology, IEEE J. Solid-State Circuits, vol. 30, pp. 1483-1492, December 1995. [32] J. M. Pez-Borallo, F. J. Casajs Quirs, Self Adjusting Digital Image Rejection Receiver for Mobile Communications, in Proceedings of the IEEE Vehicular Technology Conference, vol. 2, pp. 686-690, May 1997. [33] J. P. F. Glas, Digital I/Q Imbalance Compensation in a Low-IF Receiver, in Proceedings of the IEEE Global Telecommunications Conference, vol. 3, pp. 1461-1466, November 1998. [34] L. Yu, W. M. Snelgrove, A Novel Adaptive Mismatch Cancellation System for Quadrature IF Radio Receivers, IEEE Trans. on Circuits and Syst.II: Analog and Digital Signal Processing, vol. 46, pp. 789-801, June 1999.

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M. Banu, H. Wang, M. Seidel, M. Tarsio, W. Fischer, J. Glas, A. Dec, V. Boccuzzi, [35] A BiCMOS Double-Low-IF Receiver for GSM, in Proceedings of the IEEE Custom Integrated Circuits Conf., pp. 521-524, May 1997. V. Boccuzzi, J. Glas, Testing the Double Low-IF Receiver Architecture, in [36] Proceedings of the IEEE Int. Symp. on Personal, Indoor and Mobile Radio Communications, vol. 1, pp. 370-374, September 1998. T. Okanobu, D. Yamazaki, C. Nishi, A New Radio Receiver System for Personal [37] Communications, IEEE Trans, on Consumer Electronics, vol. 41, pp. 795-803, August 1995. M. Steyaert, M. Borremans, J. Janssens, B. D. Muer, N. Itoh, J. Craninckx, J. Crols, E. [38] Morifuji, H. S. Momose, W. Sansen, A Single-Chip CMOS Tranceiver for DCS-1800 Wireless Communications, in ISSCC Digest of Technical Papers, pp. 48-49, February 1998. M. Steyaert, J. Janssens, B. D. Muer, M. Borremans, N. Itoh, A 2V CMOS Cellular [39] Transceiver Front-End, in ISSCC Digest of Technical Papers, pp. 142-143, February 2000. D. K. Schaeffer, A. R. Shahani, S. S. Mohan, H. Samavati, H. R. Rategh, M. d. M. [40] Hershenson, M. Xu, C. P. Yue, D. J. Eddleman, T. H. Lee, A 115-mW, CMOS GPS Receiver with Wide Dynamic-Range Active Filters, IEEE J. Solid-State Circuits, vol. 33, pp. 2219-2231, December 1998. P. R. Gray, R. G. Meyer, Future Directions in Silicon ICs for RF Personal [41] Communications, in Proceedings of the IEEE Custom Integrated Circuits Conf., pp. 83-90, May 1995. U. Bolliger, W. Vollenweider, Some Experiments on Direct-Conversion Receivers, [42] in Proc. of the EEE International Conference on Radio Receivers and Associated Systems, pp. 40-44, July 1990. S. A. Sanielevici, K. R. Cioffi, B. Ahrari, P. S. Stephenson, D. L. Skoglund, M. [43] Zargari, A 900-MHz Transceiver Chipset for Two-Way Paging Applications, IEEE J. SolidState Circuits, vol. 33, pp. 2160-2168, December 1998. J. C. Rudell, J.-J. Ou, T. B. Cho, G. Chien, F. Brianti, J. A. Weldon, P. R. Gray, A [44] 1.9-GHz Wide-Band IF Double Conversion CMOS Receiver for Cordless Telephone Applications, IEEE J. Solid-State Circuits, vol. 32, pp. 2071-2088, December 1997. S. Wu, B. Razavi, A 900-MHz/1.8-GHz CMOS Receiver for Dual-Band [45] Applications, IEEE J. Solid-State Circuits, vol. 33, pp. 2178-2185, December 1998. H. Darabi, A. A. Abidi, An Ultralow Power Single-Chip CMOS 900 MHz Receiver [46] for Wireless Paging, in Proceedings of the IEEE Custom Integrated Circuits Conf., pp. 213216, May 1999.

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[47] F. Behbahani, J. Leete, W. Tan, Y. Kishigami, A. Karim-Sanjaani, A. Roithmeier, K. Hoshino, A. Abidi, An Adaptive 2.4GHz Low-IF Receiver in CMOS for Wideband Wireless LAN, in ISSCC Digest of Technical Papers, pp. 146-147, February 2000. C. Moreland, M. Elliot, F. Murden, J. Young, M. Hensley, R. Stop, A 14b [48] l00MSample/s 3-Stage A/D Converter, in ISSCC Digest of Technical Papers, pp. 34-35, February 2000. R. Jewett, K. Poulton, K.-C. Hsieh, J. Doernberg, "A 12b 128MSample/s ADC with [49] 0.05LSB DNL," in ISSCC Digest of Technical Papers, pp. 138-139, February 1997. K. Y. Kim, N. Kusayanagi, A. A. Abidi, "A 10-bit, 100MS/s CMOS A/D Converter", [50] IEEE J. Solid-State Circuits, vol. 32, pp. 302-311, March 1997. A. Hairapetian, An 81-MHz IF Receiver in CMOS, IEEE J. Solid-State Circuits, vol. [51] 31, pp. 1981-1986, December 1996. [52] R. Maurino, P. Mole, A 200MHz IF, 11 Bit, 4th Order Band-Pass ADC in SiGe, in Proceedings of the European Solid-State Circuits Conf., pp. 74-77, September 1999. [53] S. Bazarjani, S. Younis, J. Goldblatt, D. Butterfield, G. McAllister, S. Ciccarelli, An 85 MHz IF Bandpass Sigma-Delta Modulator for CDMA Receivers, in Proceedings of the European Solid-State Circuits Conf., pp. 266-269, September 1999. [54] G. Raghavan, J. F. Jensen, R. H. Halden, W. P. Posey, "A Bandpass Modulator with 92dB SNR and Center Frequency Continuously Programmable from 0 to 70 MHz," in ISSCC Digest of Technical Papers, pp. 214-215, February 1997. W. Gao, W. M. Snelgrove, A 950-MHz IF Second-Order Integrated LC Bandpass [55] Delta-Sigma Modulator, IEEE J. Solid-State Circuits, vol. 33, pp. 723-732, May 1998. [56] P. A. Weisskopf, Subharmonic Sampling of Microwave Signal Processing Requirements, Microwave Journal, vol. 35, pp. 239-247, May 1992. [57] P. Y. Chang, A. Rofougaran, K. A. Ahmed, A. A. Abidi, A Highly Linear l-GHz CMOS Downconversion Mixer, in Proceedings of the European Solid-State Circuits Conf., pp. 210-213, September 1993. [58] A. Prssinen, R. Magoon, S. I. Long, V. Porra, A 2-GHz Subharmonic Sampler for Signal Downconversion, IEEE Trans. on Microwave Theory and Techniques, vol. 45, pp. 2344-2351, December 1997. [59] R. G. Vaughan, N. L. Scott, D. R. White, The Theory of Bandpass Sampling, IEEE Trans. on Signal Processing, vol. 39, pp. 1973-1984, September 1991.

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[60] D. H. Shen, C.-M. Hwang, B. B. Lusignan, B. A. Wooley, A 900-MHz RF Front-End with Integrated Discrete-Time Filtering, IEEE J. Solid-State Circuits, vol. 31, pp. 1945-1953, December 1996. [61] S. Sheng, L. Lynn, J. Peroulas, K. Stone, I. ODonnell, R. Brodersen, A Low-Power CMOS Chipset for Spread-Spectrum Communications, in ISSCC Digest of Technical Papers, pp. 346-347, February 1996. [62] A. Brown, B. Wolt, Digital L-Band Receiver Architecture with Direct RF Sampling, in Proceedings of the IEEE Position Location and Navigation Symp., pp. 209-215, April 1994. [63] D. M. Akos, J. B. Y. Tsui, Design and Implementation of a Direct Digitization GPS Receiver Front End, IEEE Trans. on Microwave Theory and Techniques, vol. 44, pp. 23342339, December 1996. A. Prssinen, S. Lindfors, J. Ryynnen, S. I. Long, K. Halonen, 1.8 GHz CMOS LNA [64] with On-Chip DC-Coupling for a Subsampling Direct Conversion Front-End, in Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 2, pp. 73-76, June 1998. S. Lindfors, A. Prssinen, J. Ryynnen, K. Halonen, A Novel Technique for Noise [65] Reduction in CMOS Subsamplers, in Proceedings of the IEEE International Symposium on Circuits and Systems, vol. 1, pp. 257-260, June 1998. W. Yu, B. H. Leung, Noise Analysis for Sampling Mixer Using Stochastic [66] Differential Equations, IEEE Trans. on Circuits and Syst.II: Analog and Digital Signal Processing, vol. 46, pp. 699-704, June 1999. [67] W. Yu, S. Sen, B. H. Leung, Distortion Analysis of MOS Track-and-Hold Sampling Mixers Using Time-Varying Volterra Series, IEEE Trans. on Circuits and Syst.II: Analog and Digital Signal Processing, vol. 46, pp. 101-113, February 1999. A. Namdar, B. H. Leung, A 400-MHz, 12-bit, 18-mW, IF Digitizer with Mixer Inside [68] a Sigma-Delta Modulator Loop, IEEE J. Solid-State Circuits, vol. 34, pp. 1765-1776, December 1999. M. Shinagawa, Y. Akazawa, T. Wakimoto, Jitter Analysis of High-Speed Sampling [69] Systems, IEEE J. Solid-State Circuits, vol. 25, pp. 220-224, February 1990. J.-E. Eklund, R. Arvidsson, A Multiple Sampling, Single A/D Conversion Technique [70] for I/Q Demodulation in CMOS, IEEE J. Solid-State Circuits, vol. 31, pp. 1987-1994, December 1996. D. T. S. Darwin, C. C. Ling, A 200-MHz CMOS I/Q Downconverter, IEEE Trans. [71] on Circuits and Syst.II: Analog and Digital Signal Processing, vol. 46, pp. 808-810, June 1999.
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Direct Conversion Receivers

This chapter introduces the design specific issues for a direct conversion receiver operating in wide-band CDMA systems. The emphasis is in the characteristic nonidealities with respect to the CDMA, in the optimization of the receiver architecture and in the building blocks. From the nonidealities described in the previous section dc offsets and envelope distortion are alleviated. Some comments are also given on the evolution of circuit structures for digital receivers and on the design of single-chip structures having digital circuitry on the same die with an RF frontend. Finally, some reported direct conversion receivers and their properties are referred. The designed IC structures presented in the next chapter rely on this discussion, and many design choices are justified in this chapter.

4.1

Direct Conversion in Wide-Band Systems

The direct conversion architecture is an attractive candidate for wide-band CDMA receivers for several reasons. First, the radio channels have wider bandwidths, which makes the contribution of flicker noise less significant, and the filtering of the dc component is easier because a smaller portion of the spectrum is removed with the same highpass filter. Second, a larger dynamic range is achieved because of the processing gain. The signal may lie inside the noise i.e. have a negative signal-to-noise ratio before despreading. Hence, the distortion from an unwanted interferer should be compared to the noise rather than the signal. The dynamic range is improved by the amount of processing gain when it is taken into account. In the case of a negative signal-to-noise ratio, a larger interferer compared to the power at the desired traffic channel is acceptable with the same IIP3. Also, the transmitted power levels can be reduced because it is possible to detect the signal when buried in noise. In the case of smaller power levels the nonlinear effects are less significant. These issues are discussed already in chapter 2, and the benefit may be lost for example when non-CDMA systems are operated at the same band or close to it. A third reason for the use of direct conversion is that the despreading of the desired channel spreads the narrow-band interferers or notches as wide-band, noise-like signals within the chip rate. This happens even if they vary in time. The despreaded signal is actually an average of a bit sequence, and hence less susceptible to individual errors. On the other hand, the CDMA transmission is typically continuous, which rules out some design methods to compensate internal nonidealities. The drawbacks and their possible contributions should be considered carefully also in the case of CDMA. Some important design trade-offs are given in the following subsections.

4.1.1

DC Offsets and Flicker Noise

The problems and sources of different dc offsets were recognized and different solutions given already in the early attempts of direct conversion. In pager applications using 2-FSK with a deep and wide notch between the two power maximums, a highpass filter is an obvious choice to block any dc component before the detection [1]. Before discussing about different offset cancellation methods, the different types of offsets and their effects in different cases should be categorized. The dc offset is by definition a component, which is located exactly at the zero frequency. For example, it can be measured as a voltage difference between the positive and negative output

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nodes in a differential circuit. However, the offset is not necessarily constant all the time. Therefore the time-invariant and time-variant effects should be separated. Time-invariant offsets consist of nonidealities in the circuitry like component mismatches between differential branches, or a slow temperature drift. They are constant as long as the internal settings of the receiver are unchanged. The offset varies each time when the gain or LO frequency is changed abruptly during the reception. Therefore offset levels must be redefined after rapid changes. The amount of offset variation depends on the implementation. An example of the measured performance is given in [2]. The offset varies at the output of the mixer less than when the LO is swept over a 300 MHz range at 1 GHz. This is only 3 % of the mean offset value of 3 mV and therefore probably insignificant. The LO self-mixing has been considered as a main contributor to the time-variant offset, because the amount of self-mixing may vary due to changed reflection coefficient for example when the antenna is touched, or due to radiation from the antenna and reflection back to the receiver from a moving object. A third phenomena, which is not typically considered as a timevariant dc offset is the constant part of the second-order distortion or RF self-mixing as depicted in the previous chapter. However, it meets similar precautions as the LO self-mixing, because the component is located exactly at dc and can vary slowly in time according to the incoming amplitude. A modulated signal with a constant envelope produces only the dc component when detecting even-order nonlinearity while in the case of a variable envelope, a part of the power spreads over a wider bandwidth. This spread portion creates the phenomena, which is considered as an envelope or AM distortion, and can not be separated with conventional offset cancellation methods discussed in this section. Also, any other abrupt change in the input amplitude of the receiver generates a variable envelope. The AM part of any interference should not be mixed up with a time-variant offset. The envelope distortion and its sources will be discussed separately in the next subsection. What is then the definition, which separates time-variant offsets from the envelope distortion? An unambiguous categorization is not possible. The changes in time-variant offset are however so slow that the differences in the levels of subsequent symbols are negligible. This depends also on the properties of the detector and specific modulation. Spectrally the limit can be defined as a portion of the baseband spectrum, which can be removed around dc without causing significant deterioration in the reception in static conditions. Due to different modulations and transmission quality requirements the acceptable offset cancellation range needs to be specified separately in each case. The time-domain and frequency-domain concepts are illustrated in Figure 4.1.

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As given above the acceptable dc offset depends on the demodulator. The BER as a function of is simulated for the in [3], for the quaternary PAM in [4] and for the 16-QAM in [5]. All of them indicated that a reasonable loss from ideal behavior requires dc offset levels, which are only a few percentages of the detected signal i.e. -20...-25 dBc at the input of the demodulator. However, these numbers are significantly smaller than the potential offsets at the output of the analog receiver as discussed in the previous chapter when the desired channel is close to the sensitivity level and gain is at maximum. The offset of a few millivolts can be 50-70 dB above the weak signal at the output of the downconversion mixers. Hence, there should be an offset cancellation mechanism, which can remove large offsets and then compensate the residual part of the time-invariant and time-variant offsets to an acceptable level before the detection. The offset above the largest signal level increases the dynamic range requirements of the analog back-end stages and the A/D conversion, and the word length or clock rate in DSP. It is one of the parameters, which must be taken into account when dc offset compensation arrangements are developed. The most obvious method to prevent the propagation and amplification of the dc offsets is the ac-coupling. Often a highpass filter is used for that purpose. The filter with a first-order highpass function performs the same band limitation as an ac-coupling capacitor driving a resistive node. Hence, the different terms are used alternatively also here. If the filter has higher-order transfer characteristics it will be noted separately. As given above, the FSK modulations in paging systems are suitable for ac-coupling because of the appropriate spectral shape. However, the slow data rates and narrow channel bandwidths require a narrow notch around dc. Unreasonably large component values for the integration are needed to produce the notch below 1 kHz with a passive CR-network. Therefore the coupling capacitors are typically external although active dc blocks are also developed to reduce the sizes of passive components like in [6]. Still 330 pF on-chip capacitors are required to produce the notch. Another solution to the on-chip ac-coupling is given in [7]. Two 10 pF capacitors are needed to produce a 10 kHz notch in a single quadrature branch. The systems using more efficient modulations like QPSK or GMSK have the power maximum at dc in the modulated spectrum and therefore the filtering possibilities are more limited. A

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good rule of thumb is that 0.1 % or less with respect to the data rate can be removed from the spectrum around dc without deteriorating the performance too much [8], [9], [10], [11]. However, wide-band DS-SS systems are less sensitive to the DC notch although using spectrally efficient modulations. The spreading operation codes each bit over a pseudorandom sequence, which means that the loss of one information bit is an average over a period rather than a failure in a single transmission in the constellation. The averaging works better when the processing gain increases. In chapter 2, the simulated curves for the bit-error-rate were given in the case of two different highpass filters. The spreaded data allows the removal of the dc from a wider band compared to the data rate, and actually to the chip rate as well. About 1 % of the spectrum can be removed compared to the chip rate without a significant loss even when processing gain is only 6 dB. That is probably the worst case condition because the highest data rate transmissions require BER in the order of and it must be achieved at a small processing gain. The wide bandwidths and the averaging property of the DS-CDMA are clear benefits from the implementation point of view. Corresponding results are also given in [12] for a cordless system operating at the 1.2 MHz baseband channel having a 30 kHz notch. Another consequence of the high cutoff frequency in the ac-coupling is unreasonable group delay variations, which increase ISI [8], [13]. The latter reference however avoids the problem in the cordless application by using a suitable signal coding, which allows fast settling in the timedivision duplexing although using a high cutoff frequency. In the subsection of channel filtering, it will be shown that the estimated deterioration of ISI due to the 2 kHz highpass cutoff is not very significant in the WCDMA receiver. Also demodulators, which are not very sensitive to the group delay, can be constructed as [14]. Instead of ac-coupling in the signal path, the cancellation can be implemented with a feedback loop over one or several baseband stages in the receiver. The servo feedback loop has lowpass characteristics, and the negative feedback reduces the closed-loop gain at low frequencies canceling the dc offset. The feedback loop has been applied for offset cancellation at least in [12], [15], [16] and [17]. The ac-coupling methods are efficient when the offset is removed in static conditions. The drawback of the ac-coupling or filtering is the slow settling in large signal conditions like abrupt changes in power levels at the input or internal gain control steps in the receiver [9], [18]. The same trade-off applies also to dc cancellation with a feedback. The loop gain is always a compromise between the settling time and the amount of offset cancellation [12]. The settling can be sped up by disconnecting the signal when the output signal goes out of the acceptable range, and then new values are charged to the coupling capacitors when the timeconstants are reduced by many orders of magnitude. The technique has been used in [9]. However the 2 ms compensation procedure causes an instant loss of several bits in continuous transmission. Alternatively, the capacitor in the ac-coupling structure is placed between differential nodes in [6]. The method speeds up the turn-on of the receiver and is insensitive to changes in the common-mode levels, but does not allow any benefit against differential offsets. The large analog component values, removal of a large portion of the signal spectrum, and group delay distortion are limitations, which call for alternative solutions. The constant offset can be removed with a very long term averaging process [19]. When the long-time average is subtracted from the incoming signal the bandwidth of the notch around dc can be only few hertz. This is however again a trade-off with the rate of change in the dc value. Hence, rapid changes in the offset can not be removed. In the digital averaging process and periodic discretetime correction, the group delay is almost unaffected due to the notch [8]. With a specific averaging technique the offset of less than 20 mV at the output of the receiver has been achieved in [20]. The acceptable offset with the maximum gain at the input of the baseband block is in that case. The approach is discussed in [21]. Also small wobbling or dithering of the LO frequency around carrier, which can be cancelled afterwards, has been
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proposed to average out the effect of the notch [19]. However, an example of its efficiency has not been given. In burst-mode communications, like GSM or DECT using TDMA, the reception is not continuous. Hence, the internal offsets of the receiver can be stored during idle time slots and subtracted during the transmission [11]. The values at different gain settings can be also collected in a memory table and the specific offset is subtracted from the incoming signal [22]. Also, the rough offset compensation can be performed at the beginning of each frame either as a part of the cancellation algorithm [18] or sampling and subtracting it from the incoming signal during the burst before the ADC [23]. An algorithm, which is suitable for canceling high offset levels of 40 dB above the signal, is given for a 4-FSK signal in [24]. The dc component can be estimated using oversampling from a few tens of information bits in parallel with the demodulation. The specific demodulator is also quite insensitive to offsets because a 65 % offset compared to signal is acceptable without a significant deterioration. In continuous-time systems, like WCDMA, idle time intervals can not be utilized for compensation. Hence, the highpass filtering or long-time averaging methods, which are both sensitive to time-variant offsets, are available. The WCDMA direct conversion receiver described in the next chapter uses a servo feedback offset compensation with a 2-kHz cutoff. The method removes efficiently large static offsets at the input of the receiver. The time-variant offsets, for example due to the digital gain control, should be compensated separately in the digital domain. In the measurements, the offset level changed but remained well inside the ADC operation range when digital gain steps were tested. Also, the 1.5 MHz sinusoidal test signal was only slightly distorted during the 6-dB gain step and recovered within one period of the time-domain waveform. The LO self-mixing component can vary the offset frequency because of the Doppler shift when generated due to the backward reflection from a moving object. This can be eliminated in the burst-mode transmission if the offset is compensated frequently enough i.e. the offset is almost constant over each frame or other period, which defines the interval of compensation. In the continuous-time reception it may cause an additional constraint when the offset is compensated with a highpass filter [25]. However, the estimation of the worst-case conditions is difficult. Especially, the ratio of the shifted offset component compared to the maximum dc offset value depends on several antenna and operation environment specific issues. Therefore, a proper estimate would require field-testing, and the topic is not discussed any further. The methods given above are mainly concerned structures, which can remove offsets larger than the signal. Those are needed to limit the number of bits in the A/D conversion, and perform an initial cancellation. The residual may however require additional cancellation in the digital domain. Typically, the adaptive digital methods can cope with offsets of 50 % or less from the detected signal, but the loss after the cancellation can be almost negligible compared to an ideal detector. The remaining offset should be then only a few percent or less from the signal. The convergence speed is a critical factor in compensation. In [9], the dc is reconstructed by calculating the average length of the constellation vector i.e. the shift from the origin over a long period and the result is compared with the incoming symbols. Fast convergence can be achieved if a known preamble can be used to estimate offset for example in the beginning of the data burst [4]. Only 5-20 symbols are needed to correct offsets up to 40 % of the desired signal to an acceptable level. Preamble has been used for the correction of the residual also in [23]. If a preamble is not available the offset can be also averaged over the whole burst, and subtract the average from the next slot [22]. This is possible when the offset varies within acceptable levels between successive bursts. The method given in [18] is memoryless and is capable of tolerating large offsets as well. The response is fast, and the cancellation can be performed before A/D conversion after the initial offset level is detected in the beginning of the burst. Hence, the

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dynamic range requirements of the ADC remain reasonable. The fast convergence in the previous examples is based on the known behavior before the random data is detected. In continuous transmission, this may not be possible. An adaptive algorithm capable of operating in continuous conditions is described in [5]. The least mean square (LMS) algorithm requires more than 100 symbols for compensation, and therefore the response may be too slow when offset changes abruptly. The carrier offset is the shift of the LO frequency from the center of the channel. It is a combination of the small frequency errors in the synthesizers both in the transmitter and receiver. Again, the acceptable range depends on the certain modulation, symbol rate and the specific detector. A fluctuating carrier offset is a source of additional phase error and must be taken into account in the clock recovery. The effect of the carrier offset and automatic frequency control (AFC) methods in various systems are discussed for example in [3], [14], [26] and [27]. The carrier offset at the input of the receiver gives frequency stability specifications for the synthesizer together with the tolerable range of the detector. Both issues are however unimportant for the design of the analog signal path in the direct conversion receiver and therefore omitted here. The presence of flicker noise at the signal band immediately at the output of the downconversion mixers is a significant drawback of the direct conversion architecture. The effect was discussed and highpass filtering proposed to reduce the problem already in the early trials of the concept in [28]. The linearity requirements limit the acceptable RF gain typically to 25 to 35 dB in the front-end, and hence the effect of flicker noise can not be eliminated increasing the gain. The fundamentally higher noise level and the simultaneous requirement of excellent linearity at baseband before the sufficient suppression of interferers make a trade-off, which needs increased power consumption. Therefore the benefit compared to the superheterodyne, which is achieved through the lower operation frequency and thus lower parasitic leakage after the first downconversion, is partly lost. The wide-band channel in WCDMA introduces even more difficult demands although the flicker noise contribution is reduced to some extent. The optimization of the dynamic range requires careful selection and sizing of devices with respect to the power consumption. Different aspects will be discussed in the following sections.

4.1.2

Envelope Distortion

The background of the envelope distortion, called also as even-order or AM distortion, is given already in the two previous chapters. This subsection is focused to estimate different sources of the envelope distortion, and the amount of amplitude envelope in selected cases. Finally, the relationship between the envelope distortion and the second-order input intercept point (IIP2) is calculated in the case of a modulated channel with a constant power level. The discussion is concentrated only on the spectral components, which alias over the desired channel outside dc. The dc part of the distortion is covered already in the previous subsection. Also, the mechanism of the envelope distortion is squaring rather than RF self-mixing in this context. In the former case, the phase of the carrier is insignificant as depicted in [29]. The amount of self-mixing however depends on the delay in the leaked signal compared to the input of the mixer. In principle, the opposite phase may cancel the effect as well. In balanced mixers, the amount of self-mixing depends only on the differential leakage to the LO ports. The common-mode part, which is very likely much larger than the differential portion in integrated structures, is cancelled at the differential output with a proper common-mode rejection ratio (CMRR). On the other hand, the common-mode leakage modulates the LO, thus exhibiting AM-to-PM conversion in commutating switches, and possibly a larger leakage of the low-frequency signals

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to the output of the mixer. The mixer structures for direct conversion receivers will be discussed later in subsection 4.3.2 and in section 4.4. A definite explanation of the AM demodulation in direct conversion receivers including the demand of excellent balancing to cancel the effect was given already in [9]. The squaring removes the phase information in the case of even-order distortion i.e. the distortion is always a common-mode signal, and hence the envelope is detected only due to the imbalances in the differential structures. Also, the reference [30] discusses the issue, but gives only a measure that a 30 dBm signal with a 95 % AM content gives no audible hum in the analog receiver. An initial estimate for the IIP2 specification was given for a QPSK system in [31], and the spectral shape of the baseband beat was sketched roughly in [21] and [32]. However, the amount of the envelope distortion compared to the modulated signal was not quantified in those cases. Practical aspects and circuit structures to improve balance or prevent the low frequency beat components from propagating to the input terminals of the commutating switches are given in [7], [29], [31], [33]. Unfortunately, all those examples give only intuitive and sensible explanations, but not a detailed analysis of the behavior in downconversion mixers even in a simplified case. The significance of balancing and the unpredictable nature of the phenomenon in practical circuits are typically mentioned without further considerations of the matter as in [15]. It should be also remembered that not all radio systems are sensitive to the envelope distortion as will be discussed below. In this subsection, some crucial aspects of the system level issues will be given, while in section 4.4 the symmetry requirements of the active mixer structures are estimated with respect to the specified IIP2. The sources of AM distortion in cellular systems originate either in AM components at the modulated channels or in time transients due to the transmission of unwanted channels. The former is a problem only in AM modulated analog transmissions and in digital transmissions using non-constant envelopes, like QPSK. The latter is more likely an issue in burst-mode communications as is the case with TDMA, for example in GSM. The source of AM distortion can be at any frequency because the modulation spreads around dc always when the signal is squared and lies within the reception band in the direct conversion receiver if the difference of the beat components is equal or less than half of the signal band. Hence, it is appropriate to assume a single dominant source to present the worst case conditions and the source can be any of those discussed above. However, the discussion is limited here only within a single radio system at a time because at least theoretically the preselection filter removes sufficiently all outof-band interferers. The envelope distortion in a real radio environment was studied for a paging system in [34]. The measurements were performed both for static and fading conditions at the 280 MHz band. The nearby television broadcast was a potential source of AM distortion in that case but the amount of envelope was unknown. The analysis technique differed from the conventional IIP2 methods, but from the given values it can be calculated backwards that in the case of static conditions the measured envelope was about 20 dB below the interferer. On the other hand, the measurements in the fading environment indicate that the envelope was almost equal with the interferer. This adds one additional parameter for the specification of IIP2, which is typically not available for the circuit designer. Maybe therefore, the effect of fading is a rarely discussed issue in the case of integrated direct conversion receivers. Also, the results given in [34] do not give much insight on the matter. A more straightforward approach to estimate the problem from the system point of view is the envelope of a modulated radio channel in static conditions. This can be simulated quite easily with different softwares having tools for modulated channels. The envelope detector is simply a squaring circuit, and the results can be compared straightforwardly to IIP2 calculations when the undesired power to the total channel power is estimated. In Figure 4.2, the envelope of a

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QPSK channel is simulated for 4.0 Msymb/s using a root-raised cosine filter with a 0.22 rolloff. The power of the envelope is referred to the total power of the modulated radio channel. The thick line describes the total cumulative envelope power up to a certain frequency. The maximum cumulative power of 10.5 dBc is achieved at about 4 MHz frequency, but at 2 MHz the total power is only 15 dBc. It means that a significant part of the envelope distortion is filtered out in the channel selection, which relaxes the requirement of IIP2. From now on, the envelope power, is defined as the power of the modulated channel, which is aliased within the band of interest. The given description presents a situation averaged over a long period, because a large number of bits must be simulated to achieve the spectral shape of the envelope. Actually, the peak power in the envelope can cause a detection of a false bit. Hence, the probability of certain peak power levels in the modulated channel should be considered rather than an average of the envelope, and BER simulations are finally needed to find the IIP2 specification for the direct conversion receiver. Another method to describe the amount of amplitude envelope in the modulated channel is the crest factor, which means the peak to effective amplitude ratio. It can be also used to define the dynamic range of the ADC. The envelope power, differs from the crest factor because the bandwidth dimension is taken into account, but both relate directly to the properties of the modulation and filtering in the transmitter. However, both measures require also some function describing what is the probability of a certain peak or envelope power. This probability function is not directly related to the BER of the receiver, and hence a more detailed analysis is needed. In CDMA communications, the envelope of a single traffic channel is not as important as the total traffic in the same radio channel. Thus, several properly coded data channels should be simulated simultaneously to find the correct envelope or to calculate the crest factor. Some issues on the crest factor, and especially the peak limited dynamic range of ADC, are analyzed for several uncorrelated QPSK signals in [35].

The envelope powers have been also measured using a signal generator producing different digital modulations. The device under the test was a standalone BiCMOS mixer with emitter followers buffering the output. The mixer was driven into compression and therefore the linearity is badly degraded. The nonlinear distortion was hence clearly visible and the interest was only to compare the differences between modulations and transmitter filters. Because the input power of the mixer was the same in all cases, the absolute value of the IIP2 was not important. The output signal of the QPSK modulated channel at a 25-MHz IF is given in Figure 4.3. The output bandwidth of the setup was about 30 MHz and the mixer did not limit the

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bandwidth in this case. The envelope distortion around the dc and the third-order distortion on the both sides of the IF are clearly present. The cumulative powers of BPSK, QPSK and 256-QAM modulations are shown in Figure 4.4(a). All channels have equal symbol rate and root raised cosine filtering with a rolloff of 0.22. The smaller envelope of the QPSK channel is explained with a smaller probability to cross the origin in the constellation diagram. With the BPSK it happens always when the value of the bit changes, and the 256-QAM modulation produces about the same total envelope power as BPSK. Interestingly the slope at low frequencies is however not equal. The shape of the QPSK signal follows well the earlier simulation. The QPSK signal is measured also when the rolloff of the transmission filter is changed. The effect of increased envelope power with narrower filtering is evident in Figure 4.4(b). The rapid rise in the cumulative power at 4 MHz is due to the feedthrough of the data clock. The cumulative power bends up already below 10 MHz because of the 15-MHz IF in the two last plots.

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The variable envelope is not necessarily the worst case situation for the AM detection. The time-division multiple access has caused more severe problems in GSM. The abrupt change in the transmitted power level causes an AM component, which can be detected in the direct conversion receiver. Especially, this becomes severe when the transmission is bursty. The nearby transmitter switches frequently on and off at another channel in a TDMA system. Because the unwanted source is not necessarily synchronized to the desired channel, the switching can happen during the reception of the data bits. To prevent the detection of this large envelope the IIP2 of a GSM receiver must be in the range of 46-50 dB [36], [37]. Hence despite of the constant envelope in the modulation, GSM is one of the most difficult systems to realize with the direct conversion architecture. Of course, the transients must be characterized carefully in the IIP2 specifications when new traffic channels are inserted or transmitted power is changed also in CDMA systems. However, they are less susceptible to cause any problems although the reception is continuous. Some theoretical curves of envelope power behavior in the time domain are shown in Figure 4.5. All changes in the y-axis indicate always amplitude envelope, and the straight line presents the case when a vector with a fixed amplitude rotates around the origin in the constellation diagram.

The discussion has been limited so far only to the amount of envelope in some specific cases. Next, some comments will be given on the two-tone test as a method to define the beat tone and how it relates to the envelope power. In the two-tone test, the sum of the sinusoidal RF test signals with an amplitude A at frequencies and can be given as

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where The equation has the characteristics of double-sideband suppressed-carrier AM modulation at the frequency of The lowpass filtered part of the squared signal can be then given as

The power of a single test tone in the matched case is where is the source resistance. The envelope power in the low frequency beat according to Equation (4.2) is then twice the input power in the two-tone test i.e. dB in decibels. This must be taken into account when the two-tone test is compared to the envelope powers of the modulated channels given above. The part of the distortion, which leaks to the output is referred to the input as If the inputs in the two-tone test have different power levels, it is straightforward to show that the cosine term depends on the smaller amplitude and the difference increases only the DC component. The connection of the IIP2 to the system specifications is reviewed briefly. In cellular and cordless systems the maximal interference level is typically specified for the signal, which is 3 dB above the reference sensitivity level, of the receiver as

where N and I are the input referred noise and interferer power levels in decibels, respectively. To keep the BER unchanged, the interference can be at the same level with the noise. If we assume that the interference is dominated by the envelope distortion determined with IIP2, the input power can be defined from the equation

where G is the gain of the system, and are the measured outputs, and is the input referred value of the second-order distortion. Combining Equations (4.3) and (4.4) the largest acceptable input power of the interferer is

where the signal-to-noise ratio, which here is equal to the signal-to-interference ratio, is the minimum to achieve a certain BER with a specific modulation. The envelope power has been however 3 dB above the input power in the test. The last three terms in the summation actually present the noise power at the sensitivity level as given in chapter 2. Processing gain improves the immunity in the spread-spectrum systems. It has been shown that the specification of the acceptable immunity against envelope distortion is much more than a characterization of some specific test tones. A modulated channel or some other test may model the behavior well in practical cases, but the appropriate case for the worst case conditions would not be easy to find because of a large variety of different parameters. The two-tone test is still a simple and possible test for the envelope distortion but different power levels and test frequencies should be defined than for the third-order intermodulation. This has not been done in most of the specifications because they are mainly meant only for the

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superheterodyne architecture, or the specifications have been completed later when problems occur. The complexity is often increased in new wireless systems, but typically the focus is quite far from the analog part of the radio receiver. To benefit from the advantages of direct conversion architecture, a deep understanding of the complete system is necessary also for RF designers. The role as a part of the demodulator and the large number of other DCR specific issues are hence an essential part of the analog IC design in communications circuits, which can not be omitted. The following sections relate some of these issues into the circuit design, and the main focus is in the implementation of integrated direct conversion receivers and their individual blocks.

4.2

Radio Design

The design of the direct conversion receiver is based here on the initial specifications of the 3rd generation WCDMA wireless system. The most significant change to the original proposal is the reduction of the 4.096 Mcps spreading rate to 3.84 Mcps. The two implementations use the former chip rate, but the same design could be utilized when the sampling rate of the ADCs is reduced and the poles and zeros in the channel selection filter are scaled for the new cutoff frequency. The latter would require naturally a new processing round. The channel spacing is however not altered during the specification process. The direct conversion receiver is the first reported prototype for the WCDMA system, and it was originally published as a chip set in [38]. The RF bandwidth of the system was designed large enough that the same chip can be used in test beds both for base stations and mobile terminals. Later the same structures were placed on the single-chip version of the direct conversion receiver including the signal path from LNA to ADCs [39]. An external synthesizer is used to generate the LO for downconversion mixers. Many issues were still open in the specifications during the design, and therefore the results can not be directly applied to the recent versions of the specification. The initial design goal was also more likely to maximize the overall performance with the modern IC technology rather than follow strictly a list of detailed specifications. The functional prototype was a more important design goal than a small power consumption, for example. The chips were implemented with a 25 GHz BiCMOS process. The process had four wiring layers providing high-quality metal-insulatormetal (MIM) capacitors and inductors with low resistive losses. As an exception the A/D converters in the chip set used a CMOS technology. Details of the circuit design will be given in the next chapter. In this section, more general issues on the receiver optimization will be given, and grounds for some topological and system level choices are given. The main emphasis is in the optimization of the RF front-end, and especially in the downconversion. Analog baseband processing and A/D converters are only mentioned briefly. The dynamic range of the receiver was optimized in the receiver according to the gain diagram in Figure 4.6. The thick lines present the maximum and minimum voltage gains of the desired channel. The respective gains for the interfering signals at 3, 5 and 10 MHz offsets are given in the case of maximum gain with dashed lines. The gain control mechanism will be explained in the next chapter.

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4.3

Functional Blocks in Direct Conversion Receivers

The functional blocks of direct conversion receivers from low-noise amplifier (LNA) to A/D converters will be discussed next in the separate subsections. Also, the different structures for quadrature generation are described although the synthesizer including the VCO will not be covered. In analog baseband processing, only the response of the channel selection filter is of interest in this context. The controlled gain at the baseband is merged with filtering, and will be explained in the next chapter.

4.3.1

Low-Noise Amplifiers

In direct conversion receivers, the low-noise amplifier provides typically most of the gain before the conversion down to the baseband. Therefore the high gain without a significant degradation in linearity is required. This must be achieved together with a low noise figure. Typically, the noise figure of less than 3 dB is required from the LNA, but the trend has been recently towards 2 dB or even less. The discussion is limited here only to basic topologies of one-stage LNAs implemented either with bipolar or MOS devices. The recent results show that both bipolar and CMOS LNAs can have noise figures of less than 2 dB [40], [41], [42] and [43]. In the direct conversion architecture, the LNA drives directly the input port of the mixer, because external components are not needed. Hence, matching is not required and actually the LNA is driving a node, which consists of its own load and the input impedances of two mixers including parasitic loading. Hence, voltage gain is the appropriate definition as discussed in chapter 2, and the measurement of a stand-alone LNA would require a separate buffering stage.

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Therefore LNAs used in direct conversion receivers are seldom measured individually and typically the results are available only for the complete RF front-end. Common-emitter or common-source configurations are the most common topologies because, at least theoretically, very low noise figures are possible. A cascode stage is also often used to ensure stability. It also improves the reverse isolation of the LNA, which is important in DCRs. The load of the LNA is typically a resonator consisting of an inductor and either a lumped or parasitic capacitor. The inductors are however large, they may have high losses, and they may not be available, or at least not modeled, in a standard CMOS process. Therefore resistors have been sometimes adopted as loads with a reasonable cost in the noise figure [44], [45], [46]. It is also possible to use a gyrator circuit as an active inductor [47] or to compensate the losses of the inductor with a negative conductance circuit [48]. The both alternatives however degrade the noise and linearity performance significantly. The load device can be avoided using an LNA with a CMOS inverter type input stage [49]. The slower speed of the pMOS device limits the operation range in this topology. The matching of common-emitter or common-source topologies is discussed in the next subsection. A summary of some recently reported LNAs using silicon technologies is given in Table 4.1. Another LNA topology is the common-base or common-gate configuration. It allows easier matching and better reverse isolation. However, the noise figure is theoretically limited to 1.78 dB in a common-base and to 2.2 dB in a common-gate configuration only due to the input device [50]. The common-gate topology has been used sometimes in direct conversion front-ends [2], [51].

A differential signal path is used also in the low-noise amplifier. This is not an optimal solution for the power consumption, but a preferable design trade-off to suppress the common-mode distortion induced through the substrate or coupled to a sensitive RF input in a mixed-mode chip. The fully differential signal path is adopted in several reported mixed-mode receivers including an LNA on the same chip with the digital circuitry [15], [17], [39], [64]. Some

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comments on the input induced clock distortion will be given in the section 4.6 and in the next chapter discussing the single-chip version of the WCDMA receiver. Another drawback of the differential input is a need for an additional balun in front of the LNA. The loss of the balun should be added directly on the noise figure of the receiver in a practical environment. Other solution would be a preselection filter with a differential output. However, RF filters with differential outputs are not commonly available or widely used in commercial applications. A conventional common-emitter cascode LNA using two differential branches and no common tail current source was used in the WCDMA receiver. The matching network, load arrangements and other details of the topology will be given in the next chapter.

4.3.1.1

Input Matching

Matching of a common-emitter or common-source LNA is performed using two inductors and the base-emitter or gate-source capacitance of the input device. Both topologies with the most important matching components are given in Figure 4.7. The significant components are basically the same in both structures, but for example the gate resistance in a MOS LNA is typically much smaller than the base resistance in the bipolar case. The well-known equations for the matched conditions are in the case of a common-emitter topology

and

The equations come directly from the input impedance of the LNA by requiring the imaginary part to be zero and the real part to be equal with the source resistance, which is typically The resonant frequency, gives the optimum point of the matching. Principally, a differential LNA can be designed with the same method except that the source resistance is then doubled. The single-ended case can be directly applied if the differential LNA is actually only made of two individual LNAs without any virtual ground. However, the situation may vary significantly if parasitic coupling occurs between differential branches. Therefore, the isolation of differential ports is important. Most of the coupling between input ports may come from the off-chip wiring and mutual coupling between input inductors. The unwanted coupling will be discussed briefly with the measured results. The input inductor, is typically implemented with a bondwire or with a combination of the bondwire and the package pin. In the former case, the inductance value can be chosen freely with certain tolerances. The value of the bondwire can be calculated with the formula [56]

where is the permeability and dw are the length and diameter of the bondwire, respectively. For short interconnections with the standard gold wire, a good rule of thumb is 1 nH/mm. In principle, a part of the input inductance can be realized on-chip, but the resistive losses in the inductors would cause degradation in noise figure. The emitter or

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source inductors have typically much smaller values and they can be realized either on-chip or with bondwires. The latter alternative may be difficult to implement because of short bondwires.

The measurement of differential matching is slightly more complicated than with a single-ended LNA. The measured S11 is strongly dominated by an external balun if it is connected between the network analyzer and the LNA. At least the scattering parameters of the balun must be characterized separately before calculating the matching from the measured results. The reliability may not be adequate with that method. A more straightforward technique is to measure both differential ports individually and combine the results mathematically afterwards when it is known that there is a virtual ground between the two specific ports. Hence, a single differential port requires a two-port measurement in the network analyzer. Because only one differential input port should be measured in the case of matching a standard two-port network analyzer is sufficient for the purpose. Some commercially available network analyzers have four ports and allow the measurements of scattering parameters from two differential ports. They use the same mathematical calculations to define the differential performance from the four data ports as used below. The procedure to calculate the differential matching from the two-port measurements is described next. The S-parameters are measured normally for two unbalanced ports representing the differential input. Then the S-parameters are transformed to z-parameters. The input voltages, and and currents, and in the two ports are now divided into balanced and unbalanced terms because it is known that they are differential. Hence, they can be given as

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The relation between unbalanced and balanced voltages and currents can be also given with matrices:

The matrices and contain balanced and unbalanced information in separate terms. The relationship between the two new matrices can be now written as

The balanced z-parameters, which are called also as modal z-parameters, are now calculated as

The last row shows that the information of the balanced part of the signal is now in the term The other modal parameters describe the relationships between balanced and unbalanced voltages and currents or the unbalanced behavior. The modal z-parameters are next transformed back to the S-domain, and the modal parameter gives the differential matching of the circuit. is calculated from the modal z-parameters as

where

The calculations are relatively simple when only one differential port is of interest. It can be proved for example with the simulations that the given mathematical transformation for twoport S-parameters gives exactly the same result as S11 simulated for a differential input port

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when the source resistance is doubled compared to the single-ended case. Hence, the method is suitable for measurements. The measured results for the RF front-end of the direct conversion chip set are given in Figure 4.8. The S11 and S22 curves are relatively close to the differential match, which is a sign of sufficient isolation between the differential ports. The S21 and S12 curves describe the isolation between the ports. It is mainly dominated by the cross-coupling in the PCB, and the behavior can be modeled with good accuracy using coupled transmission lines in a standard RF simulation software.

4.3.2

Mixers

The RF downconversion mixer in the direct conversion requires totally different optimization approach than in other architectures. The second-order nonlinearity is often the most critical limitation, but several other parameters need special attention as well. A sufficient amplification at RF must reduce the contribution of noise from the baseband circuitry to minimum, and simultaneously provide high linearity. The noise problem relates both to the existence of flicker noise and to the inherently high noise levels of active stages, especially in filters. For those reasons, active mixers were preferred already in [10], and active mixers are adopted in most of the reported direct conversion receivers as in [6], [7], [12], [15], [31], [57] and [58], for example. Active mixers will be discussed separately in section 4.4. Passive mixers provide in general a better linearity, but also often a demand for a higher LO drive. The conventional passive structures i.e. diode or FET ring mixers are not discussed here. They have been used earlier in some test configurations [8], [9], [28], but not in recent integrated implementations. Instead, an antiparallel diode pair mixer is utilized in a direct conversion receiver to avoid the LO-to-RF leakage. This approach will be discussed in the next subsection with respect to the LO generation requirements. However, the reported results from several test circuits indicate that it is difficult to achieve high linearity simultaneously with a low noise figure [59]. Subsampling mixers are a separate subcategory of passive mixers. Their characteristic properties and design issues will be discussed separately in section 4.5.

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Another structure of interest is the four-quadrant CMOS multiplier cell in which the input transistors operate in the triode region and the LO is brought into the sources of input devices [60]. This type of a mixer is considered separately, because its principle of operation differs significantly on the active Gilbert cell mixers and passive structures. A downconversion mixer with a very high linearity but over a 30-dB noise figure has been reported with this topology up to the 1.5-GHz range [61]. The noise figure in a more recent implementation with the same topology lies still in the range of 20-dB [62]. The four-quadrant multiplier is applied in a low-IF receiver [45], which avoids partly the flicker noise problem. If the flicker noise contribution from the dc would be taken into account, the noise figure degrades even from the given numbers. Hence, the noise performance is not sufficient for direct conversion applications in most cases although the linearity, and especially the even-order performance, is potentially much better than in a bipolar based Gilbert cell. The excellent even-order linearity performance is based on the fact that the output depends linearly on the input signal even in the presence of mismatch [61]:

where is the mismatch of the preceding term, is the feedback resistor at the output opamp, and and are the differential output, input and LO signals, respectively. The mismatch at the output generates only a term, which is proportional to the square of the LO amplitude. Hence, the mixer is ideally free from the second-order nonlinearity in all cases. However, the IIP2 is not necessarily much higher than with Gilbert-cell based structures and high linearity and the lowest possible noise can not be achieved in the same bias conditions [62]. The choice of a Gilbert cell based active mixer for the WCDMA receiver was obvious due to the stringent noise requirements. The different alternatives to partition the front-end can be estimated using Figure 4.9. In the plot, the IIP3 of the LNA is nominally 5 dBm when and the solid curves present cases when IIP3 of the mixer is 0, +10 and +20 dBm, and the IIP3 of the LNA is constant. NF of the LNA is 2 dB, and the thick lines present the cases when the NF of the mixer is 10 and 20 dB, respectively. A fixed IIP3 of the LNA as a function of the gain is however not a very realistic design parameter. Hence, two other situations as defined when IIP3 of the mixer is +20 dBm. The dotted curve describes linearity when OIP3 is constant as a function of the gain and the dashed curve presents the situation when the OIP3 is inversely proportional to gain. The former is valid when the nonlinearities at input of the LNA dominate the behavior while in the latter, the output circuitry of the gain stage is dominant. Of course, in the case of a very large gain requirement a single-stage amplifier can not meet the desired performance, and the given characterization gives only little insight into the actual circuit design. Two regions are highlighted in the plot. It is assumed that about 30-dB of gain is required in the RF front-end of the direct conversion receiver to maintain the noise of the baseband circuitry at an acceptable level. Active mixers can contribute typically about 5 to 10-dB of gain with a reasonable linearity. Hence, 20- to 25-dB amplification in the LNA is sufficient. In that case, a 10 dB noise figure is still acceptable for the mixer, but 20 dB as in the recent CMOS four-quadrant multiplier [62] causes an unreasonable degradation in the noise performance. The fundamental loss of passive mixers is at least (3.9 dB), and in practical implementations 5 to 10 dB is a realistic estimate. Both the linearity of the LNA and of the mixer itself are very critical issues. The optimal choice for current IC technologies is clearly closer to the natural range of active mixers, which explains clearly the dominance of active mixers in direct conversion applications.

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The definition of the noise figure is different compared to the other architectures in direct conversion mixers. The double sideband (DSB) noise figure can be used because both image bands contain also desired signal besides of noise [2]. Theoretically, the DSB noise figure is always less than 3 dB smaller compared to the corresponding single sideband (SSB) noise figure, but 3 dB is a good rule of thumb when the noise figure is sufficiently large [63]. Another important difference in the design strategy is the interfaces to LNA and baseband, which do not need matching to The issue has already been discussed in chapter 2 from the system point of view. In the circuit design, more freedom to optimize the on-chip interfaces and their impedance levels separately is available. On the other hand, the design procedure is more complex because the contradictory requirements of different functions must be considered and optimized simultaneously. Also, the testing of stand-alone blocks is difficult. The interfaces of test equipment differ from the targeted environment causing degradation in performance. This is especially a critical issue in the RF and LO ports of the mixer. The direct conversion architecture defines evident constraints on the mixer topology. Singleended mixers can not be used for two reasons. First, the leakage of the tail current and especially the second-order beat around dc are not cancelled at the single-ended output. Second, the isolation from the single-ended LO to RF input is very limited. Single-balanced and doublebalanced architectures provide theoretically similar properties for the cancellation of the both problems mentioned above as long as the output is taken differentially. The possible RF to IF leakage is not a serious issue in the single-balanced structure because the leaked RF signals can be filtered out easily from the baseband signal at the output of the mixer. The common tradeoffs between the mixer topologies are discussed for example in [63], and some analysis is done with respect to IIP2 in section 4.4.

4.3.3

LO Generation and I/Q Balance

Although I/Q balance requirements are only moderate compared to low-IF or wide-band IF topologies they were a major concern in the early experiments of direct conversion, especially in discrete implementations. However, in some cases more than 1.5 dB amplitude and 12 phase

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imbalances were acceptable with less than 1 dB penalty in the performance [3],[14]. Hence, the required image rejection ratio would be only about 20 dB. A more realistic or at least a more conservative estimate for IRR in quadrature demodulators is about 25 dB [65], [66], [11]. It means either a 1-dB amplitude or a 6-phase imbalance requirement or a combination of 0.7 dB and 3, for example. Those numbers can be met with current IC technologies and careful design. Even a better performance is achieved with compensation algorithms like in [5] and [9]. Also a third signal path and a 120 phase shift between the channels has been proposed [67]. It allows either an effective phase or amplitude imbalance correction using a DSP algorithm. This is however very uneconomical for the implementation because a third baseband channel is required. As stated above, the acceptable I/Q-balance is not the most critical parameter in integrated direct conversion structures. Some issues must however be considered in the implementation. The choice of the quadrature generator depends on the required bandwidth and operation frequency. The imbalance must be within acceptable range over the whole band. Also, the LO leakage can be reduced with certain design choices as discussed later. Another source of frequency dependent imbalance is the mismatch of the cutoff frequencies in the baseband filters. If the cutoff frequencies between the I- and Q-channels vary only by 1 %, the phase and amplitude imbalances increase significantly from the passband value close to the cutoff. The gravity of the problem is not discussed here, but the matching of the cutoff frequencies is an additional design parameter in the analog baseband filter design. The division into quadrature branches at RF is the most critical block for the I/Q-balance. The division can be performed in principle either for the RF or LO signal. The latter is however almost always used because no additional loss exists at the signal path and only a narrow-band signal should be divided into quadrature. Two common techniques to implement a quadrature generator are a RC-CR network and a master-slave flipflop generating the 90-phase shift from a double-frequency LO [50], [68]. Also, some voltage-controlled oscillators (VCO) can provide quadrature outputs without a separate quadrature generator. A four-stage ring oscillator is an obvious option [69], [70]. Despite of the extensive research and analysis of its jitter or phase noise [71], [72], [73], [74], [75], [76], [77], the ring oscillators tend to have too high phase noise for RF applications [78], [79]. Also other types of VCOs with quadrature outputs have been implemented [80], [81], [82]. Recently, excellent phase noise results have been achieved with a multi-stage LC-oscillators connected to a ring [83]. The structure can replace the ring oscillator with a superior noise performance. The RC-CR networks provide a 90 phase shift at a wide band, but the amplitude is equal only at one frequency of The structure in Figure 4.10(a) has a relatively narrow band and the operation frequency is sensitive to absolute component values of R and C. In the case of differential input signals, the phase shift network is connected into a bridge as in Figure 4.10(b) [84]. A similar configuration with differential outputs is utilized in [85] using also an active phase corrector. The phase shift can be also included in the LO buffering. The buffers with a resistive and capacitive degeneration provide quadrature signals for two upconversion mixers in [86]. However all structures given above suffer from limited I/Q balance because of different mismatches. An effective amplitude and phase corrector for RC network is reported in [87] producing phase and amplitude errors of approximately 0.1 and 0.1 dB, respectively.

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The symmetry of an RC network is improved using a polyphase filter. A single-stage of the topology is shown in Figure 4.10(c). The sequence asymmetric polyphase networks are originally proposed for a single sideband modulator operating at the signal path [88], but they can perform the appropriate phase difference for the LO signal as well. The benefit of a polyphase network is the reduced sensitivity to the absolute values of R and C due to a symmetric structure. The balanced quadrature outputs are generated also when either the I- or Q-input port is grounded. Hence, the circuit operates as a quadrature generator [89]. The cascaded stages of polyphase networks improve the quality of quadrature signals, and the bandwidth can be increased if the frequency defined by the RC-product is varied at different stages [88]. The latter property is utilized to produce a high IRR for the wide-band signal in the low-IF configuration using altogether five polyphase stages [90]. In that case, the polyphase network improves only the quality of quadrature balance, and hence the suppression of negative frequencies. The preceding mixers have already provided the quadrature downconversion. Similar approach was proposed earlier for the low-IF receiver in [91] using an active polyphase filter described in [92]. The polyphase network can be used also to suppress the third harmonic of the LO signal, which is already divided into quadrature as given in [78]. The effect of cascaded stages is simulated and shown in Figure 4.11(a) for the amplitude balance in ideal case. The balanced input signal is fed into the in-phase (I) port through a termination and the quadrature port (Q) is grounded. The phase difference is 90 over the whole band already after the first stage as should be in the ideal case. In Figure 4.11(b), the RCproduct is changed from the nominal design value by in one- and two-stage configurations. The change is to the same direction in both stages of the two-stage network. The result indicates two reasons for the choice of a two-stage structure in the WCDMA receiver, which should cover a wide-band from 1.920 GHz to 2.170 GHz including reception bands of both the mobile terminal and the base station. First, in a one-stage network the amplitude balance changes over 1 dB between the lower and upper edge of the desired band even in the nominal case. Second, the process variations may cause unacceptable variations between the samples due to the absolute variations in the RC-product. A two-stage network provides sufficient performance even in the case of process variations. The relative bandwidths in

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different cases are collected in Table 4.2. The nominal values of R and C are and 0.8 pF, respectively. The center of the polyphase filter at 2.04 GHz is in the middle of the desired band. For comparison, the values are also defined for a two-stage network when RC-products are not the same. The differently valued resistors and in successive stages perform different resonant frequencies located in the middle of the two reception bands. However, the benefit is practically negligible in our case. Therefore the amplitude accuracy was simulated also when and The increment of the bandwidth is about 10 % when required accuracy is 0.2 dB or more. The uneven resonance values however prevent better matching over the band even in an ideal case. Hence, the differently valued RC time constants do not provide any added value in the reported WCDMA application. The absolute variation of the RC time constants from chip to chip is an important parameter when choosing the number of stages for the polyphase structure, and clearly a two-stage network is required in the case of WCDMA. Another design issue is the random process variations between the component values of the same polyphase network. The variations are typically within a few percentages, but they cause both amplitude and phase imbalance. The former is typically less significant compared to the absolute variation over the band of interest, and also the phase error remains in an acceptable level for the requirements of direct conversion. A thorough study for the polyphase networks using Monte Carlo simulations and different mismatches is given in [93].

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The major drawback of the RC phase shifting networks, including the polyphase approach, is the fundamental loss of 3 dB per stage. The loading of the network, which is typically capacitive and given as and in Figure 4.10(a), should be also designed to avoid additional attenuation of the signal. For these reasons the quadrature generator at high frequencies is typically placed in the LO signal path in direct conversion receivers. An example of the opposite approach is the pager, which uses a low-Q LC structure between the LNA and mixers for quadrature generation [6]. The use of an RC network may require additional power consumption because the attenuation must be compensated either by adding a buffering stage in front of the mixer or using a higher output swing in the VCO. The WCDMA receiver uses a two-stage polyphase filter to generate the quadrature LO signals from an external balanced input [94]. The structure provides sufficient performance over the range of interest as confirmed by the measurements. Both stages use the same nominal component values given above. The double-frequency LO approach is a wide-band structure by the nature and a good I/Q balance is possible, but it requires a higher LO frequency and a high-speed divide-by-two circuitry. This trade-off is however considered better than the RC networks in many recent designs [17], [95] and [96]. Especially, the wide input bandwidth of 950-2150 MHz in the last example does not allow narrow-band passive structures. The LO is outside the RF input band of the receiver in the double frequency configuration. This reduces the LO radiation problem because the divide-by-two circuit can be operated locally close to the downconversion mixers allowing improved possibilities to isolate the actual LO [30]. The divide-by-two structure needs a perfect 50 % duty cycle at the LO input to operate properly. The problem can be avoided with another divide-by-two operation, but the required frequency of four times the LO is probably not practical any more [68]. This is however utilized at the low-frequency channels in [96] because the double-frequency tone would otherwise fall at the passband of the receiver, and the sufficient LO is readily available to be used with the uppermost channels. A method to correct the errors in the double-frequency structure is presented using a level-locked loop in [97]. The LO radiation must be kept within acceptable limits as discussed earlier in section 3.2. The scale of the problem is discussed for different receiver configurations and radio environments in [30] and [34]. The isolation depends on the shielding of the VCO, LO-to-RF isolation of the mixer, reverse isolation of the LNA and leakage through the substrate in integrated structures. In direct conversion receivers the preselection filter provides only little attenuation, which exhibits more stringent specifications on the other structures. The off-chip LO signal may cause

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additional problems because of the mutual inductances between the bondwires and package pins. Also the finite isolation of the printed circuit board (PCB) is a potential route for the unwanted leakage. Excellent isolation can be achieved with an external LO by bringing the LO signal into the chip orthogonally to the RF wiring, and grounding the LO input properly on both sides [12], [94]. The recent results indicate over 70 dB LO-to-RF isolation at the operation band, which means less than 75 dBm LO radiation from a 5 dBm LO [39]. This is an acceptable level in most radio systems. An alternative method to double frequency LO, which avoids the in-band VCO, uses subharmonic mixers [30]. A subharmonic mixer, or more likely an even-harmonic mixer, uses a VCO, which operates at the half of the LO frequency and hence outside the system band. A conventional structure for a subharmonic mixer is an antiparallel diode pair [98]. The passive topology does not allow conversion gain, and is typically used in millimeter-wave applications to reduce the required oscillator frequency [99]. However direct conversion mixers with antiparallel diode pairs have also been developed for 1-2 GHz range applications [59], [100]. An active even-harmonic mixer is also established for direct conversion receivers using an emitter-coupled transistor pair [101]. The quadrature generation at the half frequency LO needs an unconventional structure because the 90-phase shift at the RF corresponds to a 45 shift at LO. The problem can be circumvented with quadrature generation for the RF signal as in [100] with consequences described above. Alternatively, the 45 phase shifters for the LO signals are developed in [29]. Besides of the reduction in LO radiation, the even harmonic mixers do not theoretically suffer from the LO self-mixing problem either, because the half-frequency input is cancelled when downconverted with itself. Only the second harmonic of the LO, which is much lower than the fundamental, may cause self-mixing in the ideal case. By far, the discussion is concentrated on the required I/Q balance, techniques to generate quadrature signals, and finally on some aspects on the LO radiation and self-mixing in different structures. The I/Q balance at the LO ports of the mixer is however not a measure for the quality of the quadrature signal path. The conversion efficiency of the mixer does not depend directly on the LO amplitude. Typically, a mixer is operated in a region where the conversion gain has reached the maximum value or is very close to it. For example, the slope of the gain versus the LO amplitude is less than 0.2 dB/dB in the nominal operation point of different mixer structures implemented for the WCDMA receiver. The measured gain versus LO power is shown for the single-chip WCDMA receiver in Figure 4.12. Hence, the amplitude balance of the direct conversion receiver is dominated by the mismatches at the signal path rather than the imperfections in the quadrature generator if located at the LO path. Of course, a mixing operation can be performed with a multiplier as well, and for example the Gilbert cell based topologies are multipliers when the LO drive is at a sufficiently low level. Besides of lower gain, the linearity decreases with the reduced LO in a Gilbert cell operating as a multiplier. Hence, multipliers are not discussed as potential mixers for direct conversion. The amplitude error in the LO signal is however very important because the amplitude difference, or actually the slew rate, of the signal causes unequal phase delay in the node with a limited bandwidth [102]. This leads to a problem of AM-to-PM conversion in the buffering stages and commutating switches of the downconversion mixers [50]. A limiting amplifier can be used to reduce the potential amplitude imbalances due to the process variations in a single-stage RCnetwork like in [12] and [103]. In that case the phase response of the limiting stage is critical instead of the commutating switches and the possibilities to correct the imbalance are therefore rather restricted. The AM-to-PM conversion is discussed here as a source of a fixed phase error in the signal path although the amplitude modulated distortion in the LO signal may cause more severe consequences. The harmonic content of the LO signal is another source of phase and amplitude errors in a narrow-band quadrature generator in addition to the mismatches as depicted in [50].
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4.3.4

Filtering

The channel selection filter in a direct conversion receiver can be implemented with an active lowpass filter. However, the sufficient attenuation of unwanted channels and the characteristics of matched filtering are very difficult, if not impossible, to realize simultaneously with an analog filter. Besides that the noise and linearity specifications for the baseband processing are harsh. The possible solutions for the channel selection include at least digital filtering with analog antialias stage, analog filtering with phase equalization either in analog or digital methods, combination of analog and digital filters or only an analog structure. The first alternative would require a large number of bits as discussed in chapter 2. Hence, the power consumption of a Nyquist rate converter would be unreasonable especially because the clock rate is also significantly increased. The on the other hand, have significantly smaller power consumption with high clock rates, but the signal bandwidth may not suffice in wide-band systems. It means that some analog filtering is necessary at baseband in a direct conversion WCDMA receiver. One alternative solution is to adopt directly an analog matched filter using for example switched-capacitor (SC) integrators [104]. The 8 MS/s clock rate requires still effective antialiasing before the filter, but no fast ADC is needed afterwards. More detailed analysis of analog and digital matched filters is given in [105]. Although the power consumption of digital filters scales down with the evolution of CMOS technology, the most obvious alternative for the channel selection in wide-band systems is an active analog filter based on some prototype. It should meet the two opposite criteria. First, the cutoff frequency must be low enough that it does not pass a significant amount of unwanted power to ADC. Second, the phase response should not increase ISI. Often, this is solved choosing a prototype, which meets the adjacent channel requirement with the smallest group delay indicating the phase behavior. Digital or analog phase equalization should correct the phase afterwards if the performance is not sufficient otherwise. Another strategy is to rise the cutoff frequency at higher frequencies in order to shift the peaking in the group delay out from the signal band. This typically destroys badly the channel selection function. In a WCDMA receiver, the 5th-order Butterworth filter with a separate pole at the input is a compromise of the analog approach. The performance of this topology is compared to some other prototypes in

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Table 4.3. Their properties are calculated from the arrangement in Figure 4.13 using parameters specified in chapter 2. The first row presents the ideal raised cosine response as a reference. It is evident that all analog prototypes are far from the ideal performance. Also the effect of timing errors calculated in the last column with a jitter of the sampling rate is much smaller in the ideal case. Interestingly, the group delay behavior does not directly follow the parameters calculated from the impulse response. Especially, the effect of highpass filtering in two last rows gives totally different results. As predicted earlier the 2 kHz cutoff frequency in the dc offset removal does not degrade the performance in the 5th-order Butterworth filter with a pole, and with an ideal raised cosine filter the total performance is still much better than with any other prototype. The digital signal processing in CDMA systems has effect on the filter specifications, and therefore it is not fair to speculate any longer with the acceptability of a certain prototype if the specific digital part is not included in the estimate. It is also possible to synthesize filters, which resemble the raised cosine response better than any conventional prototype [106]. In a direct conversion receiver, the channel selection filter is a part of the baseband processing block. The baseband also amplifies the signal to an appropriate level before conversion to digital. The distribution of gain and filtering is the key issue when the dynamic range of the filter is optimized. The type of the filter i.e. the IC architecture is another constraint for the dynamic range. In most cases continuous-time filters are used in reported direct conversion receivers, but also a discrete-time SC-structure has been proposed [107]. The implementation issues of continuous-time filters are discussed generally in [108] and will not be emphasized here any longer. In the WCDMA receiver the active RC topology was chosen because it provided a superior performance when both low noise and high linearity were required [16]. The gain was embedded directly in filtering stages, which minimized the number of operational amplifiers and optimized the linearity. Also, the digital gain control was included into the baseband block without changing the frequency response at different gain values. A separate preamplifier with an additional pole was though needed for noise reasons. The gain diagram of the baseband block including each stage is given earlier in Figure 4.6, and more details of the implementation will be given in the next chapter.

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4.3.5

A/D Converters

The new wireless systems and also radio architectures, which bring the A/D conversion closer to the antenna, are changing the requirements of the A/D converters in cellular communications. In the second generation mobile systems, the digital interface operates typically at several hundreds of kHz or couple of MHz sampling rate and uses a reasonable number of bits even if the channel filtering is partly performed digitally. In the third generation systems, the wider bandwidths require higher sampling rates and only the despreading needs 4-6 bits from the converter. The specifications of the A/D converter change completely if practically all filtering except of the preselection in the RF front-end is performed digitally. Both the resolution and the sampling rate are drastically increased. In this subsection, a comparison of different reported A/D converters is given. They are divided into two categories: Nyquist rate and converters. The focus is only in their performance as a part of the radio system. Wireless communications are however just a single application for A/D converters. Therefore many structures are optimized for other purposes. The converter architectures are not discussed here. A tutorial of the topic especially for telecommunications is given in [109]. The performance of the A/D converters is specified and measured with different quantities and testing methods than other blocks in the receiver chain [110]. The differential (DNL) and integral (INL) nonlinearities describe the maximum deviation from the ideal difference between two consecutive transition points and from the ideal line over the total input range, respectively [111]. The both parameters should be within half of the LSB to meet specifications for a certain number of bits. However, they can not be directly transformed to IIP3 values in the receiver, which is needed if several channels with large differences in power levels are converted. Hence, the issue must be focused in the case of a purely digital channel selection. One of the purposes in this ADC comparison is to study the feasibility of such a converter. A brief discussion of the ADC linearity from the receiver point of view is given already in [112]. The compression of the converter is simply modeled as a limiting function, which is a theoretical quantity. Probably the nonlinearity would require a more sophisticated characterization. Here, it is however assumed for simplicity that the linearity of the different ADCs is sufficient and no other measure than the number of bits is required to define the dynamic range. The effective number of bits can be calculated from the measured signal-to-noise and distortion ratio (SNDR) as

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SNDR and spurious free dynamic range (SFDR) are more important parameters for ADCs in wireless communications than DNL or INL, which describe the static properties. The effective number of bits may be smaller than the value of implemented bits in the converter. However, the latter is used in the following plots because of the common habit to report the results. Another significant limitation is the input frequency range in practice. Theoretically the Nyquist rate converters operate up to the half of the sampling rate, but in many cases they have been tested only for significantly smaller frequencies. The theoretical limit has been used here, but it may give a too optimistic figure of merit for high frequency behavior. A converter can also handle input signals up to the Nyquist rate in its input without aliasing, but the desired signal band is limited due to the shaping of the quantization noise as

where is the sampling rate (or frequency), OSR is the oversampling ratio and the signal band is This is again a theoretical value. In the bandpass converters, the desired signal lies around some IF instead of dc as given above. In the following comparison, the performance metrics are slightly in favor of the A/D converters because the numbers are theoretical optimums rather than measured values of the implementations. The necessary data for the latter approach is however not available in a unified form and therefore comparison would be even more difficult. Totally 68 converters published in academic conferences and journals between 1987 and 2000 are included although most of them are from the year 1995 or later [113]-[180]. The number consists of 49 Nyquist rate converters and 19 converters. The total power dissipation is plotted in Figure 4.14 for different converter types and resolutions when the product of the sampling rate and the number of bits is given in the x-axis. This method allows the categorization of the A/D converters for different systems and architectures in the x-axis. Instructive requirements for those are given in Table 4.4. The terms digital baseband, IF and RF mean that all filtering is performed digitally and that the whole system band from dc is inside the Nyquist limit. Hence, the possibility to subsample a bandlimited IF or RF is not considered. The ovals in Figure 4.14 describe only roughly the range of interest and the dimensions in the yaxis are arbitrary. The recent focus in the academic research has been mainly in the converters towards the digital baseband giving the high-end performance. The circuits for the 2nd generation systems are already mature structures, and the information for those could be found from the data sheets of commercially available products. The dots in Figure 4.14 form a fuzzy cloud. Therefore some trend lines have been drawn whenever at least three samples are given for each resolution. The solid lines present 6,8,10,12,13 and 14 bit Nyquist rate converters and dashed lines 11 and 12 bit structures. The A/D converters used in the chip set [94] and in the single-chip [39] versions of the WCDMA direct conversion receiver are also included in the plot. They were specified also for higher chip rates meaning a higher clock frequency. Therefore both converters are located outside the typical area for the required 3rd generation performance. This explains the relatively high power consumption in the standard WCDMA operation. Compared to their optimal performance as given in Figure 4.14, the consumption is less than average. When operated at lower clock frequencies the total power consumption scales down very poorly in some architectures.

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The Figure 4.14 indicates clearly the rapidly increasing power consumption when the requirements of the ADC increase. This is evident and distinct merit on behalf of analog signal processing. In power critical applications, the role of the analog signal processing will remain very important because of the high cost in analog-to-digital conversion. Consequently, the evolution of conversion techniques has brought more digital architectures available for other applications. Still, the digital RF is not a very feasible solution although some converters are approaching that area. To observe the different effects of resolution and sampling rate the power consumption per bit is plotted as a function of sampling rate in Figure 4.15(a). The trend lines, which are plotted for the same resolutions as earlier, show the incremental power consumption when the number of bits is increased. Even more significant is the effect of the sampling rate. The 6-bit converters given in Figure 4.15(a) are emphasized mainly for very high sampling rates, and the obscure behavior is explained with a single sample below 100 MHz. The effect of the technology scaling on the performance is studied in Figure 4.15(b). As a measure the power consumption is divided with the sampling rate for 10-bit Nyquist rate converters. The technology does not seem to provide any decreasing trend when the structures are reduced. Hence, although the digital power consumption scales down with faster technologies the A/D converter is still a bottleneck for the reduction in the total power dissipation.

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4.3.6

Decoupling

The supply voltage node must provide a good ground for high frequency signals in unbalanced circuits and also for common-mode signals in differential structures. Also, a stable supply is required to prevent noise and power transients from coupling to analog signals. This is critical especially in large digital or mixed-mode ICs with high peak currents in digital supplies. The decoupling capacitor, either on-chip or external, may not be adequate for the purpose because of an unwanted resonance formed with the inductive bondwires or package pins. Hence, careful analysis and more complicated structures are needed to avoid the problem. Decoupling strategies have been analyzed thoroughly for digital CMOS circuits in [181], and protection against supply noise in mixed-mode ICs is discussed in [182]. Here some comments are given of the decoupling strategies for the RF front-end in a mixed-mode structure. The impedance between the supply rails in the chip can be given with a simple model in Figure 4.16(a). The inductance gives the total series inductance of external supply and ground interconnections to the chip. The external impedance between the ground and the supply interconnections is assumed zero for all frequencies except dc. If the approximation is not accurate enough more passive R, L, and C elements are needed, which complicates the analysis. The capacitor presents the parasitic capacitance between the supply and ground in the circuit and the possible high-quality on-chip decoupling capacitor. To avoid the resonance at the frequency an RLC decoupling method is proposed in [182]. The principle is shown in Figure 4.16(b). If the value of the resistor is chosen correctly, the both resonances of the structure are damped i.e. no peaking is observed and the impedance between the supply and ground rails settles to an acceptable level at all frequencies. The structure avoids the power supply loss compared to the case when the resistor is connected directly in series with the supply rail. The same effect with a different frequency response is achieved with a simpler structure in Figure 4.16(c). The large on-chip decoupling capacitor is damped with a small resistor The impedance between the supply and ground, can be now given as

It is evident that can have resonance only when both the real and imaginary parts of the denominator are simultaneously zero. The real part is zero when and the imaginary one when If peaking is not possible and hence unwanted resonances with high Q values are avoided in all cases. The damping resistor however has effect on the maximum possible impedance. The given structure avoids the external tuned RLCnetwork and is insensitive to component variations. The small resistance can be implemented on-chip with a large number of parallel resistors in series with a large decoupling capacitor. This is the decoupling strategy, which has been used in the WCDMA receiver. The simulated impedance is given for different cases in Figure 4.17. The nominal resonance frequency of the LC-network is chosen to be 2 GHz in the simulations. The values of the damping resistance are swept from zero to both for the RLC and RC damping networks. The other values are and The resonance and component values were the same as in the unwanted resonance in the case of RLC network. The two high peaks are easily damped with small resistors, and the flat response was achieved with At higher values the resistor dominates the maximum impedance point. The RC network damps as efficiently the high resonances as the RLC method. In the simulations the value of the decoupling capacitor is small compared to the high-quality capacitance. This presents the worst-case condition and the smallest impedance maximum is only slightly below

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However, if the coupling capacitor is enlarged, which is typically the case, the maximum impedance can be easily dropped below This shows that the efficiency of the simpler RCstructure as a decoupling network is about the same as with the RLC method. The extra inductor is definitely not desired if it can be avoided with another technique. In single-ended structures, the resonance of the decoupling circuit is in series with the load resonator of the LNA. The frequency response of the LNA will change if the unwanted resonance appears close to the desired operation frequency and the maximum is very sensitive to component variations. This is a second reason for the use of a damped decoupling network in the RF front-end.

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4.4

Active Mixers in Direct Conversion

In this section, active mixers for direct conversion are discussed, and the main emphasis is in the IIP2 analysis with respect to some topological constraints. As depicted earlier, symmetry is a key issue to restrict dc offsets and envelope distortion at the output as much as possible. It should be taken into account throughout the design from the choice of topology to layout. Especially, if IIP2 is a critical design parameter even a small deviation from the perfect symmetry may cause unacceptable corruption in the performance.

4.4.1

Active Mixer Topologies

The term active mixer is somehow misleading by itself. Actually, switching mixers exhibit fundamentally loss in the commutating switches, but conversion gain can be obtained between input and output terminals because an amplifying stage is included in the mixer. If the voltage conversion gain is of interest, only the impedance transformation to a higher level can overwhelm the loss in the switching. On the other hand, the ideal switching function as an LO gives always the largest possible conversion gain. The nearly ideal switching shifts to multiplication between the two input signals when the LO excitation is decreased. That reduces conversion efficiency between the RF port and the IF output from the maximum and the circuit operates as a multiplier. If the other tone i.e. LO is constant, the structure can be still used as a mixer. For linearity and noise reasons, the multiplier operation is however not very commonly used as a downconverter. Another example, the four-quadrant CMOS multiplier discussed in subsection 4.3.2 operates in the multiplication mode, but can provide a much larger gain with the same linearity than the more widely used switching structures. The definition of its conversion efficiency however differs from the conventional as given in [62], and the efficiency depends on the external connections like with all other topologies. Why giving all the pedantry above? An active mixer can be defined as a structure in which the core transistors are biased so that the supply current flows through them when the switch is operating as a pass transistor. However, the term active mixer is often connected intuitively to the structure given in Figure 4.18. First, the input voltage is transformed to current in a V-I converter. Then the current is multiplied with the gate- or LO-function, and finally converted back to voltage in the load. Often but not necessarily all blocks are stacked in the same supply path. This description is simplistic and obvious, but useful for modeling theoretical performance in subsection 4.4.3. The term active mixer in this subsection is limited to this structure, which is definitely most commonly used in the integrated radio receivers. Both single-balanced and double-balanced structures are considered.

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All active mixers originate somehow from the four-quadrant multiplier, which is generally called as a Gilbert-cell [183]. The topology is shown in Figure 4.19. The double-balanced structure was developed to reduce the distortion at the output compared to the common emitter differential pair. With current IC technologies the improvement in the performance using the double-balanced structure is not necessarily very significant. Therefore, the single-balanced topology is often used to avoid single-ended to differential conversion at RF. Also, MOS devices are adopted instead of bipolars in many recent RF applications. Because both singleand double-balanced topologies are discussed, a transconductance mixer is a more appropriate term for general use instead of the Gilbert mixer in this case.

The linearity of a transconductance mixer depends on the V-I converter and the switching quad. The former is typically considered as a dominant part if switching in the LO transistors is arranged properly. The conducting switch operates as a cascode stage half of the LO period and the transitions between the on and off states are abrupt. This is however a too simplistic model for practical cases. The characterization of the nonlinear switching operation requires complex differential equations including several device parameters as analyzed for a bipolar core in [184]. The theory predicts that the third-order intermodulation distortion achieves a minimum at a certain LO voltage drive level. This can be observed as a maximum in IIP3 characteristics in Figure 4.20. The result is measured for a bipolar core from the direct conversion RF front-end in [185], which is a part of the WCDMA receiver [94]. The degradation in linearity is however only a couple of dBs at higher drive levels. Only the third-order intermodulation products are of interest in a RF mixer of the superheterodyne receiver. The significant spectral replicas are located at the band of interest both before and after the downconversion. The performance is not sensitive to small mismatches between components, and therefore the IIP3 can be simulated with a good accuracy if precise transistor models are available. In a direct conversion receiver, the IIP3 behavior does not significantly vary from the previous. Only the parasitic effects are less significant at the output because of the lower operation range. Also, the preliminary filtering of the high out-of-band interferers can be easily performed with a RC-pole immediately at the output of the mixer. Instead, IIP2 is always infinite in the ideal case, and the distorted signal is located around baseband or double-frequency after the nonlinear element as discussed earlier. Hence, the characterization differs significantly on the third-order nonlinear effects. The requirements of component match and IIP2 will be discussed in the next two subsections.

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The V-I converter operates typically in the active region if bipolar devices are used, and in saturation in the case of MOS transconductance stages. A transconductance stage biased in class AB can be used with bipolar devices to increase the compression point and hence the blocking performance [186]. This technique however does not benefit the small signal IIP3 behavior, and will not be discussed or utilized later. The theory behind the small signal linearity of bipolar and MOS devices is thoroughly discussed in [187], and a detailed analysis focused more specifically on the bipolar transconductance stages in active mixers is given in [188]. A known fact is that the linearity of a bipolar transconductance stage both in common-emitter and differential-pair configurations is very limited and not necessarily sufficient for RF downconversion mixers. The most common linearization technique is the emitter degeneration at the cost of gain and noise figure. Typically, this is done with a resistor increasing the internal emitter resistance of the device. It has been shown however that a better performance can be achieved with inductive degenaration [189]. Another important statement in the given analysis was that the commonemitter transconductance stage achieves the same gain and linearity as the corresponding differential pair configuration with a lower current consumption. Bipolar differential pairs can be linearized also using parallel, differently sized transconductance stages, which increase the acceptable input signal range [190], [191]. The technique is called according to Gilbert as the multi-tanh principle, but also other terms like unbalanced emitter-coupled pairs is used. A tutorial of the technique, and different circuit topologies are given in [192]. A third well-known technique to improve the linearity of the V-I converter in variable-gain amplifiers and transconductance mixers provides extra supply current for the converters from a separate source [193]. Recently, the linear range is extended using a common-emitter/common-base transconductance stage described in [194] and [195], and applied to a superheterodyne receiver in [196]. The topology is often called as a micromixer according to [195]. It performs also the single-ended to differential conversion for the RF input. The evolution of IC technologies has increased the operation range of MOS devices up to GHzrange. In a BiCMOS process, this can be utilized by selecting the most suitable device for each function also at RF. MOS devices in the V-I converter exhibit fundamentally better linearity than bipolars if the overdrive voltage is sufficiently large. Therefore degeneration is not absolutely necessary in RF downconverters. Also, a properly sized device provides a higher transconductance than a degenerated BJT [197]. The input devices can be also connected directly to the circuit ground without a common tail current source as in [2], for

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example. The improved linearity is achieved with the lack of common-mode rejection. Hence, the following stages should tolerate common-mode signals. It can be summarized that the MOS transconductance stages are excellent V-I converters, and with submicron technologies their operation range reaches quite easily 2 GHz. Hence, the frequency range does not limit the choice between different devices in a transconductance mixer. If the large overdrive voltage is not acceptable, because of too high current consumption or limited biasing conditions due to the low supply voltage, for example, similar linearization techniques as multitanh-principle for bipolar devices are developed for low-frequency applications [198], [199]. The fundamental differences between linearized differential pairs using either bipolar or MOS devices is discussed in [200]. However, sufficient input range has been achieved in recently reported double-balanced mixers for receiver applications using NMOS V-I converters without additional linearization [2], [64], [94]. The effect of technology scaling on the linearity of mixers is discussed for example in [201]. The deep submicron MOS devices will still provide better performance than bipolars as V-I converters although the difference is reduced significantly below gate lengths. A modified version of the micromixer adapted to CMOS was established due to the single-ended interface to a double-balanced mixer rather than because of insufficient linearity in [202]. Only common-emitter and common-source stages are discussed so far. Especially in superheterodyne receivers, which require a input match, a common-base or common-gate input stage would be an optimal choice also for the linearity performance [44]. In the direct conversion that is not necessary. In circuits with a low supply voltage, the transconductance stage can use a separate supply path like in [203]. In that case, the single-ended to differential conversion is possible to establish with a LC-network at the input of the mixer core [204]. Other low-voltage techniques include replacement of the tail current sources with LC-tanks [205], [206], folded structures [199], and use of a transformer to bring the single-ended input to a double-balanced mixer [52]. The references to linearization and low-voltage techniques are not comprehensive, but present some important techniques and recent areas of interest. In direct conversion mixers, the second-order distortion generated in the V-I converter is also of importance. However, the signal path to output differs from the desired signal as discussed in the previous chapter. The second-order nonlinear components lie either at the double-frequency or at the baseband. The former replica can be downconverted to dc if The unwanted distortion is based on the second harmonic of the LO signal. This may be significant, but the interest is here only at the baseband product. It will be observed at the output if differential branches are not perfectly matched. This behavior will be discussed in the next two subsections. To cancel the contribution of the V-I converter to IIP2, a bipolar Gilbert mixer was established in which the baseband and double-frequency beats from the V-I converter were filtered with a passive LC network [33]. The measured results indicate over 20-dB improvement in performance, and the IIP2 of the mixer with LC-filtering was about +50 dBm. Similar approach was taken in [31], but only the low-frequency part was filtered with a coupling capacitor. A direct conversion mixer having a separate transconductance stage with a LC-tank load, which utilizes the bottom plate parasitic of the ac-coupling capacitor in the tank circuit, is presented in [207]. The structure adopts the principle given in [33], and inverts the large, unwanted bottom-plate parasitics of the capacitor in a standard CMOS process into efficient use. The different filtering approaches however do not give unambiguous results of the performance improvement although the number of potential sources or at least their contribution is reduced. Hence, the switching core and the mismatches at the output are equally of importance. The results from direct conversion receivers using a conventional transconductance mixer report similar performances as with special techniques [2], [7], [15], [17], [94]. However, in all given examples MOS transistors are operating as V-I converters and on-chip LNA is connected directly or though a coupling capacitor to the input of the mixer.

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4.4.2

Interfaces to LNA and Baseband

The RF interface between the LNA and mixer is critical even though the on-chip interconnection should have small parasitics. The interconnection can be normally modeled with a lumped RC-network including the capacitive input of the two V-I converters, and resistive losses of the wiring. The two transconductance elements model the I- and Q-mixers. The RC-time constant is not an appropriate model for the interface, if the load of the LNA is a tank circuit, which is typically the case. The wiring and the input impedance of the mixers are then a part of the tank. Hence, the interface should be an inseparable part of the LNA design, but it has also a significant effect on the linearity of the mixer. Another critical factor is the coupling mechanism. In a standard CMOS process, direct coupling may be needed because the large bottom-plate parasitics of the coupling capacitors may lead to an unacceptable trade-off in the sizing of the coupling element. The desired signal will leak through the low-resistivity substrate to the ground if the capacitor is too large. On the other hand, a small capacitor leads to an unacceptable voltage loss over the capacitor at the signal frequency in the division with the mixer load. An analysis of the different design strategies using a standard CMOS process with poly-capacitors in the ac-coupled RF interface is given in [208]. The coupling capacitor is then an essential part of the tank circuit. The results are summarized in the next chapter. In the given example, the subsampling mixer caused additional requirements for the interface, but the methods are basically applicable to other mixer topologies as well. Similar trade-offs have been considered briefly also in [207] as discussed above. The modern BiCMOS processes intended on the RF integration can contain high-quality metal-insulator-metal (MIM) capacitors. Their capacitance density is high, losses of the plates are low compared to polysilicon and the small area with a better substrate reduce parasitic losses of the bottom plate to an acceptable level. MIM capacitors were available in the WCDMA receiver implementations, and therefore the traditional RF design trade-offs could be followed instead of tricks necessary in a standard CMOS. A mixer can be biased independently of the LNA if coupling capacitors are used. Otherwise, the load of the LNA determines also the biasing conditions of the input terminal in a V-I converter. In CMOS, this is possible and implemented at least in [7], [15], [51]. Large overdrive voltage improves linearity, but on the other hand limits the supply range due to increased for example. The design trade-offs in low-voltage conditions is discussed in the case of CMOSonly Gilbert cell in [209]. Also regulated biasing is needed in double-balanced structures to improve matching [51]. In the simplest form, the downconverted current is transformed back to voltages for baseband processing with resistive loads. The possibility to use current-mode signal processing in the baseband circuitry will not be considered here. The resistor approach requires excellent matching for load devices in direct conversion receivers due to the IIP2. It will be discussed in the next subsection. Because of the matching requirements the load resistors may not be feasible with all processes. The used BiCMOS process in the WCDMA receiver provided highquality polysilicon resistors with small deviation in adjacent component values. The other option uses high-impedance current sources connected to the supply rail, and the load for signal is located between the positive and negative outputs as in [2], for example. The resistive load is either a lumped resistor or a transistor operated in the triode region. The separate current sources allow the biasing of the mixers to be independent of the load. The current sources and transistor loads are however noisy and nonlinear. Especially, the minimization of flicker noise is critical at the output and large devices are required. In direct conversion receivers, the large out-of-band interferers can be attenuated preliminary with a passive pole at the output of the mixer. This arrangement relaxes the linearity

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requirements of the baseband if the pole is located relatively close to the actual cutoff frequency of the channel selection filter. In that case, the passive pole should be included in the filter prototype and the matching of its cutoff frequency is critical for the linearity performance. In narrow-band systems, the capacitor should be implemented with an external component like in [57], but in a wide-band receiver an on-chip structure is feasible [94]. The noise of the channel selection filter is often a dominant source of the noise performance in a direct conversion receiver [15]. The optimum noise and linearity conditions may significantly differ from the output impedance and bias point directly available from the mixer. Therefore a buffer, typically an emitter or source follower, is required between the mixer and baseband [15], [94]. The reduced impedance level however requires a significant amount of supply current, and buffering stage can be the dominant source for the power consumption even in on-chip structures. The baseband circuitry requires also a stabile dc-level, which is independent of the supply voltage at its input. A common-mode feedback circuit (CMFB) can be used to control the dc level at the output of the mixer. The acceptable dc-level at the output of the mixer limits the supply range more than the linearity or gain performance in the WCDMA direct conversion receiver although a CMFB is used [185]. The supply range can vary only about from the nominal 2.7 V although the gain and linearity are unchanged down to 2.1 V as given in Figure 4.21.

4.4.3

Theoretical Characterization of IIP2 in Transconductance Mixers

The analysis of second-order nonlinearity and how it appears in the direct conversion receiver is not as straightforward as other nonlinear characteristics of the circuit. In a perfectly balanced case, IIP2 is infinite and the result is independent of any other parameter as long as the balance is not violated. This is a well-known fact and the mismatch behavior for analog multipliers has been analyzed at least in [183] and [210] for bipolar and in [199] and [211] for MOS circuits. The given analyses are based on the large signal input-output transfer functions and they can be applied to the mixer core. The traditional method to present the nonlinear behavior is to plot the signal level at the output as a function of input as shown in Figure 4.22, and the results are typically given in percentages from the ideal curve. It can be thought as an analog eye-diagram although the precision requirements are of course much stricter than with digital structures.

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However, the method neglects the frequency transformation characteristics, and the results do not give much insight on the required matching in the case of a direct conversion mixer operating in the switching mode. In this subsection a simple, functional model for a switching mixer is described. The mixer core is replaced with a mathematical gate-function, which gives more insight on the frequency transformation characteristics. Both the single-balanced and the double-balanced behavior will be discussed. In the next subsection, the gate-function is replaced with the large signal model for a differential pair in the single-balanced mixer core. The analysis gives better understanding in the choice of devices for the core, although only a very simple model is adopted. Also, the difficulty to model the frequency transformation even with quite simple mathematical equations becomes obvious.

The second-order intercept point was a problem already in the transmission of cable TV channels some thirty years ago. The large signal levels of amplitude modulated channels and the requirement of over a 66-dB relative attenuation of second-order beats were a problem for push-pull amplifiers. They were used instead of individual amplifier stages to lower the output powers of each stage. The sum term was a more important problem at that time, but the analysis given in [212] does not take the frequency characteristics into account. This is because only amplifiers are characterized, the output response is wide-band, and the potential channels causing the problem are known in advance. However, many aspects of the analysis are valid for the downconversion mixers, but some complementary aspects are needed. In the amplifier analysis, the mismatch parameters between the two signal paths were the amplitude error, and the phase errors before and after the nonlinear element. Three observations follow from the analysis in [212]. First, an individual imbalance term causes rapid degradation from ideal as the imbalance increases. The IIP2 curve drops according to in dB scale, where is the imbalance term plotted in the x-axis and n the scaling factor. The scaling factor depends on the type and position of the imbalance in the system. Second, two simultaneous phase errors shift the maximum IIP2 in the x-axis if one imbalance term is constant and the other is swept. Third, the amplitude error causes saturation of the maximum IIP2 value if either one or both of the two individual phase imbalances are not zero. The IIP2 follows then a bell-shaped curve instead of peaking in one individual point. These observations will be of importance also for downconversion mixers. The variables modeling the imbalance are changed in the analysis and the results are specified for the mixer applications. Only the difference beat is considered in this case, but the corresponding results could be calculated also for the sum term if the second harmonic of the LO will be taken into account. Lambert names the phenomenon as a second-order improvement in [212], but it is only a matter

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of terminology. Instead, the IIP2 is generally used in receiver applications. It should be noticed that the analysis resembles also image rejection calculations discussed earlier, but the results are specified for another purpose. The analysis is performed here for a simple behavioral model given earlier in Figure 4.18. The V-I converter is modeled with an ideal voltage controlled current source having also a nonlinear terms as

where is the transconductance of the V-I converter and is the nth-order nonlinear term with respect to the fundamental. The relative terms are used for convenience in the analysis, and the corresponding fundamental and higher-order terms in chapter 2 are and respectively. In weakly nonlinear structures, as is the case with the V-I converter, three terms model the behavior with a sufficient accuracy. It is assumed in this model that all nonlinear effects in the transistor can be included in this equation independently of their source. Also, the output conductance is assumed to be infinite, and hence the operation of the transconductance element is totally independent of the state in the commutating switches. The ideal switches performing the frequency conversion are controlled with mathematical gate functions and and the output current is converted back to a voltage with two load resistors. A simplified behavioral model is shown in Figure 4.23, and it divides the structure in three independent parts as discussed earlier in subsection 4.4.1. The tail current, describes the biasing of the V-I converter. If we compare the behavioral model to the transistor level design, it neglects all reactive elements. They are needed in the simulations of RF mixers, but their inclusion complicates the analysis too much. Secondly, the active devices should be assumed to operate in the saturation in the case of MOS and in the active region in the case of BJT when the transistors are ON. This is a valid condition for practical mixers. However, the actual channel conductance and early effects should be included at least in the simulations. Also, the model assumes that the quiescent current is zero when the commutating switches are OFF, and that the transitions between the states are abrupt in the switches. It is obvious that this model is too simple for circuit design purposes, but on the other hand it gives much information about the fundamental restrictions of the IIP2 behavior, which can be applied directly to more elaborate circuit models in the simulations. Some of the idealized parameters will be considered with more realistic models in the next subsection.

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The analysis can be made simple because the switching operation in each switch is ideal and the second-order intermodulation component (imd2) is observed at the output only due to asymmetric conversion back to voltages or due to non-ideal timing of the switching moments. Hence, the analysis is actually based simply on the leakage of the difference beat to the output, but similar equation can be used for the sum term of imd2 or when using nonlinear switch models also in the commutation process. However, the combination of different nonlinear replicas is not straightforward, although the signal source is the same, because the replicas are generated in different elements. Hence, only one nonlinear element is preferred, and the IIP2 is estimated in the case of one or more constant imbalances at a time. Before calculating the IIP2, some comments will be given with respect to noise analysis methods for mixers as given in [213], [214], [215] and [216]. It is a well-known fact from the mixer noise analysis that when the both commutating switches are ON simultaneously, the noise from the core transistors is visible at the output [213]. That can be reduced with a steeper slope in the switching function by increasing the LO power. After a certain LO level the downconverted noise from the input stage becomes dominant. It has been shown recently that the noise from the core transistors at large LO levels is not negligible either due to the finite capacitance current from the common-source node of the commutating switches to ground [216]. This is significant especially in the direct conversion because the flicker noise of the commutating switches drifts into the output through the mechanism. The noise analysis of the mixers is a complicated issue due to the nonlinear time-varying characteristics, which leads to cyclostationary behavior of the output noise. However a single nonlinear function, which is independent of the switching function, allows more simplified analysis and gives still instructive results. The different statistical properties of noise and distortion together with the fact that the noise behavior depends typically only slightly on the mismatch are the main reasons for the need of a different approach.

4.4.3.1

Single-Balanced Mixer

The gain of an ideal balanced switching mixer can be calculated from a Fourier series expansion of the symmetric square wave as given in [2] and [64], for example. The fundamental conversion loss of and the voltage gain of

follow directly from the analysis. All even-order terms are however zero, which means that this presentation gives an infinite IIP2 in all cases independently of other parameters. Therefore the gate function must be modified to include the time when both switches are ON and also unequal conduction times for each switch. The former can model the dc-leakage through the mixer and the latter asymmetries in the switching operations. Such functions should be given separately for positive and negative gate functions as

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and

where

and are the duty cycles of the positive and negative gate functions, and The ideal gate functions are presented in Figure 4.23. The different duty cycles model the unequal conduction times. They can be given as

and

where is the nominal value of the duty cycle and is the difference in the duty cycles between the positive and negative gate functions. The differential gate function returns to the Fourier series given in [2] and [64] when and The positive and negative gate functions for and are presented in Figure 4.24(a) when the curves are plotted up to the second and fourth harmonic in the Fourier series of the LO. In this analysis, the interest is in the downconversion of the fundamental signal, which defines the gain, and in the even harmonics. For the calculation of the small-signal gain, only the from the odd harmonics is required in the gate function. On the other hand, the envelope distortion component is the same at the baseband and at after the ideal nonlinear operation as given in chapter 2. Hence, the possible dc leakage should be compared to the downconversion gain from The amplitudes of the second and fourth harmonic of the LO in the Fourier series are compared to the dc leakage at the single-ended output and plotted as a function of duty cycle in Figure 4.24(b). In the range of interest i.e. around 0.5, the harmonics are almost negligible compared to dc. Hence, the higher harmonics are omitted in this analysis, but in practical cases the condition is not necessarily valid. The effect of the should be checked in the two-tone measurements by an appropriate choice of test frequencies.

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The currents in the positive and negative branches can be now calculated for the terms of interest. The RF input signal is given as The interesting current components at the lowpass filtered outputs are

and

where is the downconverted signal and is the low-frequency beat. The second mismatch term, in addition to an unequal duty cycle, is the imbalance in the load devices. The load resistors are given by

and

where is the nominal value of the load resistance and the relative mismatch. Using these two mismatch terms the differential output voltage can be given as

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It is assumed that the common-mode term is rejected sufficiently at the output and it can be ignored. The voltage gain gets a complicated form

However, it is quite easy to show that the latter term is negligible if which is a realistic assumption. Also, the cosine part from the former term is typically close to unity. Hence, gain is almost independent of mismatches, but degrades to some extent when both commutating switches are simultaneously ON. The gain degradation as a function of the nominal duty cycle is given in Figure 4.25. Also, two fixed and relatively large mismatches are plotted in the same figure. They have only minor effect on the performance as stated above.

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The second-order input intercept point can be now calculated from the fundamental and the imd2 terms as

The value is a rms-voltage quantity. Usually, it is practical to refer the value to the power i.e.

input

In decibels, the corresponding in the impedance level. The IIP2 depends only on the imbalance in the system. For the simulations it is not a very useful estimate, because the IIP2 result requires always a certain imbalance parameter defined in advance and the MonteCarlo simulations in the case of harmonic balance are very slow for a complete mixer. The quality of the circuit against second-order distortion can be easily divided in two different quantities i.e. the fundamental distortion and the effect of balancing. The former can be defined for example from the single-ended output of the mixer. It is not directly the of the transconductance because of the switching function. The single-ended iip2 is defined here from the positive output in the nominal conditions i.e. as

This term is independent of the balancing and can be simulated with the same confidence as the other nonlinear effects. A larger value indicates always a smaller sensitivity against envelope distortion. Direct measurement is also possible, and therefore the effect of imbalance can be separated from the fundamental nonlinearity. A similar approach can be used also for doublebalanced configurations by applying only a single-ended signal to RF input. To alleviate the necessity of excellent balancing, a quantity of balancing factor is defined here as

The balancing factor depends on the matching properties of the devices in the IC process and the layout of the circuit. If the probability distribution functions (PDF) of the different process variations are known and the sources of mismatches are recognized in the circuit topology, the balancing factor can be used to estimate the yield of certain IIP2 value, for example. The other important parameter in the direct conversion mixer i.e. the dc offset at the output can be also defined from the above calculations as

It shows clearly the part, which depends on the input signal amplitude. IIP2 is plotted as a function of a single imbalance with different parameters in Figure 4.26(a). The mismatch in the

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load is a significant reason for the IIP2 degradation, but the fundamental nonlinearity is also very important for the performance. The single-ended IIP2 is +20 dBm in the nominal case. The both imbalances are included simultaneously in Figure 4.26(b). It shows that two imbalances may degrade the performance significantly from a single mismatch if they are summed. On the other hand, the maximum of the IIP2 shifts as a function of the other mismatch as expected.

4.4.3.2

Double-Balanced Mixer

In the case of double-balanced mixers, the calculation of IIP2 requires some more effort. On the other hand, new variables of imbalance can be adopted. The following analysis includes the transconductance mismatch of the V-I converter and the amplitude and phase imbalances of the RF input signal. The double balanced mixer is basically the Gilbert-cell in Figure 4.19 in which the transistors are replaced with ideal models as in Figure 4.23. The V-I converters in each branch are however independent voltage controlled current sources instead of a differential pair. Hence, there is no common-mode rejection available in the input stage and the tail current is always divided equally between the devices. This is a slightly artificial approach but still useful to alleviate some issues. The transconductance stage can be replaced with a transistor level differential pair in a more sophisticated analysis. Some properties of differential pairs will be discussed in the next subsection. In that case they are operating as nonlinear switches rather than as weakly nonlinear input stages. The input signal is given separately for positive and negative input terminals as

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and

The presentation takes into account the effect of a 180-power divider without any insertion loss, but the amplitude and phase imbalances are included. The amplitude imbalance is assumed equal for both signals in the two-tone test, and the amplitudes at the positive and negative inputs are given as

and

where is the amplitude imbalance. The phase error is included only in the negative input and the difference in phase errors between the two different tones is

Because the two tones have the same signal path and the relative frequency difference between the tones is typically rather small the difference term can be assumed to be much smaller than the phase error of an individual tone. The total transconductance of the V-I converter is assumed to be the same as in a single-balanced mixer and hence the transconductances of input devices can be given as

and

The nonlinear terms, are assumed equal in both branches. The given precautions should be characterized separately with respect to biasing and other transistor level parameters if a comparison of properties between the single- and double-balanced mixers is made. However, they are sufficient when the theoretical differences in the IIP2 behavior are analyzed. If only one fundamental component, currents of the V-I converters are and the low frequency terms are given, the output

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and

The differential output is then given as

After lowpass filtering the output can be written as

where

The and term collect the IF components and and the low frequency components. If it is assumed that the gain is relatively independent of mismatch, which can be calculated from the above presentation, the voltage gain of a double-balanced mixer can be given as

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It differs only by a factor of from the single-balanced, which is due to the single-ended to differential conversion. The second-order intermodulation term however achieves a complicated form

If the second and third factors of each term are multiplied and the components, which have a squared mismatch term or multiplication of two different mismatch terms, are considered insignificant in the summation, IIP2 can be written as

Still the equation is quite complicated and contains a large number of independent variables. When the sum term in the denominator is calculated and assumed that the imbalance terms multiplied with it can be neglected. Hence, the IIP2 simplifies to

There is one important difference in this analysis compared to the single-balanced case. The denominator is zero when Hence, the maximum of IIP2 is achieved when the resistance mismatch is about one decade smaller than other imbalances. If different imbalances are at the same range in percentages, the maximum shifts far from the ideal situation as shown in Figure 4.27, and the IIP2 value is saturated almost to a constant level in the vicinity of circuit balance. However, rather small changes in a single mismatch term may significantly change the saturated IIP2 value. In Figure 4.27, a single-balanced and a double-balanced mixer is compared as a function of Nominal conditions are the same as used earlier. The slightly better performance of the double-balanced mixer is due to the smaller gain. The phase imbalance at the input of the mixer is practically negligible. The interesting curves are those, which are plotted for fixed Input amplitude and transconductance mismatches are in the same position, which makes sense, and therefore is kept zero in Figure 4.27.

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The analysis shows that it may be difficult to achieve a high IIP2 even when tuning is used. Theoretically it may be possible but this analysis gave only one possible reason for the saturation of IIP2 and a rather limited set of mismatches. More complicated models are probably necessary. The characterization of different mismatches and their relation is extremely difficult if very small imbalances may shift the ideal point of IIP2 far from the nominal as this model predicts. Although this behavior is observed only in the case of a double-balanced mixer, it is reasonable to predict that similar cases can be found also for the single-balanced case. In the case of single-balanced mixer the dc offset at the output was dependent on the same mismatch parameters as IIP2. In the analysis of double-balanced mixer the dc offset, which depends on the tail current is directly

The signal dependent part is neglected, but it follows the imd2 behavior like earlier. The dc offset from the tail current does not depend on which is natural for a double-balanced structure. It also shows that the dc offset and IIP2 are not necessarily tied together. Because only a simple behavioral model is used, it is too early to make very definitive conclusions. However, the issues discussed here can be intuitively combined with the measurements performed throughout the receiver project. Also, it is possible to connect the results to some earlier experiments reported in literature although very little background and practically no analysis have been given on those IIP2 tuning trials. In [31], a 15-dB improvement up to +50 dBm at the input of the mixer was reported using bias adjustment. A digital tuning circuit and 3-bit DAC controlling the tail currents of direct conversion mixer in [29] resulted into about 10 dB better IIP2 of +37 dBm at the input of mixer compared to the uncompensated case. The dynamic matching technique in [217] provided also about 15 dB improvement but the IIP2 of +72 dBm is the best reported result so far. The given discussion is valid for double-balanced mixers. The behavior of transconductance stages, which perform also the single-ended to differential conversion like the micromixer

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[194], [195], is more likely a combination of two parallel single-balanced mixers when IIP2 is analyzed. The second-order nonlinearity should be analyzed separately for the two different signal paths between the input and the core. The symmetry conditions in the sense of IIP2 are more complicated to achieve and not discussed here any further.

4.4.4

Switching Core

So far, only the frequency conversion properties of the core transistors have been characterized using idealized models. In this subsection, some basic properties of bipolar and MOS transistors are discussed when they operate as commutating devices in a direct conversion receiver. The effect of LO amplitude on the conversion gain is given, and the IIP2 is calculated for a singlebalanced mixer using a bipolar differential pair as a core. The discussion is limited only to single-balanced structure in order to restrict the number of variables and to keep the analysis simple. It is also assumed that the V-I converter is the dominant source of nonlinearity, and only the mismatch of the differential pair is taken into account. The first-order large signal model for the collector current of a bipolar transistor operating as a switch in the mixer core can be given as

where is the saturation current depending on the process parameters, emitter area and base width. The thermal voltage, is 26 mV in the room temperature, is the base-emitter voltage in the biasing point when no LO is applied and is the differential LO voltage in the switching pair. It is assumed that the core transistor operates always in the active region when it is ON. The transfer function of the switching pair follows then the well-known behavior [218]. If the LO voltage is sufficiently large the conversion efficiency of the mixer comes directly from the ideal switching function as given earlier. Otherwise, the amplitude of the LO signal has effect on the voltage gain. The degradation from the maximum gain is given in [188] as

where is the differential amplitude of the LO signal. The curve is plotted in the room temperature in Figure 4.28. With a sufficiently low LO amplitude, the structure is not a switching mixer but a multiplier as can be seen from the figure.

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The analysis of a MOS mixer core is not as straightforward because the overdrive voltage, has a more complicated relation to the current division in the differential pair than in the case of bipolar devices. The large signal transfer function of a MOS differential pair operating as mixer core can be given as [187]

using the level 1 MOS model in which the drain current of MOS switches in saturation is simply

where is the process and size parameter, is the time-varying gate-source voltage of each individual device, is the threshold voltage and is the tail current of the switching pair. A relatively simple approach to analyze the differential pair as a switching core is taken in [64]. The gain degradation is calculated based on the time when both switches are simultaneously ON for a short while. The gain degradation can be given as

The above formula however assumes that the amplitude of the LO signal is sufficient for perfect switching and only the simultaneous conduction degrades the gain from A more elaborate model is given in [214] including the effect of LO swing and short-channel effects of MOS devices. For a sinusoidal LO the gain degradation can be written as

156

where is a function of device and process parameters and biasing including the tail current and overdrive voltage of the switching pair. should be always larger than in the mixer. The latter analysis is however rather complicated for comparison between the MOS and bipolar devices. The simple characterization of V-I transfer functions as in Equation (4.59) gives more insight on the matter. The transfer function in the case of MOS devices depends on the overdrive voltage in the biasing. The large overdrive voltage, which is often desired, requires a larger LO amplitude for the switching. The transfer functions are plotted for bipolar and MOS switching pairs in Figure 4.29. The product of load resistor and tail current is unity in both cases. This corresponds to a 1 mA tail current and load resistors, for example. The MOS curves describe only the upper formula in Equation (4.59), which is not valid when The limitation is evident in the plot. Although the overdrive voltage is an additional parameter compared to bipolar implementations and gives some flexibility in design, the required LO amplitude is typically much larger for the MOS core in the switching operation. This is a well-known trade-off, which prefers the use of bipolar devices in the core. However, the required source power is not directly connected to the amplitude because of different input characteristics of the various devices. In principle, it is also possible to operate the MOS core in the weak inversion in which the behavior resembles a bipolar one. However, large devices biased to a low current are needed. This option is not very feasible in the RF design and therefore only mentioned here. The gain degradation is plotted as a function of LO amplitude in Figure 4.30 using the both MOS equations and compared the results to the bipolar core. The thin lines presenting Equation (4.62) are plotted for V and 1.1 V. The latter is calculated directly for the MOS devices biased with a 5.6 mA tail current as given in [214], and the former is realistic with a smaller biasing current.

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Although the required LO amplitude is of importance when the core transistors are chosen the flicker noise contribution of the switching devices is practically a more difficult issue in direct conversion receivers. The inherently higher flicker noise of MOS devices is a serious problem especially in narrow-band systems if the modulated information is located around dc and the noise figure requirement of the receiver is very low. The low flicker noise requires large MOS devices, which may have too large parasitics for the GHz-range operation. The flicker noise contribution is significantly reduced if the channel can be highpass filtered up to tens of kHz like in [15]. The 11 MHz bandwidth at baseband in [7] is large enough to restrict the flicker noise contribution much below 1 dB. However, the total noise figure of the receiver is still over 8 dB. Even in low-IF topologies care must be taken into flicker noise. It is reasonable at 100 kHz in [219], but deteriorates badly the information below 80 kHz. As discussed in [51] and analyzed more detailed in [216], the flicker noise in MOS mixers can not be eliminated effectively even when high LO signal levels and hence abrupt switching is used. The recent results of dynamic matching to improve the IIP2 in a direct conversion receiver seem to work efficiently also in the cancellation of flicker noise in MOS structures [217]. Still the use of bipolar core is strongly preferred in the mixer because an acceptable flicker noise performance is achieved with relatively small devices. Hence, the capacitive effects remain small providing fast transitions between the states and high frequency operation.

4.4.4.1

IIP2 Analysis for Single-Balanced Mixer Using Bipolar Core

The core transistors have effect on the IIP2 in the direct conversion receiver as depicted earlier. However, the nonlinearity in the signal path can not be modeled with the first-order transistor models as given above because the signal current is directly multiplied with harmonics of the gate function and only the frequency conversion is included in the multiplication. The nonlinear products of the signal have been generated always before the gate function. Hence, more complicated models should be used. A large variety of different effects are described in the case of weakly nonlinear behavior both for bipolar and MOS devices in [187]. However, the

158

characterization of the switch in the ON-state as a cascode stage and in the OFF-state as an open circuit is definitely not very accurate especially because many nonidealities in the mixer come from the strongly nonlinear switching operation. Unfortunately, the nonlinear characterization of the core leads to complicated equations, which can be only solved numerically [184]. In the case of IIP2, the equations should be combined with mismatch analysis and the results do not probably give more insight on the nature of the phenomenon than a simplified analysis presented next. The simple model in Equation (4.20) is still used as the only nonlinear function. In addition to the load mismatch, the saturation current mismatch, of the bipolar switching pair is included as another mismatch term in the analysis. It is in the same role as the duty cycle mismatch, used earlier giving a more realistic model for the core. Some simplifications will be made in the analysis to avoid some problems. The limitations will be discussed during the analysis and it follows in many cases the approach for emitter-coupled pairs given in [218]. The dc analysis is assumed appropriate for the large signal behavior, which is of course a rough simplification. The model for the analysis is given in Figure 4.31 and the output conductances of active devices are all negligible. The emitter resistors of the core transistors are also omitted because the solution in a closed form would be otherwise impossible. The collector-emitter voltages and collector currents of and can be given as

The base current is assumed to be much smaller than the collector current in the given equations. The relationship between the LO and collector currents in each branch can be written as

where

is the nominal biasing and

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in each branch. The nominal base-emitter voltage is equal at dc in both devices and the mismatch is included only in factors. The current ratio between the differential branches can be now written as

The current equation in the emitters of the core transistors is now

The last expression is valid because is close to unity when the current gain of the transistor is large. Then, the output signal of the mixer can be written as

The saturation currents of core transistors are given as

160

and

The difference and sum terms in Equation (4.72) are then

and

The output voltage can be written now as

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The last approximation is valid if it is assumed that the multiplication of two mismatch factors is negligible when summed with a single mismatch. It is evident that the tanh-function presents the transfer function of odd harmonics and the other terms describe the dc leakage and even harmonics in the downconversion. The factor multiplying the current and load resistance is actually the gate function for the bipolar core. However, the separation of different frequency components is practically impossible if a sinusoidal LO signal is used in the analysis. The Taylor series expansion for a function in the form of requires a very large number of terms to find the correct factor for the desired frequency component if is large. The last condition is actually the definition for a switching mixer. However, it is still possible to use the gain degradation function in Equation (4.58) when approximating the fundamental downconverted signal. Hence, the amplitude of the IF output is given as

The same problems as above apply also for Taylor series of However, the interest is here only in the dc leakage term of the gate function because the nonlinearity comes from the V-I converter. Also, the possible downconversion from the second harmonic of LO is neglected. Hence, the dc term of the can be given simply as The amplitude of the imd2 term at the output can be now written as

DC offset at the output follows again the same mismatch behavior. Only the tail current is added to the RF dependent term as

The second-order input intercept point is then

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The result can be now plotted as a function of LO amplitude. Several curves according to values given in Table 4.5 are collected to Figure 4.32. Some peaking in the IIP2 value is observed below the maximum gain. In some conditions it is negligible, but may lead to a high maximum if mismatches cancel perfectly. Maybe a more important result from the analysis is that only a variation in can change IIP2 about 10 dB in the switching as seen from curves 1-3. On the other hand, curves 6-8 indicate that IIP2 can degrade or improve when LO amplitude is increased depending on the mismatch. The sensitivity of IIP2 even to small mismatches is shown again with a more realistic model. Still, the model is a very simplified version compared to practical situations and more variables is probably needed. However, the simple approach allows practical means to calculate some selected sources of mismatch and study their consequences on the IIP2 behavior. This approach can be extended to double-balances circuits or MOS switches. Unfortunately, the large-signal modeling of the commutating switches is difficult and even quite simple functions as used here cause difficulties in the analysis. It is very likely that these observations can be utilized in a practical circuit design, for example to select a good strategy for simulations, which are typically very heavy for mixer circuits.

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4.4.5

BiCMOS Transconductance Mixer

The given discussion has pointed out several critical factors in the design of direct conversion mixer. In the case of a BiCMOS process, the use of MOS input stages and bipolar core transistors as shown in Figure 4.33 provides an optimal topology for the circuit design. The MOS input stages are more linear and a channel length is sufficient for the 2 GHz operation. Likewise, bipolar devices in the commutating switches can be relatively small and still have low enough flicker noise even when the total noise figure of the receiver is about 5 dB. The BiCMOS mixer has been therefore used both in the direct conversion chip set [94] and single-chip version of the same WCDMA receiver [39]. Some mismatch simulations have also been done for this structure. Those are plotted in Figure 4.34. The mismatch of 1 % in the load resistors drops the IIP2 already below 60 dB in this configuration. Also, the emitter resistances in bipolar core have almost equal effect. The imbalance in the V-I converter is modeled here as a variation in the threshold voltages of the input devices. The same relative mismatch causes less degradation in the performance, which indicates that the two former mismatches are more important for the IIP2. The simulations were performed only for a single mismatch at a time. The combined consequences of several parameters should be characterized separately with carefully selected combinations.

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4.5

Downconversion by Subsampling

The basic principles and limitations of subsampling as a mixing operation were described already in the previous chapter in connection with direct digital receivers. In this section, the conversion efficiency of a subsampling mixer is calculated. In comparison to other passive mixer structures the fundamental loss can be smaller due to the hold property and narrow aperture time of the sampling gate. This condition is valid for all subsampling mixers independently of the following circuitry. If the subsampling mixer is followed by discrete-time signal processing, either analog or digital, the behavior follows the special case when the duty cycle is zero because only discrete samples are processed afterwards. The finite aperture time however limits the tracking of the incoming signal and hence the high frequency behavior. The discrete-time case is a natural condition for subsampling and definitely most often used. The continuous-time circuitry after a subsampler would necessitate the filtering of the unwanted replicas around each clock harmonic. The intention is here mainly on the continuous-time approach because it is more general and allows straight comparison to other RF mixers. In direct conversion receivers, all typical constraints like flicker noise or dc offsets are present in subsampling as well. In addition to that, wide-band noise aliasing, direct dc feedthrough from RF circuitry and I/Q demodulation cause distinct problems in downconversion by subsampling. In the sampling process, harmonic components, generated in the switching operation, mix with the band-limited input signal and produce replicas over a wide range of frequencies. A replica, located at baseband or close to it, can be used as a downconverted signal in baseband or IF signal processing. Therefore, in comparison to classical continuous-time mixers, an additional degree of freedom for LO frequency selection is available. To prevent aliasing of signal replicas, a sampling frequency at least twice the signal bandwidth must be chosen. By appropriate choice of the switch duty cycle a small conversion loss for a passive structure can be achieved. To produce the desired IF frequency a set of sampling frequencies can be chosen given by the equation where n is an integer. In Figure 4.35 two different sampling frequencies produce the same IF. The clock harmonics of sampling pulses and possible spectral replicas for the analog signal processing are shown in the picture. The amplitudes of the different replicas depend on the gate function in the sampling as will be shown below. The higher sampling frequency produces less harmonic components close to the desired IF. The more significant benefit of using a high sampling frequency comes from the fact that every switching harmonic converts noise around it to the baseband. Because one source of the noise is the switch resistance of the sampler, the internal noise aliasing problem can only be reduced by increasing the sampling frequency or by reducing the on-resistance of the switch if possible.

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The conversion efficiency of a subsampling mixer can be obtained from the simplest possible description of a sampler including only the switch resistance and hold capacitor in Figure 4.36. The circuit has two operation modes, which depend on the switch position. When the switch is closed the output tracks the input and the operation corresponds to first-order lowpass filtering. There is thus no frequency translation. Opening the switch turns the sampler to the hold mode, and the output retains the final value of the input until the switch turns on again. The sequence of samples forms a hold envelope in the time domain at the intermediate frequency according to

where m is the harmonic component of the sampling frequency closest to the RF frequency. Thus, the hold mode converts the signal power down to the desired IF by appropriate choice of sampling frequency. Because of fast transients during the changes between two operation modes, the signal spreads over a wide range of frequencies. Theoretically it can be shown that the desired IF component can be designed to be much larger than the unwanted spurious responses thus yielding a small conversion loss for a passive structure. Before that, the following conditions must be met to validate the simple analysis and give the first level design prerequisites. Signal bandwidth is limited to the half of the sampling frequency to avoid spectral aliasing. That is typically done with the preselection filter located directly after the antenna in the receiver front-end. In the circuit, the time constant for charging the hold capacitance must be small compared to the time duration while the switch is closed in order to track the input. The falling edge of the sampling pulse must be steep enough so as not to limit the input bandwidth. The circuit output should be terminated with a high impedance buffer to minimize signal droop during hold. The behavioral model given here assumes infinitely fast rise and fall times of the sampling pulses. The shape of the sampling function and its effect on the high frequency behavior has been analyzed specifically for a MOS switch in [220].

In the track mode the input signal function. For a single tone input the output is

is multiplied directly with a rectangular gate

166

where is the interval between samples and is the width of the pulse. The effect of the hold can be obtained when the rectangular hold function, which is non-overlapping with the gate function, is convolved with the sampled values taken at the moment when the switch turns off giving

The clock duty cycle is taken as a separate parameter used later in the analysis. Track and hold mode waveforms are non-overlapping in time and therefore the output can be defined by their superposition both in the time domain and in the frequency domain. The Fourier transform of the output is thus

For the sinusoidal stimulus Fourier transform of the input

Equation (4.85) can be rewritten by using the

To calculate the conversion efficiency at zero IF, first the set of outputs which can produce zero frequency components must be defined. It happens only when is an integer multiple of the sampling frequency, called m according to Equation (4.82). We get

It produces the replica at DC when m=-n and hence the downconverted component is

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When the desired IF is much smaller than half of the sampling frequency, the previous formula approximates the transfer function at low intermediate frequencies accurately and simplifies analysis. The subsampling ratio of the signal is defined as

where is the incoming signal frequency, which should be below the sampler -3dB point and produce an integer value for Thus, the power conversion efficiency for an arbitrary sampling pulse width and ratio is

The theoretical conversion efficiency is shown in Figure 4.37 as a function of the clock duty cycle. The thick solid line describes the case when the subsampling ratio is very large and the two last terms in Equation (4.90) are negligible. The first term comes from the hold function and the two last terms describe the tracking behavior. If the subsampling ratio is relatively small the tracking terms are significant for the conversion efficiency. Their correlation to the hold function has not been studied, but the extreme cases when the track and hold function sum, as in Equation (4.90), or subtract are plotted with dashed lines in Figure 4.37 when the subsampling ratio is 8. The zero duty cycle represents the case when discrete-time signals processing follows the mixer immediately after the downconversion.

Equation (4.87) shows that any input frequency located at some harmonic of the sampling frequency will alias down to the baseband. The input bandwidth of the sampler limits the noise at high frequencies like a first-order lowpass filter, and the aliasing from external sources is theoretically avoided with the bandpass filter in the receiver front-end. But the noise generated

168

after the filter will be aliased as any other input frequency, and hence the noise performance will deteriorate as a function of the subsampling ratio. In practical receivers operating in the 1-2 GHz range, the stopband attenuation of the prefilter is far from ideal, and the front-end amplifier introduces noise outside the RF-band as well. In principle, a noise filter in front of the sampler would reduce the previous phenomena, but the noise generated by the switch can not be avoided. Therefore, the noise aliasing is an inherent problem for subharmonic samplers and can be seen in the noise figure performance. The implementation of a continuous-time subsampling mixer will be described in the next chapter.

4.6

Single-Chip Radio Receivers

Single-chip is a very flexible concept in connection with the radio transceivers. Sometimes a combination of two independent blocks on the same chip may be sufficient for advertising single-chip operation. However, strictly speaking a single-chip receiver would require all digital coding necessary to separate the transmitter data bits from the channel coding on the same IC with the LNA. It is anyway appropriate to exclude the antenna and preselection filter. The recent results have been shown that the integration level in the receivers has been increased significantly. Still there are only few examples of the RF front-ends on the same chip with digital circuits operating during the reception [15], [17], [39], [64] and [95]. The single-chip receiver is hence used here when the LNA is operating on the same chip with switching digital circuits. The analysis is not limited only on the direct conversion architecture, but is applicable for all single-chip receivers having small signal levels at the input. It will be assumed that the clock signal and its harmonics are the worst possible interferers because the clock switches from rail-to-rail even when the sensitivity is measured. All other spurious tones, which are generated in the mixing of the clock and unwanted input signals, are defined with blocking and intermodulation tests. Those tests allow higher spurs because of increased signal levels. Subsection 4.6.1 discusses more detailed about the issue, and it will be shown that the difference between sensitivity and other receiver tests is significant in the presence of clock spurious. Relatively little discussion has been given earlier on the possible effects of the clock feedthrough on the receiver performance. The frequency-hopped direct conversion receiver in [15] has only limiting amplifiers on the back-end of the analog signal path and the digital demodulation is performed on a separate chip. However, a direct digital frequency synthesizer operating with about 100 MHz clock is placed on the same die. Unwanted signals at the input generate a baseband replica with the spurs of the frequency synthesizer. The performance was measured at certain frequency offsets from the LO. In the worst case, the signal at 43 dB above the reference level produced the same response as the desired at the baseband output. The harmonics of the clock do not directly fall on the 902-928 MHz band of interest. The other papers do not mention any potential problems considering the effect of clock feedthrough on the receiver performance. The focus is here on the integration of the A/D converter on the same die with the RF front-end including the LNA. This subsection explains some backgrounds, and especially the frequency planning issues. The measurement results of the single-chip WCDMA receiver will be given in the next chapter. The RF front-end operates at 2 GHz range and the 6-bit ADC is clocked nominally at 16.384 MS/s i.e. four times the chip rate. However, the ADC was designed also for higher channel bandwidths and can be clocked up to 65 MS/s. This necessitates higher rise and fall times from the digital circuitry increasing the harmonic content of unwanted spurs.

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4.6.1

Frequency Planning in Mixed-Mode Implementations

In principle, the frequency plan of a direct conversion receiver is more straightforward than in the case of other receiver architectures due to the absence of the intermediate frequency processing and the strong image frequency components. However, the integration of the radio receiver on a single chip including the A/D converters combines strong clock signals with the sensitive RF front-end on the same die. Hence, the coupling of the digital signals to the RF input port becomes an additional parameter in the design. The clock feedthrough is considered here as a new source of spurious tones, which decreases the sensitivity of the receiver. In the analog signal processing environment, the possible harmonic combinations of the different tones can be given as

where is the desired channel, the local oscillator (LO) frequency, and are the independent blockers in the system input, and the output frequency of the transmitter. The factors k, m, p, q and r are positive integers. However, only a few of them are susceptible to cause unwanted spurious distortion in the passband of the receiver. The desired IF frequency is It is assumed that the relatively narrow-band preselection filter removes all out-ofband harmonics in the antenna to the level, which does not cause any unwanted spurious with other tones in the receiver. Also, the relatively linear nature of the radio receiver prevents efficiently the generation of the higher harmonics from the desired signal, which can distort the received waveform itself. Instead, the spectral regrowth problem occurs in the efficient nonlinear power amplifiers. Because the wanted nonlinearity, which performs the downconversion, is designed to be much stronger than any other nonlinear phenomena in the signal path, it is appropriate to assume that the desired RF signal can not generate any harmful spurious with any other tone in the receiver. Therefore, the term can be ruled out from the possible spurious frequency components. A blocking signal can occur at any frequency, and the receiver must operate in the vicinity of numerous strong interferers. In CDMA systems, also the other code channels at the same radio channel can be considered as blockers to some extent. Of course, their power levels are strictly controlled in the system. To keep the spurious generation mechanisms at a general level, Equation (4.91) initially contains two different blockers, which represent all possible combinations. However, the two different blocking signals at the passband of the preselection filter can be replaced with a single tone because the nonlinear behavior of those two input tones is limited already in the third- and second-order intermodulation tests. The intermodulation tests detect again the dominating source of the nonlinearity caused by two input tones in the system, and hence rule out the susceptibility of other mechanisms. Also, because of the band limitation at the input of the receiver and relatively linear characteristics in the signal path, the fundamental tone of the blocker is the most probable source in the generation of spurious tones. The interference from the transmitter is insignificant in the TDMA systems, which can use time division duplexing. In CDMA systems, which typically do not have the time duplex division, the transmission and reception are continuous and the transmitted power can leak to the receiver and distort the reception. Due to the simultaneous operation, the transmitter power leakage is not allowed to desensitize the receiver, or in a strict sense not to deteriorate the sensitivity of the receiver at all. Hence, the power leakage to the input of the receiver should be below the receiver 1 dB compression. If the receiver avoids the desensitization due to the transmitter leakage power, the tone itself is filtered out in the channel selection filter later. Hence, the leaked transmitter power can be considered as a blocking signal, and in the harmonic analysis

170

the possible blocker can exist either in the reception band or at the corresponding duplex frequency. Hence, the Equation (4.91) can be simplified as

It is appropriate to assume that the significant high frequency LO harmonics are limited up to the third-order products. It can be seen from Equation (2) that if the blocking signal is not located in the offset which is smaller than the channel bandwidth from the LO frequency or its harmonics, the spurs will be filtered out in the channel filter. That necessary condition is naturally avoided as explained above. The analysis becomes complicated immediately when the clock signal and its harmonics are added to the analysis. The high-speed clock requires fast rise and fall times, which produce a wide range of harmonic components up to the RF frequencies. The harmonic contents and the parasitic leakage depend on several factors, which are difficult to predict. The parasitic coupling through substrate or between long metal wires, the mutual inductance of the bonding wires or the pins of the package and the coupling outside the chip, including the printed circuit board, are all possible mechanisms for unwanted leakage. An overview of substrate coupling issues and floorplan strategies for mixed-mode circuits is given for example in [221]. Potentially, the most sensitive node to the distortion is the RF input port, because the in-band interferers are amplified with the same large gain before the A/D conversion as the weak desired signal. Also, the clock signal can couple to the LO port, modulate the LO, and hence downconvert an unwanted blocker to the baseband. The single-chip receiver with potential interferers is shown in Figure 4.38.

Depending on the clock waveform the even and odd harmonics of the clock signals behave differently. For example, the input amplitude and the clock interface to the chip may have a strong effect on the harmonic content. The ratio between even and odd harmonics generated in

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the interface can vary when the amplitude of the clock generator is changed. Either even or odd harmonics can be stronger on-chip interferers following the distorted shape at the clock interface. Careful spectral analysis is hence required for all clock harmonics, and the possible dominating spurious of the single-chip direct conversion receiver can be given as

The potential clock harmonic can be in the order of several hundred of mV. Different possibilities to downconvert the unwanted spurious tones in the mixer are described in Figure 4.39.

Before analyzing the blocking problems, the mixing products of the clock and LO signal are considered. Both signals have very large amplitudes and therefore they are the most susceptible sources of unwanted spurious. Also both signals are always present, which means that the sensitivity of the receiver can be deteriorated. Because the LO signal is close to the pure sinusoid, we can expect that the component is the dominant spurious. Typically, the digital clock is at the symbol rate or some multiple of it. If the LO is a multiple of the symbol rate, the distortion will always be located at DC, and the component is filtered out with other DC offsets in a direct conversion architecture. However, it is not possible to place adjacent channels in the radio communications exactly at the distance of the symbol rate, because otherwise perfect brick wall filters would be required both in the transmitter and receiver to limit the band. On the other hand, doubling the distance between the adjacent channels would waste the radio spectrum too much. Hence, it is always possible to find a channel, which is sensitive to the mixing products of the clock and LO due to the spurious tones at the passband of the channel selection filter, if the clock frequency is not raised above the system bandwidth. That would increase the power consumption of the digital circuitry and ADC, which is probably not acceptable. Theoretically, the other option is to use an asynchronous clock, which samples the ADC at a multiple of the channel bandwidth. The feasibility of such an arrangement is not in the scope in this context, but the synchronization to the chip rate must be recovered with digital multipliers and dividers, for example. The different signals and their strong harmonic components are shown in Figure 4.40 for the RF input, LO and clock. The possible spurious frequencies caused by the fundamental tone of the LO and the harmonics of the clock are shown in Figure 4.41 for the lower WCDMA band. The triangular curve describes the spurious frequency when the LO is swept, and the circles show the actual
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LO frequencies spaced at 5 MHz. The channel selection filter attenuates the spurious above 2 MHz, and hence only two LO frequencies out of twelve are potential candidates to deteriorate the performance.

The degradation of the sensitivity due to the clock distortion can be defined by measuring the noise figure or the sensitivity when the is exactly at dc, and then changing the LO slightly, which moves the spurious to the passband of the channel filter. In CDMA systems, the narrow-band spurious will be spread over the band when the channel is decorrelated. Hence, the effect should be determined by integrating the noise and distortion over the channel bandwidth. However, it is important to define the frequency of the narrowband tone to distinguish the possible source of the spurious. In the measurements, the output of the A/D converter can be transferred to the frequency domain with the fast Fourier transform (FFT). If the narrow-band spurious tone is considerably higher than the noise floor at the output, the degradation of the performance due to the spurious

173

can be determined directly from the rms-value of the spurious tone with a sufficient accuracy. The tone is compared to the total noise voltage at the output or it can be referred to the input power with the associated gain and impedance level of the input. Of course, the noise floor depends on the resolution of the FFT. The input referred power as a function of the spurious tone at the output is given at 95 dB of total gain in the receiver Figure 4.42.

Because in CDMA systems the spurious tones can be compared to noise, it is possible to define the noise factor, which includes the effect of the spurious as

where is the noise figure without a spurious component, the input referred power of the spurious tone and the thermal noise at the input i.e. kTB. Because the system noise depends on the bandwidth, the wide-band systems are less sensitive to spurious tones, which can be seen in Figure 4.43. However, even in the case of wide-band systems the spur must be below at the input of the ADC. This means about 130-dB isolation requirement of the digital rail-to-rail signal to the RF input with 2.7 V supply and 95-dB total gain. The degradation of the sensitivity due to a spurious tone is defined here as the difference of and It will be used later when the measured results are given.

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Equation (4.94) is an appropriate definition of the receiver noise figure when the spurious is caused by internal distortion as is the case with LO and clock signals. If the spurious contains an external blocking signal, the tone should be compared to the allowed noise and distortion level for the specific test. It is typically 3 dB higher than the noise level. However, the leakage of the transmitter power should be considered as an internal source, because it is always present when the system is operating if the transmission is continuous. If the unwanted channels are attenuated sufficiently before the clock or any other switching signal than LO is connected or coupled to the direct conversion receiver, a blocking signal can only compress the weak desired channel by reducing the gain of the system. In a single-chip receiver, a blocker can also generate spurious tones at the baseband with the clock signal. From Equation (4.93), two potential mechanisms can be observed. Either the blocker and the nth harmonic of the clock directly generate a spurious tone, or the LO signal is involved in the process. In the former case, n is large, but in the latter both the blocker and LO are at the same frequency range and hence the order of the harmonic of the clock can be small. When the blocking signal is located at the distance of the clock frequency from the LO, the fundamental of the clock is a part of the baseband product as The two different mechanisms can not be separated at the baseband because the LO frequency is converted to DC, and hence if n can be any integer value, the closest frequency component of from either LO or DC locates at the same frequency. The blocking signals are typically modulated channels, and their bandwidth must be taken into account in Figure 4.41. Thus, in the case of a single-chip direct conversion receiver the blocking test should characterize two different phenomena i.e. compression of the desired channel and desensitization of the reception due to spurious tones at the passband. It will be shown in the measurements of the single-chip DCR that the desensitization due to spurious tones dominates the upper signal range with some specific frequency combinations.

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4.7 IC Implementations
Finally, several reported direct conversion receivers and RF front-ends for direct conversion receivers mainly for cellular applications are collected in Table 4.6. The direct comparison is unjustified because of the different radio frequencies, channel bandwidths etc. in various applications. It is evident that for example in pagers the direct conversion has been a mature architecture already for a long time while in some systems it is still an unrealistic solution. It should be also highlighted that all given direct conversion receivers are very different entities. For example, the implemented blocks on the reported structures vary a lot, which directly reflects in power consumption etc. Some specific details are commented separately, but the given notes are definitely not very complete. The number of chips in Table 4.6 counts only the analog chips including the A/D converter. Digital parts are not discussed. Sometimes the transmitter is placed on the same chip, but the interest is here only on the receiver applications. The given baseband bandwidth indicates the cutoff frequency of the lowpass filter. The references [38] and [39] are the chip set and the single-chip version of the WCDMA receiver discussed here. The specific results of the RF front-end are given also in [185]. Those references are highlighted in Table 4.6.

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177

References
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Circuit Implementations

In this chapter four different circuit implementations are described. Two of them are involved in the design of direct conversion subsampling RF front-ends and the other two are more conventional direct conversion receivers for third generation wide-band CDMA systems. The circuits are presented in the chronological order. The first chip is a subsampling mixer implemented with a digital GaAs MESFET process. Low loss was achieved using narrow and sharp strobe pulses for sampling. The second circuit is a differential LNA for a subsampling RF front-end using CMOS. The main emphasis was to build an optimized ac-coupled interface to a parallel track-and-hold network for RF subsampling. Unfortunately, the measurement results of the chip were not satisfactory, and the characterization is here theoretical. The optimization techniques described in section 5.2 are however straightforward and applicable to interfaces between the LNA and a direct conversion mixer in general. They are especially useful in standard CMOS processes without high-quality passive components. The last two sections cover the circuit design and experimental results of a direct conversion WCDMA receiver. The both versions are implemented with a 25-GHz BiCMOS process. In the first version, the RF front-end and analog baseband circuitry are placed on different dies, and the separate 6-bit A/D converters use CMOS. In the second chip, all functional blocks from the LNA to 6-bit digital outputs are on the same die. The circuit structures originate from the former chipset. The single-chip receiver can handle channel bandwidths up to 8 MHz at baseband with 65-MS/s ADCs and tunable channel selection filters. The background for all the implementations is described already earlier and only the circuit design aspects and experimental results will be given in this chapter.

5.1

Subsampling Mixer

Subharmonic samplers in the RF frequency range have been used up to 1 GHz as a separate mixer [1], as a part of the receiver front-end including filtering [2] and in a picocell wireless terminal prototype [3]. Some recent direct digitization GPS receivers use the same principle in the front-end at 1.5 GHz [4], [5]. Here, a fully integrated subharmonic mixer with an on-chip strobe pulse generation circuit capable of handling input signals up to 2 GHz with small conversion loss and high third-order intercept and compression points will be described [6]. It uses a pair of two-diode bridges and operates with a single 3-V power supply, which is low for a diode bridge sampler. This approach uses a relatively high sampling frequency to reduce the noise aliasing problem inherent in subharmonic samplers. The highest available sampling frequency 1.5 GHz is at the range of a typical input signal bandwidth of a mobile receiver.

5.1.1

Circuit Description

Sampling circuits can be roughly divided to two categories according to the switch type. Diode switches are often used when high-speed switching is needed, but at lower sampling frequencies transistor switches are the dominant choice. Most subsampling mixers use CMOS switched capacitor track-and-hold circuits [1], [2], [3]. This topology limits the clock frequencies to approximately 100 MHz, and hence the input bandwidth of the mixer is close to the Nyquist limitation for wireless communication systems like GSM which have a 30 MHz receive bandwidth. The intention was here to use a topology capable of operating at smaller

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subsampling ratios in order to reduce the effect of noise aliasing and to minimize the conversion loss. The circuit consists of two sampling bridges, an output buffer, and the strobe pulse generation circuit. Figure 5.1 shows the block diagram of the downconverter. The differential high frequency input signal is divided to two separate single-ended samplers, which have a common differential buffer at the output. Differential signal processing, although expensive in terms of power, is preferable in RF circuitry because of the insensitivity it provides to common-mode distortion from the substrate and supply voltages. Isolation is very important when high-speed clocks are present in the RF circuitry. In addition to that there is a requirement for separate analog and digital supplies. Although the strobe pulse generation is implemented with differential structures, the top and bottom nodes of the sampling bridge are finally controlled by two separate single-ended pulses, which have opposite phases. A slight asymmetry between pulses is inevitable. At small input signal levels, the asymmetry dominates charging the hold capacitor from sample to sample to one direction and thus limiting the dynamic range. With two separate bridges the error cancels out in the output buffer when the differential branches are recombined. The strobe pulses are generated on-chip from an external signal source.

5.1.1.1

Sampling Bridge

Diode bridge design with FETs and a low supply voltage has the problem that it requires large amplitude sampling pulses. Schottky diodes are easily implemented in a MESFET process, but the commonly used four-diode bridge requires current sources on the top and bottom of the bridge to supply sufficient current during the track mode. Hence at turn on, two diodes and two current source transistors in saturation are in the stack between the supply rails simultaneously. The minimum saturation voltage of a depletion mode transistor biased at is close to 1 V in a typical MESFET process. Hence, the smallest possible supply is theoretically 3.4 V. DC isolation between the bridge and current sources is not possible because the discharging of the coupling capacitors is too slow while tracking and the continuous charging of the capacitors from sample to sample destroys the operation. The trend towards low supply voltages requires the use of alternative topologies in diode bridge samplers implemented with MESFET technologies.

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The two-diode bridge [7] in Figure 5.2 is capable of operating with a low supply voltage because the strobe pulse circuit can be ac-coupled. The initial design specification was 3 V, but in the measurements the strobe pulse generator was insensitive to supply variations from 2.7 V up to 5 V. The diodes conduct when the sharp strobe pulses pull the voltage over the turn-on point. The current from the pulse generator charges the hold capacitor to a voltage proportional to the input. The falling edge of the strobe turns off the diodes and switches the sampler to hold mode. In the hold mode, the hold capacitor connected to a high impedance buffer keeps its value with a small droop. Simultaneously, the coupling capacitors discharge through the bridge resistors because the output node of the bridge is at a virtual ground for the strobe circuit. The resistors also keep the voltage at the top and bottom of the bridge equal to the output during the hold mode, and therefore no reverse biased bootstrap diodes are needed.

5.1.1.2

Output Buffer

In a subsampling mixer followed by continuous-time circuitry, discharging of the capacitor during the hold mode decreases the conversion efficiency. On the other hand, if discrete-time samples are processed after the circuit the same effect can be handled as a reduced voltage value directly proportional to the time constant. In both cases, a high impedance buffer after the sampler is needed to minimize the droop during the hold mode. A differential common source amplifier with resistive loads was used followed by two emitter followers driving the loads in the measurements. A common source stage provides a high input impedance and good common mode rejection. The bias to the input transistors is brought through the bridge to avoid discharge through the biasing circuit. The simulated buffer gain is 4 dB.

5.1.1.3

Strobe Pulse Circuit

As given in the previous chapter, the conversion loss is minimized when an infinitely narrow sampling pulse is used. However, the hold capacitor can not be charged instantaneously to the full input voltage. In the two-diode topology, the time constant charging the hold capacitor depends on the current from the strobe pulse generator. Therefore a strong clock buffer is required to optimize the circuit performance. The sampling pulses are generated by a SourceCoupled FET Logic (SCFL) differential delay chain coupled to an OR gate as shown in Figure 5.3 [8]. A sinusoidal LO input of approximately 0 dBm is amplified, and the delayed edges of the LO produce positive and negative sampling pulses as illustrated in the timing diagram. The generator produces strobes with fixed pulse widths at different LO frequencies. The simulated pulse width values of approximately 350 ps give enough time for the circuit to set up the track mode when the switches are on with the designed clock buffer. Thus, the duty cycle at a

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500 MHz sampling frequency is 0.18, which gives the theoretical conversion loss of 2 dB. Except in the clock buffer, standard SCFL cells with resistor loads are used to avoid the effects of uncorrelated process variations between enhancement and depletion transistors. The clock buffer shown in Figure 5.4 amplifies the pulse swing above the diode turn on point and feeds sufficient current to the bridge. Because of the capacitive coupling to the bridge, only the relative swing between the positive and negative branch is important, relaxing the absolute dc level requirements with low supply voltages. In this case transistor loads are required in the intermediate stage to produce sufficient amplitude swings.

5.1.1.4

Layout and Fabrication

The circuit has been fabricated using E/D-MESFET process designed for digital VLSI circuits. The process did not support inductors, and the capacitors built from three wiring layers had small capacitance per unit area and large parasitics to substrate. The capacitors were implemented using a sandwich structure shown in Figure 5.5 to minimize the area and

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parasitics. The top and bottom metal layers were connected together forming two parallel capacitors with the middle plate. The coupling capacitors between diode bridges and clock buffer require special attention because the parasitic capacitance from the signal nodes to ground is unavoidable. The parasitic capacitance from the bottom plate to the substrate is of the order of 50% of the capacitance value between two metal layers. By placing the bottom metal on the clock buffer side a significant part of the strobe current will flow into ground ruining the circuit performance. Connected the other way around the parasitics do not have significant effect on the strobe pulse swing and current in the bridge. The photograph of the fabricated circuit is shown in Figure 5.6. The active circuit area is including 77 transistors.

5.1.2

Measurement Setup

Spectral measurements were done to evaluate the circuit performance. A 180-power splitter and biasing blocks were connected between the circuit and the RF synthesizer to produce the differential input. The output was combined with a discrete 180 hybrid. Due to the dc-block at the output, the lower frequency limit was fixed at 100 kHz in the measurements, and the direct conversion performance must be evaluated based on this low IF. Most of the measurements

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were done at a 5-MHz IF output. A separate synthesizer using the crystal reference from the RF source generated the LO for the sampler. Noise figure measurements of a subsampling mixer must be also done with a spectrum analyzer because the large number of harmonics and different mixing principles interfere with the operation of a noise figure meter in the mixer measurement modes, and thus the results are not reliable. Many modern spectrum analyzers have a separate noise spectral density measurement mode, which is accurate and takes into account the filtering in the analyzer itself, for example. Often, the internal noise of the spectrum analyzer exceeds the output noise of the device under test, and a separate low-noise amplifier is needed to amplify the noise from the DUT up to the measurable range. If the difference between the analyzer noise and the output noise is small the result can be scaled to correspond to the desired noise value when the internal noise floor is known

where is the measured value including both circuit, and spectrum analyzer noise, in dBs. is the gain of the low-noise amplifier. The noise measurement setup is shown in Figure 5.7. The noise figure of the downconverter is calculated by definition from the measured output noise, circuit gain and -174 dBm/Hz input noise spectral density introduced by the termination.

5.1.3

Experimental Results

The circuit met the design objectives of 2-GHz input bandwidth with a small conversion loss, and the measurements matched well with the simulations. The input response is defined to a fixed IF in Figure 5.8(a) at a 500-MHz sampling frequency. To achieve sufficient resolution in the measurements at relatively small sampling rates, the LO frequency is adjusted to the closest possible value that produces the desired IF when the RF is swept over the band. The notch at 2 GHz is due to the imperfections of the probe card used in the measurements. This means that the mixer is capable of operation at two or more different frequency bands using the same system configuration. Of course, the system requires separate preselection filters, and to minimize the noise, the input bandwidth must be restricted up to the highest frequency band. The IF band of the circuit was limited by the external configuration in the measurement system. The IF frequency selection does not have a significant effect on the conversion gain over the measured range shown in Figure 5.8(b).

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The circuit was measured with two different LO-frequencies of 500 MHz and 100 MHz. The results are summarized in Table 5.1. The 1-dB conversion loss is small for a passive structure and shows good correspondence with the theory and simulated performance. The slightly smaller system gain at the 100 MHz sampling frequency is the effect of signal droop during the longer hold period. The linearity has been measured both with one and two input tones in Figure 5.9. The former yields results comparable to [1] and the latter is normally used to specify the intermodulation performance of a mixer. The single-tone test actually gives the unwanted mixing product when the harmonic of the input signal mixes with a high harmonic of the clock rather than intermodulation of two in-band interferes. This may be a serious problem in wideband mixers where the second harmonic of the signal is not attenuated sufficiently by the RCproduct of the input. A high linearity has been achieved when compared to typical integrated continuous-time mixers. The compression point of +7 dBm is close to the theoretical maximum of the topology defined by the diode turn on caused by the input signal swing.

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The circuit can operate with a large range of sampling frequencies from 40 MHz to 1.5 GHz, and the minimum required LO input power is -2 dBm. The LO power fed to the sampling bridges is spread over the harmonics of the sampling frequency in the strobe pulse generator. The spectrum depends mainly on the digital clock circuitry including the buffering. The LO harmonics which leak to the circuit input can be divided into two categories whether the component is located inside or outside of the prefilter passband in the receiver front-end described in Figure 5.10. The LO leakage to the RF input is measured, and different harmonics are summed to give the total leakage power at 100 MHz and 500 MHz as -64 dBm and -56 dBm, respectively. In direct conversion receivers, self-mixing is a serious problem because the mixing product will be located at baseband together with the received signal [9]. In a subsampling mixer, all the leaked LO harmonics can self-mix down to baseband if reflected back before the preselection filter, and they can be treated equally at all sampling frequencies. The reflections from the mismatch in the antenna and the power from external reflections or near-by transceivers operating at the same frequency will be filtered out, and all harmonics except the one located at the passband of the preselection filter will be attenuated significantly. Although the internal self-mixing can be stronger, the spurious responses from external sources are more difficult to predict and compensate later with digital techniques. Because the power spreads over a larger number of harmonics, reducing the power per component when a lower sampling frequency is used, the low sampling rate gives even more benefit than the total LO leakage power indicates. In that case the harmonic in the prefilter passband is much smaller than the corresponding component when a high sampling frequency is used. In the described sampler, when operating at 1.5-GHz RF-input, the in-band harmonic leakage will be -61 dBm at 500 MHz sampling frequency and 15-dB smaller at 100 MHz. The difference is approximately the same at other harmonics as well. The nominal supply voltage is 3 V but the digital supply for the strobe pulse generator can be as low as 2.7 V. The strobe pulse generator dissipates 125 mW of power which is much lower than in some earlier diode bridge samplers [10], [11]. The output buffer needs to drive loads, and therefore consumes 102 mW. For an on-chip load the dissipation would be significantly smaller.

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5.1.4

Summary of the Subsampling Mixer

The described subharmonic mixer based on a diode bridge is capable of operating at mobile radio frequencies up to 2 GHz. A small conversion loss for a passive mixer (1 dB) has been achieved with high linearity. The circuit operates from a 3 V power supply and dissipates less power than many other diode bridge samplers. Noise aliasing is an inherent problem in subharmonic sampling, but it can be reduced by using high sampling frequencies. On the other hand, LO leakage to input is smaller at low sampling frequencies, which has special significance in direct conversion applications. Subsampling downconverters can replace traditional continuous-time mixers and use a low frequency LO synthesizer in superheterodyne or direct conversion receivers.

5.2

Low-Noise Amplifier and Interface to a Subsampling RF Front-End

The design of a 1.8 GHz CMOS LNA with an optimized interface to a direct conversion mixer is given in this section [12]. The LNA is designed to drive a capacitive load such as the load of a subsampling mixer. The output resonator limits the mixer input noise bandwidth, which is necessary to optimize the system noise figure. ac-coupling, an essential function in a direct conversion front-end, is realized with an on-chip structure, which has low sensitivity to parasitic effects. The subsampling mixer, which is on the same chip with the LNA, is reported in [13]. The hold capacitor of the track-and-hold circuit is a part of the load resonator of the LNA. The most harmful part of the offset in the direct conversion comes from the second-order nonlinearities, which mix any combination of the two non-desired channels passing the preselection filter directly to a dynamic error at baseband. A large coupling capacitor can be used to remove the dc offset caused by the second-order nonlinearities from the LNA. An on-chip realization would require a large area and the parasitic bottom plate capacitance to silicon substrate would destroy the signal swing in the interface between the LNA and the mixer.

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5.2.1

Low-Noise Amplifier

The low-noise amplifier uses the most common architecture i.e. inductive degeneration scheme with a cascoded input shown in Figure 5.11. Matching criteria for differential amplifier described in the previous chapter was used. The gate resistance was not included in the MOS model, but it was minimized fingering the large input devices. The value was estimated using the effective gate resistance given by [14]

for a transistor with the total gate width W, length L, and n number of fingers in the layout each having gate contacts only at one end of the transistor. is the sheet resistance of the gate polysilicon. The gate noise contribution can be reduced by a factor of four when contacting the gates at both ends. The thermal noise current for a MOSFET operating in saturation is

where the factor is 2/3 for a long channel device. In submicron technologies the has been shown to be significantly larger than the above value and the value depends on the biasing conditions in saturation [15]. The commonly used approximation of 2.5 was used in the simulations. The power consumption versus noise figure has been optimized with the method described in [16]. The quality factor for the input stage is defined by

where is the resonance frequency of the matching network. and are the gate and source inductors, respectively. The M1 bias current was chosen to be 7 mA for a 3 V supply, and the gate width based on the optimization was for the transistor M1 at the input signal frequency of 1.8 GHz.

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5.2.2

Resonator Load with On-Chip Coupling Capacitors

In most cases, an LNA drives an inductive load, in Figure 5.11, which is matched to a output with a series capacitor or with a separate buffer. An inductor load is ideally noiseless and allows a large signal swing at the output even with a low supply voltage. In this case, the LNA is driving a sampler, which has a capacitive input. The sampler processes the input signal as a voltage value over the capacitor, and therefore an output matching to a lower impedance level is not required. On the other hand, the sampler has a wideband input. As a subsampling mixer, which has the bandwidth at least up to the desired input frequency, it aliases all the incoming noise down to the Nyquist domain defined by the sampling frequency. Any structure limiting the noise band at the input of the sampler will improve the system noise performance. Hence, the sampler input can be designed to operate as a parallel resonance circuit at RF. Typically, the coupling capacitor required in the RF front-end is as large as possible and therefore negligible at the signal frequency, or it can be used as a series matching element. In ideal case, the same is also valid for the capacitive load because of the capacitive voltage division between the coupling and sampling capacitances would reduce the voltage swing at the output. The integrated capacitor has a large parasitic bottom plate capacitance in series with a substrate resistance to ground. The parasitic effects shunt the signal to ground, and they may significantly shift the center frequency and ruin the Q-value of the resonance circuits. The parasitic capacitance was estimated to be an eighth part of the based on the available process data of the applied CMOS. If the value of is in the same range with the sampling capacitor, i.e. and hence the resonance peak will be strongly dependent on small variations of and The reduction of the coupling capacitor to be smaller than minimizes the effect of the both parasitics, and the simulations showed improved performance compared to the large case with excellent insensitivity to value. The inductor can be placed either to bring the bias current for the transistors M1 and M2, or to avoid the gain degradation, on the other side of the in parallel with the capacitive output as shown in Figure 5.12. The former presents a traditional LNA architecture having the benefits described in the beginning of this section. The latter suffers from the need of a separate bias current network.

To compare the two given alternatives the small signal equivalent circuits were simulated. In Figure 5.13, a detailed model is shown for the resonator of Figure 5.12(b). Hence, the resonator is not any more a simple LC-tank, and the performance must be optimized taking care of the additional capacitors and parasitic effects. In the simulations, the on-chip inductor was modeled with the resistive loss of to give a realistic approximation for the available Q. The case

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when the inductor is located in parallel with the sampling capacitor gives a better performance compared to the traditional topology as shown in Figure 5.14. The gain maximum with the same current is improved over 5 dB, and a much better isolation around DC can be achieved due to the pole, which locates closer to the resonance peak. The gain advantage comes from the high impedance of the parallel resonator, which allows the use of a small series capacitor without significant voltage drop over it. mitigates the effects of and In an integrated structure, the benefits of the described alternatives can not be combined using two inductors, because the two resonators should be perfectly matched to avoid collapse in performance. The resonator structure in Figure 5.12(b) was chosen and the biasing problem was solved separately.

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5.2.3

Current Biasing Circuit for the LNA

The bias circuit should be negligible for the resonator, which means a high output impedance at wide range of frequencies. In principle, an inductor can be used for biasing but the required value would be too large to realize even with an external component. Another choice is the LNA topology with a complementary input [17]. However, the PMOS in the desired process was too slow for 2 GHz operation. Therefore, PMOS was used as a load. The PMOS noise contribution can deteriorate the noise performance significantly. An LC-tank, formed by and in Figure 5.15, degenerates the PMOS channel noise current. The simulations indicate that the PMOS noise contribution is insignificant. The resonance frequency of the LC-tank is defined to be equal with the actual resonance to optimize the performance. Because the tank is not directly connected to the output, the resonator mismatch has little impact on the LNA gain.

5.2.4

Implementation

The circuit is designed for a standard CMOS process. A differential structure was used because the subsampling mixer uses an SC track-and-hold circuit, which requires a balanced input. It also improves the insensitivity to common-mode noise from the substrate and supplies. The input matching inductors and are implemented with the bond wires. performs also common mode rejection. The components inside the dashed line in Figure 5.15 are integrated on the same chip with the subsampler. In the simulations, a simple lumped tenelement model for the on-chip inductors was used [18]. The parameters were extracted from the measured test structures. The resonance frequency depends significantly on the inductor parasitics, and therefore an accurate experimental model is necessary. The microphotograph of the subsampling front-end is given in Figure 5.16 and the simulated performance is collected in Table 5.2. The frequency response is shown in Figure 5.17. The low-frequency isolation is excellent, and follows the theoretical curve in Figure 5.14. The different noise sources of the LNA were analyzed in the circuit simulator. The result indicates that the PMOS load with the degeneration circuit adds only 0.2 dB to the total noise figure and therefore does not deteriorate the noise performance.

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5.2.5

Summary of the LNA and Interface to Subsampling Mixer

The on-chip RF interface between the LNA and downconversion mixer with a capacitive input can be optimized using a small coupling capacitor. The LNA noise band has been limited with an output resonator to reduce the aliasing problem in the subsampling front-end. The on-chip coupling capacitor scheme eliminates also the feedthrough of the second-order nonlinearities into the output of the subsampling downconverter in a direct conversion receiver. The given interface is especially suitable for the standard CMOS processes, which do not have highquality passive components for the RF design. The LNA noise figure of 3.4 dB and 17-dB gain was achieved in the simulations. In the measurements, the spectral shape was roughly recovered as designed. The problems in the testing of the whole subsampling front-end however prevented the complete characterization of the LNA block as it. A PMOS load transistor delivers the drain current for the gain stage without interfering with the actual resonator. The PMOS noise contribution to the output was degenerated with a second on-chip resonator.

5.3

Chipset for Direct Conversion WCDMA Receiver

The chip set described in this subsection is the first prototype receiver published for the 3rd generation cellular systems [19], [20]. The system is often called either Universal Mobile Telecommunication System (UMTS) or International Mobile Telecommunications 2000 (IMT-2000). Later the term 3GPP (Third Generation Partnership Project) according to the standardization organization is also used in the meaning of the new system. In Europe and Japan, the Wide-Band Code Division Multiple Access (WCDMA) scheme will be adopted in the air interface. In the United States a slightly different path called cdma2000, which is backwards compatible to IS-95, has been followed in the standardization of wide bandwidth wireless systems. Although a lot of effort has been done to unify the different proposals, the future of the 3rd generation communications will be probably a family of systems for wideband communications rather than a single universal specification. The specifications of the chip set are based on the technical aspects of the WCDMA proposal in its original form, but the given structures can be easily applied to all systems using wide-band direct sequence spread spectrum (DS-SS) radio access. The major change from the original proposal is the reduced chip rate from 4.096 Mcps to 3.84 Mcps. However, the channel spacing is still 5 MHz. Hence, the required changes for the new specifications would be scaling of the cutoff frequency in the channel selection filters and reduction of the sampling rate in the ADCs. Table 5.3 collects the system characteristics of the original WCDMA proposal. In this approach, the receiver is also capable of handling wider channel bandwidths with a 10 or 20 MHz channel spacing to increase the chip rate and capacity of a single carrier. The extended data rates at the baseband and a higher sampling rate of the ADCs lead to different optimization criteria of the receiver blocks. Especially the power consumption of the ADCs depends on the sampling rate and reduces only little when clocked at a smaller rate. Therefore the power consumption is not optimized for the smallest bandwidth although almost all results are given with that nominal condition.

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The direct conversion architecture is adopted in the WCDMA receiver capable of operating both in mobile terminals and base stations using the proposed frequency ranges, channel bandwidths, data rates and modulation for the 3rd generation mobile telecommunications system. The receiver consists of the analog signal processing circuitry including analog-todigital converters, which suppresses sufficiently the adjacent channel and other interferers passing the preselection filter before digital signal processing. Coherent detection, pulse shaping, decorrelation, decoding, and demodulation are performed in the digital domain.

5.3.1

Building Blocks of the Direct Conversion Receiver

The direct conversion receiver in Figure 5.18 is distributed on four dies to avoid substrate coupling between the sensitive blocks. The low-noise amplifier (LNA) and quadrature mixers on the radio frequency (RF) die amplify and convert the signal for the baseband chip, which includes quadrature paths of filtering and controlled gain in a merged manner. The 6-bit analogto-digital converters (ADC) give enough headroom for efficient digital signal post-processing. The RF and analog baseband blocks use a 25 GHz BiCMOS process with a MOS minimum channel length while the ADCs are implemented with a CMOS technology. The external components are limited to input matching and supply decoupling at RF, and ground stabilization and four servo feedback capacitors at baseband.

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Highly integrated direct conversion CDMA receivers for lower data rates and narrower radio channels have been published for direct sequence [21] and frequency-hopped [22] ISM band (902-928 MHz) test systems. The WCDMA receiver is designed to operate in commercial cellular bands at the 2 GHz range, and the channel spacing can be digitally selected from 5 to 20 MHz. A digital signal post-processor is needed to despread and detect the data with variable rates in the third generation mobile communications. The direct sequence spread spectrum system provides a straightforward trade-off between the transferred data rate and the quality of service or the cell size by changing the processing gain in the constant chip rate transmission. The robust, digitally controllable analog front-end allows flexibility in the overall radio system design. The trade-off between noise and linearity at the baseband signal processing has been optimized using a merged filtering and controlled gain scheme after the downconversion. The applied scheme does not violate the filter transfer function, and the number of amplifiers is minimized. The measured results prove that the integrated baseband block does not significantly limit the high dynamic range of the receiver.

5.3.1.1

LNA and Downconversion Mixer

The RF front-end in Figure 5.19 has a differential bipolar LNA, which provides 20-dB gain, and uses bondwire inductances L3-L7 for matching and cascode transistors Q3 and Q4 to isolate the resonator load from the input. The inductor L5 is bonded directly between the emitter pads to increase the required component values. Otherwise the small emitter degeneration inductors (<1 nH) are very sensitive to variations and short wires are difficult to bond on the PCB. The on-chip resonator load consists of 1.7-nH inductors L1 and L2, and 2.7-pF capacitors Cl and C2. The LC-load has too narrow bandwidth for operation both in mobile terminals and base stations. To avoid external tuning of the resonators, they are de-Qed with on-chip parallel resistors Rl and R2 to achieve over 500 MHz bandwidth with a negligible degradation in the noise performance. The two 60-MHz frequency bands at a 190-MHz duplex separation can be covered with this arrangement and the process variations have only a minor effect on the low-Q resonator load. The biasing of the LNA is done using current mirrors from an external source. The LNA draws 4-mA supply current.

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The quadrature mixers use a modified double-balanced Gilbert cell topology in Figure 5.20. The NMOS input devices Ml and M2 provide high linearity and sufficient gain with a 4 mA of total mixer core current. On the other hand, the use of bipolar transistors as commutating switches minimize the critical flicker noise. To relax the linearity requirements of the baseband block, the 70-pF on-chip capacitors Cl and C2 form a pole with load resistors Rl and R2 at 6 MHz. The high-quality metal-insulator-metal coupling capacitors block the lowfrequency noise and distortion from the RF section and the local oscillator (LO) inputs of the mixers, and hence the low frequency leakage into the mixer output comes mainly from internal sources. The external LO is divided in quadrature by a second-order polyphase filter (RC-PP), and differential pair buffers compensate the loss of the polyphase filter. The RF chip operates down to a 2.1-V supply with negligible degradation in the gain and linearity.

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5.3.1.2

Interface to Baseband

A relatively low impedance level is required at the baseband input to keep the noise at an acceptable level. At the highest gain setting the differential input resistance of the baseband block is Therefore, low impedance output buffers are required to feed the baseband. The buffer gain drops 1 dB from the maximum when driving the baseband, which is a trade-off between the gain and current consumption. The DC level of the mixer output is set with a common-mode feedback (CMFB) circuit, which compares the node to the baseband voltage reference, and adjusts the DC current through the mixer loads Rl and R2 until the DClevel at the buffer output is correct. The two-stage amplifier used in the CMFB-circuit is shown in Figure 5.21. The CMFB limits the RF supply range from 2.5 V to 3.0 V when operated with the baseband circuitry, which requires input DC-level accuracy of approximately This has been shown already in the previous chapter when the interface to baseband is discussed.

5.3.1.3

Baseband Processing

The analog channel filtering is always a compromise between the adjacent channel rejection and inter-symbol-interference (ISI). Based on the discussion in the previous chapter the 5thorder Butterworth response was chosen as a prototype. In the baseband circuitry, Figure 5.22, a preamplifier is needed in front of the filter to reduce the filter noise contribution at high gain values. The pole of the preamplifier at the filter cutoff frequency relaxes the linearity requirements of the following stages. At lower gain values the pole moves to higher frequencies. The active RC filter implementation has high linearity and insensitivity to parasitic effects, and the Miller-compensated opamps are suitable for low supply voltage operation and achieve low noise. The merged filtering and controlled gain stages in Figure 5.23 optimize the noise and linearity performance of an active RC filter, and minimize the number of amplifiers at the baseband circuitry. The 78-dB gain control range can be adjusted digitally in 3-dB steps. The gain ranges and step sizes of different stages are collected in Table 5.4. The control is implemented with switched resistor matrices, and the shape of the filter frequency response is unaffected at all gain settings. The gains of the integrators are changed by scaling the input resistors. The shape of the response is kept constant by an opposite change in the feedback resistors as shown in Figure 5.23. In practice, the finite GBW of the amplifiers slightly changes the shape of the frequency response at high gain values. A corresponding technique can be implemented also with SC-filters as in [23].

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The filter can be programmed to three bandwidths from 2 to 8 MHz, which allow data transfer at the rates of 4.096, 8.192 and 16.384 Mcps. The channel bandwidth is selected and the filter frequency response tuned with binary-weighted 7-bit switched capacitor matrices. The frequency response tuning is 5-bit [24], [25], [26]. The channel bandwidth is selected by

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shifting the 5-bit tuning code. At the channel bandwidth of 2 MHz, the five most significant bits of the 7-bit code are used for the tuning of frequency response. The on-chip frequency response tuning circuitry is based on a single-ended time-domain test integrator [26]. The reference for the tuning comes from the same accurate external clock, which is used in the A/D converters. In the filter, the opamp GBWs are tuned according to the channel bandwidth by scaling the biasing currents. This optimizes the power consumption at different channel bandwidths. The servo loop, which filters out the dc component at the input and compensates the internal offsets of the baseband, is connected over the whole baseband excluding the output buffers shown in Figure 5.22. The servo amplifier is an active RC integrator with two 220-nF off-chip capacitors and on-chip high-ohmic polysilicon resistors. The highpass pole is located at 2 kHz with the highest gain setting and moves down when the baseband gain is decreased. Offsets up to 300 mV at the input of the baseband circuitry can be tolerated at all gain settings. The baseband block has been implemented completely with MOS transistors excluding the bipolar emitter followers as output buffers.

5.3.1.4 A/D Converter

The weak CDMA signals are buried in noise before despreading. Although the gain control adjusts the input level to an appropriate value for the ADC input, several bits are required to detect the desired channel, which is below the noise and different user signals propagated through multipath channels. It is estimated that 4- to 6-bit converters have adequate performance in the WCDMA environment [27]. The DCR uses two A/D converters, which employ a 1.5-bit/stage pipeline architecture with digital correction and interstage gain [28]. The pipeline architecture allows the use of low supply voltage and scaling of the capacitor values and amplifiers of the stages along the converter to minimize the power consumption in the highspeed medium resolution ADCs. The A/D converter was originally designed to have a resolution of 8 bits at a nominal sampling rate of 40 MS/s [29]. Hence, the power consumption is not optimized for 6-bit 16-MS/s operation used in the WCDMA receiver. The capacitor values, switches and amplifiers of the last three pipeline stages are scaled to compromise between the design complexity and power dissipation.

5.3.2

Layout

The microphotographs of the circuits are shown in Figure 5.24. The active silicon area of the receiver is distributed on four chips. Test structures on the RF die and large standard cells driving the ADC output are excluded from the given area. The layout symmetry in the differential RF block and the first stages of the baseband is the key element to achieve a high immunity against even-order distortion. For example, dummy crossings between different wiring layers are used to keep the capacitive loading equal in critical RF parts. Hence, the IIP2 depends mainly on the matching of the adjacent components, because no IM2 cancellation circuitry is used as in [30]. The RF and LO inputs are grounded properly on both sides and brought orthogonally onto the chip to minimize the LO-to-RF leakage due to the mutual inductance of the bond wires. The LO-to-baseband isolation is improved by placing the output bus far from the LO wires between the LNA and mixer. The long signal wires are drawn with a thick, low-resistivity top metal layer, which is used for inductors as well. In the baseband, the frequency tuning and reference blocks are placed between the channels to reduce the crosstalk between I- and Q-branches.

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5.3.3

Experimental Results

The four chips are mounted on two different printed circuits boards (PCB). The RF chip is glued and bonded directly on the PCB. The bondwires are used for input matching and several bonding pads are used for ground and supply to keep the parasitic inductance at an acceptable level. The simulated 0.5-dB loss of the RF input wires on the PCB is not extracted from the results. Due to the size limitations of bonding instruments the baseband and ADC chips are placed on a separate board. The baseband and ADC chips are in the standard CQFP64 and CLCC44 ceramic packages, respectively. The DCR is characterized with the 6-bit ADC clocked at 16 MHz for the 4.096-Mcps channel. External baluns are used at the RF and LO inputs. The bits were captured from the ADCs with a logic analyzer and transferred to the frequency domain with an FFT as depicted in Figure 5.25.

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The differential matching is defined as described in the previous chapter. The differential S11 is compared to the simulated value together with the measured S11 and S22 in Figure 5.26(a). The matching is better than 10 dB in the 1.9 to 2.4-GHz range. The response of the RF chip is shown in Figure 5.26(b), and the shift from the targeted 2 GHz maximum gain rises the noise figure of the receiver by about 1 dB. The measured IIP3, IIP2, and 1 dB compression are 9 dBm, +43 dBm, and -25 dBm, respectively at 5-dBm LO power. The LO-to-RF isolation is better than 66 dB at all frequencies, and less than 1 and 0.6-dB I/Q phase and amplitude imbalances meet the requirements of the DCR.

The baseband frequency responses at several different channel gain settings and bandwidths are shown in Figure 5.27(a). At the 27-dB gain setting, the 4- and 8-MHz channel responses for higher chip rates are also given. The frequencies below 10 kHz could not be measured at the highest gain due to the limited dynamic range of the measurement equipment. The largest absolute gain and gain step errors are less than 3 dB and 0.4 dB, respectively. The baseband IIP3 and IIP2 of +14 dBm and +60 dBm would dominate the receiver performance without the pole at the output of the mixer. The 6-MHz pole damps 10- and 20-MHz interferers, and hence improves the overall linearity. The measured I/Q phase imbalance indicates better than 1 % accuracy in the time-constants in all cases. The gain error is less than 0.2 dB. The input referred noise at all gain values is compared to the simulation in Figure 5.27(b). The steep slope above the 40-dB gain is the effect of the preamplifier, which brings the noise down for weak signals. The ADCs can operate up to 50 MS/s, and the differential input range is 1.6 Vpp. The measured SNDR and SFDR are 35.7 and 45.5 dBc in the 6-bit mode. DNL and INL are 0.42 and 0.36 LSB, respectively.

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The DCR channel response is shown for a 2-GHz RF signal in Figure 5.28(a). The receiver voltage gain is 94 dB and the DSB noise figure 5.1 dB. With the maximum gain of 96.5 dB at 1.7 GHz, the noise figure is decreased to 3.9 dB. In the two-tone test in Figure 5.28(b), the third- and second-order intercept points 9.5 dBm and +38 dBm indicate high linearity and excellent immunity against envelope distortion. The measured blocking performance without the band select filter is shown in Figure 5.29 at the maximum gain. The 107-dBm test signal is compressed by 1 dB due to a blocker. Below 10 MHz, the channel filter dominates the behavior while the RF compression limits the maximal level to 25 dBm at large offsets from the LO. At 20-Hz offset the input compression is 47 dBm, which is much above the possible LO leakage. Hence, the DCR is not sensitive to a 5-dBm LO signal with over 66-dB LO-to-RF isolation. The measured DCR performance is summarized in Table 5.5. From the 128 mA supply current, the LNA and two mixers take 17 %, channel filters 26 % and two ADCs 36 %. The rest is needed for buffering between stages. As described earlier the filter current is scaled up at higher bandwidths. As given in chapter 2, the sensitivity can be calculated for the receiver from the thermal noise floor at the RF band, receiver noise figure, processing gain at the desired bit rate and the minimum required SNR for a certain BER. For example, the BER requires a 6.7 dB SNR when QPSK signals are detected. With a 128-kb/s data rate and 5.1-dB NF of the receiver, -114 dBm sensitivity is achieved for the 4.096-Mcps transmission. The sensitivity changes as a function of data rate and BER requirement as given already in chapter 2. The high transmission rate and high quality requirements in the data transfer are possible only with much higher signal levels than for speech at the input of the receiver.

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221

5.3.4

Summary of the WCDMA Chip Set

The direct conversion architecture is suitable for wide-band communications even in spectrally efficient modulations like QPSK, because the dc offset cancellation is easier than in narrowband systems, and continuous transmission avoids some transient problems of TDMA.

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Although the spread-spectrum systems are relatively insensitive to narrow-band interferers, a highly linear, selective and sensitive analog processing unit is required due to many technological limitations, and it efficiently reduces the number of bits of the A/D converter, simplifies digital processing and reduces DSP power consumption. The receiver performance is optimized embedding the required gain inside the channel selection filter and merging the digital gain control along the filter chain. The high linearity and tolerance against envelope distortion is achieved with modified Gilbert-cell mixers having NMOS transistors as input stages, careful layout design, and optimization of the baseband processing. The BiCMOS process with high-quality passive components allows effective methods to combine different transistor types, and low losses for high-performance applications. The direct conversion receiver described in this section reflects the requirements of the third generation wireless communications and shows a high-performance integrated solution with a state-of-theart technology for such a system.

5.4

Single-Chip Direct Conversion Receiver for WCDMA

This section introduces the implementation of a single-chip direct conversion receiver based on the circuit design in the previous section. The main emphasis is to study the presence of digital circuits on the same chip with a sensitive RF front-end and to prove the performance with a careful characterization. The single-chip direct conversion receiver is published in [31].

5.4.1

Circuit Design

The circuit design is based on the chip set where the RF, analog baseband and ADC blocks were on separate dies [19]. The different blocks of the receiver are described already in section 5.3. Only minor modifications have been done for the RF and baseband blocks, but A/D converters are redesigned for the new process using the same architecture as earlier. The singlechip version, in Figure 5.30, consists of a common-source LNA, two Gilbert-cell mixers with MOS input stages, quadrature LO generation from an external source using a polyphase filter and buffers, active RC-filters with a digitally adjustable gain and 6-bit pipeline ADCs. The bandwidth of the 5th-order Butterworth lowpass filter is tunable to 2, 4 or 8 MHz bandwidths and the ADC operates up to 65 MS/s. The differential receiver achieves 95-dB gain with a 25-GHz BiCMOS technology. External components include RF input matching with bond wires, four servo feedback capacitors and decoupling structures. The RF circuitry is placed opposite to the ADCs on the chip in Figure 5.31. The RF input and LO pads are grounded on the both sides, and the digital blocks of the baseband and ADCs are isolated from the with an layer connected to The digital output pad drivers are outside the protection well.

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5.4.2

Experimental Results

The chip is bonded directly on the PCB, and the bits from the ADC are captured with a logic analyzer. The signals are analyzed with FFT without despreading. Noise figure is measured over the entire WCDMA band at the LO frequencies, which are multiples of the 16.384 MHz ADC clock, and at a 1 MHz offset from the clock harmonics. The first measurement gives the noise figure without a spurious tone, because the servo loop removes the offset and spurs below 2 kHz, and the second test gives a reference with a spur at the passband. The noise figure without the clock distortion is plotted in the middle of Figure 5.32(a). The two curves are measured separately from the I- and Q-channels. The same custom is followed throughout the measurements of the single-chip receiver. The variations between adjacent testing points indicate the accuracy of the FFT method without averaging. The upper curves in the figure

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present the levels of the downconverted clock harmonics at the frequencies where n is the order of the clock harmonic, which alias at or closest to dc. The effect of those spurs on the noise figure is plotted also in Figure 5.32(a). Less than a 1-dB deterioration from the 5.5-dB noise figure was typically obtained, and in the worst case the degradation was below 2 dB. It is important to observe that the even and odd harmonics of the clock signal behave differently. The situation was sensitive to the amplitude of an external clock signal, which indicates that the coupling to the RF input is most likely dominated by the unmatched clock interface rather than substrate leakage. The 1.975-1.990 MHz LO-range was measured with a tighter raster to define the effect of the baseband filter response on the noise figure in Figure 5.32(b). The notch in the spur amplitude is at the clock harmonic, which downconverts directly to dc.

In the blocking test, the gain compression and spurious tone were defined at the offsets of 15 and 115 MHz with LO frequencies at 2015 and 2115 MHz. The test tones were chosen rather arbitrarily. The spur at downconverts to about 1 MHz IF in each case and it was always the strongest spurious signal at the band of interest. However, there were other possible combinations of LO, clock and blocking signals, which can produce the same tone as well. Unfortunately, the slow measurement method did not allow more testing frequencies. The -1 dB compression of the -99 dBm desired RF input signal was measured with a -24 dBm blocking signal in all cases. If the desired signal is 3 dB above the noise floor in the blocking test, the unwanted spurious can be at the same level with noise. In this case, the spurious tones below are acceptable at the input of the ADC. The value was calculated in the previous chapter. The blocking power was swept at all test frequencies, and in the worst case the spurious tone reached the maximum acceptable level with a -29 dBm input as given in Figure 5.33. On the other hand, at some frequencies the effect of the spurious was negligible before compression. Hence, unwanted spurious tones desensitizing the receiver are a problem, which must be carefully considered. Here, only a slight deterioration in the blocking test was measured, but especially in the narrow-band systems a better isolation between clock signals and RF input is necessary.

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5.4.3

Summary of the Single-Chip Direct Conversion Receiver

The measured performance of the receiver is given in Table 5.6. The numbers are also compared to the earlier chip set. The different IIP2 values in the I- and Q-branches indicate the typical sensitivity to mismatches in double-balanced mixers. Other parameters are comparable to the earlier chip set. The direct conversion receiver with the on-chip A/D converters achieves an excellent performance although the noise figure and blocking behavior are slightly degraded compared to the chip set. Also, the gain compression with the maximum gain at the passband of the channel selection filter was measured. As given in Table 5.6, the limited input range of the 6-bit ADC dominates the compression behavior. The layout and floorplan issues are critical in the implementation, but they were considered already in the previous implementation. Only little changes were done on the layout in the single-chip version. Multiple supply and ground connections were used, and especially the separate analog and digital supply voltages of the ADCs were isolated from other structures. The testing of single-chip receivers is much more complicated than with other direct conversion structures. One important factor is the large number of potential unwanted spurious falling at the passband of the channel selection filters. On the other hand, the values measured using a realistic A/D converter of the system give the real performance without a need to any mathematical combination of different blocks afterwards.

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