1/31/2012

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James A. Mynderse ME588 Sequential Logic 1
SEQUENTI AL LOGI C
Sequential logic is a logic function that takes the current
configuration (state) of the circuit and the inputs, and map these into
a new configuration (state) and output
Output depends on the current and past inputs
History dependence is achieved with feedback
Synchronous System
State transition synchronized with a special reference signal, the clock
Asynchronous System
State transition time is not predictable
Next State
Combinational
Logic
Current State
(Memory
Device)
Output
Combinational
Logic
Feedback Signal
Inputs
Clock
Outputs

= , Inputs
y = g(, Inputs)
x(k + 1) = x k , u k
y = g(x k , u(k)) compaie with
James A. Mynderse ME588 Sequential Logic 2
MEMORY DEVI CES LATCHES & FLI P-FLOPS
Example: (Cross-coupled NOR gates S-R Latch)
The S-R latch can hold its current state. By asserting R (reset), the
state can be set to 0 and by asserting S (set) the state is set to 1
R S S-R
Latch
00 01 11 10
0
Q
1
State Diagram:
K-Map:
R
S
Q
Q
R S Q Q
0 0
0 1
1 0
1 1
R S Q Q*
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Truth Table:
Q Q
1 0
0 1
not allowed
S0 S1
0 1
S=1,
R=0
S=0,
R=1
S=0
R=0
S=0
R=1
S=0
R=0
S=1
R=0
0
1
1
1
0
0
X
X
next state
1
0 1 X
X
0
0
1

= S + R

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James A. Mynderse ME588 Sequential Logic 3
LATCHES AND FLI P-FLOPS
Latches
Output changes when the input changes (after appropriate
propagation delay.)
Flip-Flops:
Output changes only with respect to clock transitions.
Edge-triggered: positive or negative
Input is sampled on either the L-to-H or H-to-L transition of the
clock transition. Input is valid if it is stable within the rise and hold
time around the clock transition edge. Output changes at a
propagation delay from after the clock transition
Master/Slave Flip-Flops
Type When inputs are sampled When outputs are valid
Unclocked Latch Always Propagation delay from input change
Level Sensitive Latch Clock High Propagation delay from input change
Positive Edge-Triggered FF Clock L-to-H Transition Propagation delay from rising edge of clock
Negative Edge-Triggered FF Clock H-to-L Transition Propagation delay from falling edge of clock
Master-Slave Flip-Flop Clock H-to-L Transition Propagation delay from falling edge of clock
James A. Mynderse ME588 Sequential Logic 4
LEVEL TRI GGERI NG S-R FLI P-FLOP
Using an enabling input (clock) signal CL to determine when the
inputs S and R are sampled
The flip-flop behaves like an S-R latch when CL is asserted, i.e.
when CL = 1. The flip-flop retains its previous state when CL = 0
The change of the flip-flop states is triggered by the level of the CL
signal. This is sometime referred to as level triggering
S
R
CL
Q
/Q
R S CL Q*
0 0 1 Previous Q
0 1 1 1
1 0 1 0
1 1 1 Not Allowed
X X 0 Previous Q

= CI S + R

+ CI
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James A. Mynderse ME588 Sequential Logic 5
J-K FLI P FLOPS
Output sets to 1 when J = 1 and resets (Q = 0) when K = 1.
Output toggles when both inputs J = K = 1.
0 0
0
1
1
1
0 1
J K J-K
Latch 00 01 11 10
0
Q
1
J
K
Q
/Q
J K Q Q*
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Q
0
1
toggle Q* = Q J + Q K
James A. Mynderse ME588 Sequential Logic 6
MASTER/SLAVE J-K FLI P-FLOP
Uses two stages
First stage takes the the new set and reset input at the rising edge
of the clock signal and generates the internal output state P
The second stage accept P and /P as input on the falling edge of
the clock signal and changes the output at the falling edge of the
clock
1s/0s Catching
Any glitches at the inputs to the flip-flop can cause unintended state
changes
CLK
J
K
Q
Q
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James A. Mynderse ME588 Sequential Logic 7
D FLI P FLOPS
Edge-Triggered Flip-Flop
Input and states are modified after a valid H-to-L or L-to-H transition
of the clock signal has been detected
Output changes at the arrival of the appropriate clock transition
At appropriate clock transition, the input is passed to the output
The output is held stable for at least one clock cycle
CLK
D
Q
Q
D CLK Q Q*
0
1

1
X
X 0
1
Q Q
Q Q

=
James A. Mynderse ME588 Sequential Logic 8
T (TOGGLE) FLI P-FLOP
The output (stored state) is complemented when the input is
asserted
Not found in standard part list, can be easily constructed using
other types of flip-flops
Example:
Using an D flip-flop to construct a T flip-flop
T
Q
Q
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James A. Mynderse ME588 Sequential Logic 9
TTL LATCHES AND FLI P-FLOPS
Schematic Symbols:
TTL Components:
Quad S-R
Latch
Dual J-K
Flip-Flop
with CLR
Dual D
Flip-Flop
with PRE
CLR
Hex D
Flip-Flop
CLR
R
S
Q
Q
S-R Latch
J
K
Q
Q
J-K Latch
J
K
Q
Q
Edge-
Triggered
J-K Flip-Flop
Edge-
Triggered
D Flip-Flop
D Q
Q
James A. Mynderse ME588 Sequential Logic 10
FLI P-FLOPS
S-R Latches
Usually used as components in implementing master/slave or
edge-triggered flip-flops
It can also be used for debouncing switches
J-K Flip-Flops
Often results in the fewest gates implementation of next-state
combinational logic
Requires two inputs per device complicated wiring
D Flip-Flops
Requires only one input attractive if wiring is an issue, as with
most VLSI technologies
T Flip-Flops
Good building blocks for counters
Can be easily formed using J-K or D flip-flops
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James A. Mynderse ME588 Sequential Logic 11
CONVERSI ON AMONG DI FFERENT FLI P-FLOPS
Any flip-flops can be implemented as combinational logic for the
next state functions in conjunction with a different kind of flip-flop
General Conversion use excitation table as truth table to build
interface combinational logic:
J
K
Q
Q
D
CLK
D flip-flop
implemented by J-K
flip-flop
D Q
Q
K
J
J-K flip-flop implemented by D flip-flop
Q Q* R S J K T D
0 0 X 0
0 1 0 1
1 0 1 0
1 1 0 X
X 0
0 1
1 0
X 0
1
0
0
1
1
0
0
1
S-R J-K T D
James A. Mynderse ME588 Sequential Logic 12
SYNCHRONOUS STATE MACHI NES
All logic is synchronized with the same clock signal
Provides similar noise margin in the temporal domain that binary
quantization provides in the signal domain
Memory devices are constrained to switch only in synchronous
with the clock
Timing constraints are local to each memory device
All input circuits must be stable before memory devices change
Asynchronous inputs should be passed through synchronizers
(usually composed of a D flip-flop with clock.)
Q
Q
SET
CLR
D
ASYNC_IN
CLK
SYNC_IN
Synchronous
Logic
Synchronizer
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James A. Mynderse ME588 Sequential Logic 13
FI NI TE STATE MACHI NE STRUCTURE
Mealy Machine
A sequential logic such that the output depends on both the current
inputs and the current states.
Moore Machine
A sequential logic such that the output depends only on the current
states.
Input
Output
Logic
G( . )
State
Memory
Next State
Logic
F( . )
Excitation
Current State
Output
Input
Output
Logic
G( . )
State
Memory
Next State
Logic
F( . )
Excitation Current State
Output
Next State = F Cuiient State, Cuiient Input
0utput = 0(Cuiient State, Cuiient Input)
Next State = F Cuiient State, Cuiient Input
0utput = 0(Cuiient State)
James A. Mynderse ME588 Sequential Logic 14
COUNTERS
Sequential logic circuit that proceeds through a well-defined
sequence of states
Up/Down Counters
Counts up/down a defined sequence in response to a count pulse,
usually labeled as CLK
Once the largest/smallest value has been reached, the sequence
starts with the smallest/largest value (sometimes a carry-over
signal is asserted.)
CLK
LOAD
ENP
ENT
QA
QB
QC
QD
RCO
0
0
0
0
1
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
1
1
1
0
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James A. Mynderse ME588 Sequential Logic 15
SYNCHRONOUS STATE MACHI NE
Example 2-Bit Up Counter
A counter will count to the next value if the count signal is asserted
and will stay at the current count if the count value is not asserted.
State Transition Diagram:
Circle (Oval) represent states
Top text is state name
Bottom text is the output associated with the state
Arrows are transitions
Numbers above the arrow gives the input values causing the
transition
S0 S1
S3 S2
00 01
10 11
Input: CNT
Output: 2 bit counts
(QA,QB)
CNT=1
CNT=1
CNT=1
CNT=1
CNT=0
CNT=0
CNT=0
CNT=0
_
A

=
A
(CNI, A, B)
B

=
B
(CNI, A, B)
James A. Mynderse ME588 Sequential Logic 16
SYNCHRONOUS STATE MACHI NE
Example 2-Bit Up Counter
State Transition Table:
A truth table that include the inputs, current states, next states, and
the output
CNT QA QB QA* QB* QA QB
0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 1
0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 1

S
0
S
1
S
3
S
2
00 01
10 11
CNT=1
CNT=1
CNT=1
CNT=1
CNT=0
CNT=0
CNT=0
CNT=0
0
1
0
1
0
1
0
1
0
0
1 1
0 1
0 1
1 1
0 1
0 0
0 1
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James A. Mynderse ME588 Sequential Logic 17
SYNCHRONOUS STATE MACHI NE
Example 2-Bit Up Counter
Memory Element:
Select flip-flop to implement the state machines memory storage
element.
D flip-flop is the easiest to implement.
Next-State Logic:
0 1 0 1
QA QB
QB*
00 01 11 10
0
CNT
1

0 1 1 0
0 1 0 1
0 1 0 1
QA QB
QA*
00 01 11 10
0
CNT
1

CNT QA QB QA* QB* QA QB
0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 1
0 0 0 0
0 1 0 1
1 0 1 0
1 1 1 1

0
1
0
1
0
1
0
1
0 0
1 1
0 1
0 1
1 1
0 1
0 0
0 1
A

= A CNI
+A B
+A B CNI
B

= B CNI
+CNI B

=
James A. Mynderse ME588 Sequential Logic 18
SYNCHRONOUS STATE MACHI NE
Example 2-Bit Up Counter
Implementation Generate wiring schematics
Simulate logic circuit
Q: What if an edge-triggered JK flip-flop is used instead of D flip-flop?
D
Q
Q
QA
D Q
Q
QB
CNI
CLK
A B
A B
QA
QB
QA*
QB*
A

= A CNI

+A B

+A B CNI
B

= B CNI

+CNI B
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James A. Mynderse ME588 Sequential Logic 19
STATE MACHI NE DESI GN PROCEDURE
Understand the problem
Finite state machine (FSM) is often described in plain language
specifications. It is important to interpret the description in a unambiguous
manner.
Obtain an abstract representation of the FSM
Identify inputs and outputs.
Represent the FSM description using state transition diagram.
James A. Mynderse ME588 Sequential Logic 20
STATE MACHI NE DESI GN PROCEDURE
Perform state minimization
Certain path through the state machine can be eliminated because their
input/output behavior is duplicated by other functional equivalent paths.
Perform state assignment
Outputs are often generated from the bits stored in the state flip-flops.
A good choice of how to encode the states often leads to a simpler
implementation.
Select flip-flop for implementation and generate next-state logic
D flip-flop tends to simplify the implementation process.
Use Boolean algebra and K-map to generate the next-state and output
logic functions.
Simulate and implement the state machine
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James A. Mynderse ME588 Sequential Logic 21
FI NI TE STATE MACHI NE DESI GN
Example 2-Button Combination Door Lock
The correct combination is a pre-defined sequence of push and
release operations:
Push and release button B2, then push and release button B1 to
unlock the door.
Abstract representation of the system:
Inputs: B1 and B2 (asynchronous inputs)
Output: L ( L = 0 is lock, L = 1 is unlock )
State diagram:
B1
B2
Lock
S1
0
S2
0
S3
0
01 00 10 00
01 00
10
S0
0
idle
S4
1
unlock
James A. Mynderse ME588 Sequential Logic 22
FI NI TE STATE MACHI NE DESI GN
Example 2-Button Combination Door Lock
Perform state minimization
State assignment:
At least (log
2
N ) number of bits, where N is the number of states.
For the current example:
N = 5 need log
2
5 = 2.32 3 bits
Select flip-flop for implementation:
D flip-flop often results in simpler wiring.
States Q1 Q2 Q3
S0 0 0 0
S1 0 0 1
S2 0 1 1
S3 0 1 0
S4 1 1 0
1

= = F
1
B1, B2, 1, 2, S
2

= = F
2
B1, B2, 1, 2, S
I = 0(1, 2, S)
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James A. Mynderse ME588 Sequential Logic 23
FI NI TE STATE MACHI NE DESI GN
Example 2-Button Combination Door Lock
Generate next-state and the output truth table:
Inputs: B1 B2 Next
State
00 01 11 10
S0
S1
S2
S3
C
u
r
r
e
n
t

S
t
a
t
e
S4
S3
S2
S0
B1 B2 Q1 Q2 Q3 Q1* Q2* Q3* L
0 0 0 0 0
0 1 0 0 0
1 0 0 0 0
1 1 0 0 0
0 0 0 0 1
0 1 0 0 1
1 0 0 0 1
1 1 0 0 1
0 0 0 1 1
0 1 0 1 1
1 0 0 1 1
1 1 0 1 1
0 0 0 1 0
0 1 0 1 0
1 0 0 1 0
1 1 0 1 0
0 0 1 1 0
0 1 1 1 0
1 0 1 1 0
1 1 1 1 0
S1
0
S2
0
S3
0
01 00 10 00
01 00 10
S0
0
idle
S4
1
unlock
S4
S1 S0 S0 S0
S1 S0 S0 S2
S2 S3 S0 S0
S4 S3 S0 S0
S0 S0 S0
0 0 0
0 0 1
0 0 0
0 0 0
0 1 1
0 1 0
0 0 0
0 0 0
1 1 0
0 1 0
0 0 0
0 0 0
James A. Mynderse ME588 Sequential Logic 24
FI NI TE STATE MACHI NE DESI GN
Example 2-Button Combination Door Lock
Generate next-state logic and the output logic:
Q2 Q3 Q1*
(Q1 = 0) 00 01 11 10
00
01
11
B1 B2
10
Q2 Q3 Q1*
(Q1 = 1) 00 01 11 10
00
01
11
B1 B2
10
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James A. Mynderse ME588 Sequential Logic 25
FI NI TE STATE MACHI NE DESI GN
Example 2-Button Combination Door Lock
Generate next-state logic and the output logic:
Q1 Q3 Q2*
(Q2 = 0) 00 01 11 10
00
01
11
B1 B2
10
Q1 Q3 Q2*
(Q2 = 1) 00 01 11 10
00
01
11
B1 B2
10
James A. Mynderse ME588 Sequential Logic 26
FI NI TE STATE MACHI NE DESI GN
Example 2-Button Combination Door Lock
Generate next-state logic and the output logic:
Q1 Q2 Q3*
(Q3 = 0) 00 01 11 10
00 0 0 0 X
01 1 0 0 X
11 0 0 0 X
B1 B2
10 0 0 0 X
Q1 Q2 Q3*
(Q3 = 1)
00 01 11 10
00 1 1 X X
01 1 0 X X
11 0 0 X X
B1 B2
10 0 0 X X

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James A. Mynderse ME588 Sequential Logic 27
FI NI TE STATE MACHI NE DESI GN
Example 2-Button Combination Door Lock
Summary:
State transition (Next State) Logic (for D flip-flop)
Output Logic
James A. Mynderse ME588 Sequential Logic 28
FI NI TE STATE MACHI NE DESI GN
Example 2-Button Combination Door Lock
Schematics and Simulation
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James A. Mynderse ME588 Sequential Logic 29
FI NI TE STATE MACHI NE DESI GN
Example 2-Button Combination Door Lock
Schematics and Simulation
Q: What if a random sequence of input is applied, will the lock
circuit still work?
CLK
B1
B2
B1_SYNC
B2_SYNC
Q1
Q2
Q3
L
James A. Mynderse ME588 Sequential Logic 30
STATE TRANSI TI ON FOR T FLI P-FLOP
When using a T flip-flop, the state transition (next state) truth table
needs to be modified to show the input to the T flip-flops:
INPUT = 1 if the next state is different from the current state.
INPUT = 0 if the next state is the same as the current state.
B1 B2 Q1 Q1* T1 Q2 Q2* T2 Q3 Q3* T3 L
0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 1 0
1 0 0 0 0 0 0 0 0
1 1 0 0 0 0 0 0 0
0 0 0 0 0 1 1 1 0
0 1 0 0 0 0 1 1 0
1 0 0 0 0 0 1 1 0
1 1 0 0 0 0 1 1 0
0 0 0 0 1 1 1 1 0
0 1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 0 0
1 1 0 0 1 1 1 1 0
0 0 0 1 1 1 0 0 0
0 1 0 0 1 1 0 0 0

0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
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James A. Mynderse ME588 Sequential Logic 31
AUTONOMOUS OBJECT SEEKI NG
You are asked to design a controller that control the steering and
motion of a robot.
The inputs to the controller are three sensors that are mounted to
the robot:
LS is mounted to the left of the robot and will be active if it senses
an object to the left of the robot.
RS is mounted to the right of the robot and will be active if it senses
an object to the left of the robot.
CLOSE is mounted in the front of the robot and it will be active is
the an object is with in 2 inches of the robot.
The outputs of the controller are:
FORWARD should be activated when the robot is to move forward
and deactivated when the robot is to stop.
LEFT should be activate to turn the robot to the left.
RIGHT should be activated to turn the robot to the right.
James A. Mynderse ME588 Sequential Logic 32
AUTONOMOUS OBJECT SEEKI NG
The operation of the robot is as follows:
When LS is active and RS is not, then the robot should turn left.
When RS is active and LS is not, then the robot should turn right.
When both LS and RS are active, then the robot should go straight.
When CLOSE is active, the robot should stop.
The robot should start from stop.
When non of the LS, RS, and CLOSE is active, then the robot
should go forward and turn toward right to circle around.
Some of the operation constraints are:
LEFT and RIGHT cannot be activated unless FORWARD is also
activated.
To stop the robot, FORWARD, LEFT, and RIGHT should be
deactivated.
To move the robot in the current forward direction, both LEFT and
Right need to be deactivated and FORWARD needs to be
activated.
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James A. Mynderse ME588 Sequential Logic 33
AUTONOMOUS OBJECT SEEKI NG
Identify all the input and output signals of the state machine and
state the physical meaning for their binary representations.
Inputs
LS = 0 LS deactivated (off) (nothing is sensed towards the left)
LS = 1 LS activated (on) (something is sensed towards the left)
RS = 0 RS deactivated (off) (nothing is sensed towards the right)
RS = 1 RS activated (on) (something is sensed towards the right)
CL = 0 CL deactivated (off) (nothing is in front)
CL = 1 RS activated (on) (something is in front)
Outputs
L = 0 L is low
L = 1 L is activated, vehicle turns left
R = 0 R is low
R = 1 R is activated, vehicle turns right
F = 0 F is low, vehicle stops
F = 1 F is activated, vehicle moves forward in current direction
James A. Mynderse ME588 Sequential Logic 34
1 0 1
0 0 1
0 1 1
AUTONOMOUS OBJECT SEEKI NG
Sketch the state transition diagram for the FSM.
S1 (LT) S2 (RT)
S0 (STOP)
0 0 0
S3 (FOR)
Sx (xxx)
L R F
Inputs:
LS RS CL
100
000
110
000
010
100
010
xx1
110 xx1
110
xx1
100
010
xx1
000
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James A. Mynderse ME588 Sequential Logic 35
I MPLEMENT FSM ON ARDUI NO
#define S0 0
#define S1 1
#define pin_out_S0 3
#define pin_out_S1 4
//create state variable and initialize it to S0
int state = S0;
void setup(){
pinMode(pin_out_S0, OUTPUT);
pinMode(pin_out_S1, OUTPUT);
digitalWrite(pin_out_S0,LOW);
digitalWrite(pin_out_S1,LOW);
}
void loop(){
switch(state){
case S0:
digitalWrite(pin_out_S0,HIGH);
if (something)
state = S1;
break;
case S1:
digitalWrite(pin_out_S1,HIGH);
if (something)
state = S0;
break;
}
}
S0
out_S0
S1
out_S1
James A. Mynderse ME588 Sequential Logic 36
SI MPLE POSI TI ON CONTROL
You are asked to design a controller (finite state machine) to control the motion of
a robot arm. The machine has two inputs (P, N) and three outputs (Forward,
Reverse, Slow).
The inputs (P, N) are described as follows:
When the robot position is less than the desired position; P=1, N=0.
When the robot position is larger than the desired position: P=0, N=1.
When the robot position is identical to the desired position: P=0,N=0.
When the robot has moved 7/8 the way to the desired position: P=1,N=1.
The outputs are:
FORWARD (F): The robot will move forward when this output is asserted.
REVERSE (R): The robot will move backward when this output is asserted.
SLOW (S): Brake will be applied to slow down the robot.
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James A. Mynderse ME588 Sequential Logic 37
SI MPLE POSI TI ON CONTROL
The operation of the machine is:
The system starts at a stop state where all outputs are zero.
If the current position of the robot is less than the desired position, FORWARD
should be asserted (FORWARD=1).
If the current position of the robot is larger than the desired position, REVERSE
should be asserted (REVERSE=1).
If the position is correct, stop the robot by setting all outputs to zero.
If the robot has moved 7/8 the way to the target position, the SLOW output should
be asserted (SLOW=1) to brake the motion of the arm.
James A. Mynderse ME588 Sequential Logic 38
SI MPLE POSI TI ON CONTROL
State Transition Table
Inputs: P, N
Output: F, R, S
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James A. Mynderse ME588 Sequential Logic 39
SI MPLE POSI TI ON CONTROL
State Transition Diagram
Inputs: P, N
Output: F, R, S
James A. Mynderse ME588 Sequential Logic 40
SI MPLE POSI TI ON CONTROL
State Assignment:
Truth Table:
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James A. Mynderse ME588 Sequential Logic 41
SI MPLE POSI TI ON CONTROL
Next State Logic:
Q1 Q2 Q0*
(P = 1) 00 01 11 10
00
01
11
N Q0
10
Q1 Q2 Q0*
(P = 0) 00 01 11 10
00
01
11
N Q0
10
Q1 Q2 Q1*
(P = 1) 00 01 11 10
00
01
11
N Q0
10
Q1 Q2 Q1*
(P = 0) 00 01 11 10
00
01
11
N Q0
10
Q1 Q2 Q2*
(P = 0) 00 01 11 10
00
01
11
N Q0
10
Q1 Q2 Q2*
(P = 1) 00 01 11 10
00
01
11
N Q0
10
James A. Mynderse ME588 Sequential Logic 42
STATE REDUCTI ON
Identify and combines states that have equivalent behavior.
Equivalent States
Have the same output.
The corresponding next states are the same, or equivalent.
Implement FSM with fewest possible states
Least number of flip-flops
More opportunities for dont cares
Reduce number of gates needed for implementation
Algorithmic Approach:
Start with state transition table
Identify states with the same output
If such states transition to the same next state, they are equivalent
Combine the equivalent states into a single new renamed state
Repeat until no new states are combined
1/31/2012
22
James A. Mynderse ME588 Sequential Logic 43
STATE REDUCTI ON
Row Matching Method
Example:
Single input X, output Z
Taking inputs grouped four at a time, output 1 if last four inputs were
the string 1010 or 0110.
X
Z
=
=
0010 0110 1100 1010 0011
0000 0001 0000 0001 0000
L
L
Reset
0/0
1/0
0/0 1/0
0/0 1/0
0/0 1/0 0/0 1/0 0/0 1/0 0/0 1/0
0/0 1/0
0/0 0/0
1/0 1/0
0/0
1/0
1/0
0/1
0/0
1/0
1/0
0/0
1/0 0/1
S0
S2
S1
S5 S3 S6 S4
S7 S8 S9 S10 S11 S12 S13
S14
0110 1010
James A. Mynderse ME588 Sequential Logic 44
STATE REDUCTI ON
Initial state transition table
Present State
S
0
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S
10
S
1 1
S
12
S
13
S
14
Input Sequence
Reset
0
1
00
01
10
1 1
000
001
010
01 1
100
101
1 10
1 1 1
X =1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X =0
S
1
S
3
S
5
S
7
S
9
S
1 1
S
13
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
X =1
S
2
S
4
S
6
S
8
S
10
S
12
S
14
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
0
X =0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
Next State Output
S
10
S
10
1/31/2012
23
James A. Mynderse ME588 Sequential Logic 45
STATE REDUCTI ON
1st round reduced state transition table
Present State
S
0
S
1
S
2
S
3
S
4
S
5
S
6
S
7
S
8
S
9
S '
10
S
1 1
S
13
S
14
Input Sequence
Reset
0
1
00
01
10
1 1
000
001
010
01 1 or 101
100
1 10
1 1 1
Next State
X =0 X =1
S
1
S
3
S
5
S
7
S
9
S
1 1
S
13
S
0
S
0
S
0
S
0
S
0
S
0
S
0
S
2
S
4
S
6
S
8
S '
10
S'
10
S
14
S
0
S
0
S
0
S
0
S
0
S
0
S
0
X =0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
X =1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Output
S
7
S
7
James A. Mynderse ME588 Sequential Logic 46
STATE REDUCTI ON
2nd round reduced state transition table
Present State
S
0
S
1
S
2
S
3
S
4
S
5
S
6
S
7
'
S '
10
Input Sequence
Reset
0
1
00
01
10
1 1
not (01 1 or 101)
01 1 or 101
X =0
S
1
S
3
S
5
S
0
S
0
X =1
S
2
S
4
S
6
S
0
S
0
X =0
0
0
0
0
0
0
0
0
1
X =1
0
0
0
0
0
0
0
0
0
Next State Output
S
7
'
S
7
'
S
7
'
S
7
'
S
7
'
S '
10
S '
10
S
7
'
S
3
S
4
1/31/2012
24
James A. Mynderse ME588 Sequential Logic 47
STATE REDUCTI ON
3rd round reduced state transition table
Input Sequence
Reset
0
1
00 or 11
01 or 10
not (011 or 101)
011 or 101
Present State
S0
S1
S2
S3'
S4'
S7'
S10'
X=0
S1
S3'
S4'
S7'
S7'
S0
S0
X=1
S2
S4'
S3'
S7'
S10'
S0
S0
Next State Output
X=0
0
0
0
0
0
0
1
X=1
0
0
0
0
0
0
0
Reset
S1
S3'
S7'
S2
S4'
S10'
0,1/0
0,1/0
0/0
0/0
1/0
1/0
1/0
1/0
1/0 0/1
S0
0/0
0/0
0110
1010
James A. Mynderse ME588 Sequential Logic 48
STATE REDUCTI ON
Implication Table (Chart) Method
Construct implication table (chart), one square for each
combination of states taken two at a time.
Squares are labeled Si,Sj. If the outputs of Si and Sj are different,
the square gets X. Otherwise, write down implied state pairs for
all input combinations.
Advance through the chart from top-to-bottom and left to right. If
the square Si,Sj contains the next state pair Sm,Sn and that pair
labels a square already labeled X, then the square Si,Sj is also
labeled X.
Continue executing the previous step until no new squares are
marked with X.
For each remaining unmarked square Si,Sj, then the states Si and
Sj are equivalent.
1/31/2012
25
James A. Mynderse ME588 Sequential Logic 49
STATE REDUCTI ON
Implication Table (Chart) Method
Example:
Single input X, single output Z
Output a 1 whenever the serial sequence 010 or 110 has been
observed at the input.
State transition table
X
Z
=
=
001 110 010 101 001
000 001 001 000 000
L
L
Present State
S
0
S
1
S
2
S
3
S
4
S
5
S
6
Input Sequence
Reset
0
1
00
01
10
1 1
X =1
0
0
0
0
0
0
0
Next State Output
X =0
S
1
S
3
S
5
S
0
S
0
S
0
S
0
X =1
S
2
S
4
S
6
S
0
S
0
S
0
S
0
X =0
0
0
0
0
1
0
1
James A. Mynderse ME588 Sequential Logic 50
STATE REDUCTI ON
Implication Chart Method
Enumerate all possible combinations of states taken two at a time
Naive Data Structure:
Xij will be the same as Xji
Also, can eliminate the
diagonal
Implication Chart
Next states
under all
input
combinations
S0
S1
S2
S3
S4
S5
S6
S0 S1 S2 S3 S4 S5 S6
S1
S2
S3
S4
S5
S6
S0 S1 S2 S3 S4 S5
1/31/2012
26
James A. Mynderse ME588 Sequential Logic 51
STATE REDUCTI ON
Implication Chart
Entry Xij Row is state Si and column is state Sj
Si is equivalent to Sj if they have the same outputs and equivalent
next states.
Xij contains the next states of Si and Sj, which must be equivalent if
Si and Sj are equivalent.
If Si and Sj have different output, then Xij is crossed out.
Example:
S0 transitions to S1 when X = 0 and to S2 when X = 1;
S1 transitions to S3 when X = 0 and to S4 when X = 1;
Square X01 contains entries: S1 S3 (when X = 0)
S1 S3 (when X = 1)
S1 S3
S2 S4
S0
S1
James A. Mynderse ME588 Sequential Logic 52
STATE REDUCTI ON
Implication Chart Method
Starting Implication Chart
S2 and S4
have different
I/O behavior
This implies that
S1 and S0 cannot
be combined
S1

S2

S3

S4

S5

S6
S0 S1 S2 S3 S4 S5
S1-S3
S2-S4
S1-S5
S2-S6
S3-S5
S4-S6
S1-S0
S2-S0
S3-S0
S4-S0
S5-S0
S6-S0
S1-S0
S2-S0
S3-S0
S4-S0
S5-S0
S6-S0
S0-S0
S0-S0
S0-S0
S0-S0
1/31/2012
27
James A. Mynderse ME588 Sequential Logic 53
STATE REDUCTI ON
Implication Chart Method
Results of First Marking Pass
Second Pass Adds No New
Information
S3 and S5 are equivalent
S4 and S6 are equivalent
This implies that S1 and S2
are equivalent too!
Input Sequence
Reset
0 or 1
00 or 10
01 or 1 1
Present State
S
0
S
1
'
S
3
'
S
4
'
X =0
S
1
'
S
3
'
S
0
S
0
X =1
S
1
'
S
4
'
S
0
S
0
X =0
0
0
0
1
X =1
0
0
0
0
Next State Output
S0-S0
S0-S0
S3-S5
S4-S6
S0-S0
S0-S0
S1
S2
S3
S4
S5
S6
S0 S1 S2 S3 S4 S5