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EMT 251
Objectives
To discussed the fundamentals of CMOS fabrication steps. To examined the major steps of the process flow. To overview the cross section view of a circuit
Introduction
MOSFET
NMOS
PMOS
CMOS
MOSFET
Gate Drain Source
Metal Oxide Semiconductor Field Effect Transistor Source (Arsenic, Phosphorous, Boron) Drain (Arsenic, Phosphorous, Boron) Gate (Aluminum, Polysilicon)
NMOS
P-type substrate N-type dopant for Source & Drain Inversion layer is formed to conduct electricity
NMOS
P-type substrate N-type dopant for Source & Drain Inversion layer is formed to conduct electricity
PMOS
N-type substrate P-type dopant for Source & Drain Inversion layer is formed to conduct electricity
PMOS
N-type substrate P-type dopant for Source & Drain Inversion layer is formed to conduct electricity
CMOS
A combination of both NMOS & PMOS technology Most basic example: inverter
PROCESS FLOW
WELL FORMATION ISOLATION FORMATION TRANSISTOR MAKING
INTERCONNECTION
PASSIVATION
Grow epitaxy layer (made from SiO2) as mask layer for well formation
Photolithography (CED)
photoresist Si02 P-substrate
UV light
P-substrate
Masking and exposure under UV light(E) Opaque area Resist dissolved after developed (D) Transparent
mask area
etching
Removing the unwanted pattern by wet etching Resist clean Desired pattern formed
P-substrate
P-substrate
Phosphorus ion
Ion bombardment by ion implantation SiO2 as mask, uncovered area will exposed to dophant ion
Thick oxide
Increase SiO2 thickness by oxidation at high temperature Oxide will electrically isolates nmos and pmos devices
By photolithography and etching process, pmos and nmos areas are defined
Gate oxide
Grow very thin gate oxide at elevated temperature in very short time
gate
photoresist
Photo process to define the nmoss active (source and drain) area and VDD contact Ion implantation with Arsenic ion for n+ dophant. Photoresist and polisilicon gate act as mask
source
drain
VDD contact
Nmoss Source and drain with VDD contact formation Resist removal
photoresist
Photo process to define the GND contact and pmoss active area (source and drain) Ion implantation with boron ionto have p+ dophant Photoresist and gate act as mask
Pmos source
Pmoss source and drain formation with GND contact Resist removal
SiO2
Metal 1
Mask Layout
Mask Layout
Mask Layout
Mask Layout
Assignment
B
GLOSSARY
Photolithography (photo)
Process of transferring pattern on mask to photoresist layer on wafer surface (pre-pattern the chip)
Etching
Process of permanently removed the unwanted part of design on wafer surface to get the desired pattern
Diffusion
Process of introducing dophant layer by movement of dophant atoms from high concentration to low concentration area at high temperature
Ion implantation
Process of introducing dophant layer by bombardment of high energy dophant ion in high electric field chamber
Oxidation
Process of growing thick or thin SiO2 layer depend on oxide application
CMP
Process to physically grind flat to have a planar surface for better exposure at photo process.
THE END