IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 321

LC8n CI8CguCnlu! CiCul u8n iCVCi8b!C !CC

Prsshsnt. Yeleksr
Department of Electronics Telecommunications,
Yeshwantrao Chavan College of Engineering,
Nagpur, India
prashantyelekar@gmail.com
hv/ruc/- The reversible logic design in today's era is
attracting more interest due to its low power consumption.
Reversible logic h a s g r o w i n g importantance in low
power circuit design and high processing com puting. This
paper provides synthesizing reversible counter which is the new
approach in designing four bit reversible asynchronous
sequential circuit. This paper also proposed a reversible U fip
fop and Tfip-fop. The important reversible gates used for
reversible logic synthesis are Feynman gate, Fredkin gat e ,
TSG gate and sayem gate etc. This pap e r presents a basic
reversible gate to build more complicated circuits. The
transistorized implementation of reversible gate presented in this
paper are completely reversible in nature i.e. it can perform both
fonard and backward computation.
AcJw0rJv- 0w-]0wcr I5, 0w-]0wcr tMU5Jcvgn, rcvcrvhIc
I0gc, rcvcrvhIc c0un/crv.
I. INTRODUCTION
Energy loss is an important consideration in digital circuit
design, also known as circuit synthesis. Part of the problem of
energy dissipation is related to technological non- ideality of
switches and materials. Higher levels of integration and the
use of new fabrication processes have dramatically reduced
the heat loss over the last decades. Reversible logic has
received geat attention in te recent years due to their
ability to reduce the pwe dissipation which is the main
requirement in low power VLSI desig. It has wide
applications in low power CMOS and Optical information
processing, quantum computation and nanotechnology.
Irreversible hardware computation results in energy
dissipation due to information l oss. According to Landauer
research, the amount of energy d i s s i p a t e d for e v e r y
irrepressible bit Operation is at least KTln2 joules, where
K=1.3S06505* 10
23
m
2
kg
2
K
l
Uoule/Kelvin
-l
) is the
Boltzmann's constant and T is the temperature at which
on is performed [1]. In 1973, Bennett showed that
KTln2 energy would not dissipate from a system as long
as the _% allows the reproduction \ f t h e i n p u t s
from \ b s e r v e d \ u t p u t s [ 2]. Energy dissipation can be
reduced or even eliminated if computation becomes
Information-lossless Reversible logic supports the process of
Prct. Sa|sts S.Chlwsnde
Department of Electronics Telecommunications,
Yeshwantrao Chavan College of Engineering,
Nagpur, India
Su jata _chiwande2S@yahoo.co.in
running the system both forward and backward. This
means that reversible computations can generate inputs
from outputs and can stop and go back to any point in the
computation history.
II. THE CONCEPT
Reversibility in computing implies that no
information about the computational states can ever be lost,
so we can recover any earlier stage by computing
backwards or lcomputing the results. This is termed as
logical reversibility. The benefts of logical reversibility can
be gained only afer employing pysic reversibility.
Physical reversibility is a process that dissipates no energy
to heat. Absolutely perfect physical reversibility is
practically unachievable. Computing systems give off heat
when voltage levels change from positive to negative: bits
from zero to one. Most of the energy needed to make that
change i s g i v e n o f f i n t h e f or m of heat . Rather t ha n
changing voltages to new levels, reversible circuit elements
will gadually move charge from one node to the next. This
way, one can only expect to lose a minute amount of
energy on each transition. Reversible computing sy
affects digital logic desigs. Reversible logic elements are
needed to recover the state of inpus from the outputs. It
will impact instruction sets and high-level programming
languages as well. Eventually, these will also hve to be
reversible to provide optimal efciency.
III. NEED OF REVERSfLE COMPUTING
Reversible computing provide Reliable and low
power design, high performance circuits synchronous with
speed and processing power. Reversible circuits that
conserve information, by uncomputing bits instead of
throwing them away, will soon offer the only physically
possible way to keep improving performance. It again
Improve computational effciency this can be done by
building circuits which reduce energy from state will save
energy. Reversible computing will also lead to improvement
in energy efciency. It Increase portability of device to
reduce element size to atomic size. It has incurred more
hardware cost, but power cost and performance are dominant
ISBN: 978-S1-909042-2-3 2012 IEEE
IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 322
than hardware cost. Hence need of reversible computing
cannot be ignored in computing era,
Some factor regarding reversible logic are given below
The number of garbage outputs (GO): This rfe to
the number of unused outputs p h a
reversible logic circuit. One cannot avoid the
garbage outputs as these are very essential to
achieve reversibility.

Quantum cost (QC): This refers to the cost of the

circuit in terms of the cost of a pimitive gate. It
is calculated knowing the number of primitive
reversible logic gates (1 * 1 or 2*2) required to
realize the circuit. of reversible gates used in
circuit.

The number of constant inputs (CI): This refers to

the number of inputs that are to be maintained
constant at either 0 or 1 in order to synthesize
the given logical function
IV. REVERSIBLE LOGIC GATES
A reversible logic gate has equal number of input and
output terminals and there is one to one mapping between
them. again we can say, gate is reversible if we can determine
input vector from output vector and vice-versa.revrsible gate
should practically loose very little amount of energy. Fan-out
is not allowed in reversible circuits however fan-out can be
achieved using additional gate. In this paper we have discuss
basic reversible gate like Feynman gate, fredkin gate, TSG
gate and Sayem gate Which we have used in implementing
reversible sequential circuits.
A. FEYNMAN GATE
Feynman gate is a 2*2 one through reversible gate
as shown in fgure I. The input vector is I(A, B) and the
output vector is O(P, Q). The outputs are defned by P=A,
Q=A B. Quantum cost of a Feynman gate is I. Feynman
Gate (FG) can be used as a copying gate. Since a fan-out
is not allowed in reversible logic, this gate is useful for
duplication of the required outputs.
A
B
~CyIHH
gatC
Figure I. Feynman gate
|=T
[=7
I) TRANSiSTOR iMPLEMENTATiON
Figure 2 shows the transistor implementation of the
Feynman gate. The transistor implementation is flly
reversible, that is, the given circuit can also work for forward
as well as reverse operation.
Figure 2: Reversible Transistor Implementation of the Feynman gate
As shown |n das|gn |n |g.2, only four trans|stors ara
naadadtodas|gnthafullyravars|bla aynmangata.
B. FREDKN GATE
Figure 3 shows a 3*3 Fredkin gate. The input vector is
I (A, B, C) and the output vector is 0 (P, Q, R). The output is
defned by P=A, Q=A'B AC and R=A'C AB. Quantum
cost of a Fredkin gate is 5
"
D
LK|
6AH
| P
L "
j H=AC AB
Figure 3: Fredkin gate
I) TRANSISTOR iMPLEMENTATION
Figure 4 shows the transistor implementation of the
Fredkin Gate that need only four transistors. In the
implementation, the output P is directly taken from input A as
output P is same as input A. The proposed transistor
implementation is suitable both for forward as well as
backward computation, i.e., completely reversible in nature.
The forward and backward computations for Fredkin gate are
explained below.
u
c_
Figure 4. Transistor Implementation of Fredkin Gate
ISBN: 978-81-909042-2-3 2012 IEEE
IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 323
C TSG GATE
Fig 5 shows a 4*4 TSG gate. The input vector is I (A,
B, C, D) and the output vector is 0 (P, Q, R, S). The output is
defned by P = A, Q = A'C'EB', R = (A'C'EB')E D and S =
(A'C'EB').DE (ABEC) The proposed TSG gate is capable of
implementing all Boolean fnctions and can also work singly
as a reversible Full adder as shown in fgure 6

P
b
`aGG! ~ o-r'c'Qs'
C R (/'c'QeiD
D
= b ,ca).o(t-c ,
Figure 5: TSG gate
A

l!
LGTG
P=
Q=s
M = A 9L ^ S1O
>=( A @ D ) c,@o = Cc1
Figure 6: TSG Gate Working As Reversible Full Adder
TRANSISTOR IMPLEMENTATION
The transistorized implementation of TSG gate is as
shown in fgure
Figure 7. Transistor Implementation of TSG Gate
D. SAYEMGATE
Sayem gate (SG) is a 1 trough 4x4 reversible
gate. The input and output vector of this gate are, Iv = (A,
B, C, D) and Ov = (A, A'B E AC, A'B E ACE D, AB E
A'C E D). The block diagram of this gate is shown in Fig
8. The sayem gate can be used to build reversible T fip
fop along with Feynman gate.
A
A
ABJC
J
>0
^'1AC
C
0
AbdA'LJ
Figure 8: Sayem gate
I) TRANSISTOR IMPLEMENTATION
Transistorized implementation of sayem gate (SG) is
shown in fgure. The sayem gate is extension of Feynman
gate. The implementation of sayem gate requires four
transistors with two buffers and two Feynman (FG) gate as
shown in fgure. The buffer is introduced so as maintain
proper voltage level. The given implementation is completely
reversible i.e. it works for both forward and backward
computation.
r_
| L
L
c c
Figure 9. Transistor Implementation of Sayem Gate
1 LATCHES
Here we can use D-Latch or T-Latch depending upon
choice that can be used in implementing reversible sequential
circuit (counter)
I) D-LATCH
The D fip-fop is a circuit that needs only a single
input and clock pulses. The action of the D fip-fop is
straightforward. When the clock pulse transitions from low to
high, the value of D is transferred to Q. The characteristic
equation of D-Latch is Q+ =DE+E'Q. Realization can be done
using single SG gat by giving E, Q, D and 0 respectively in
1st, 2nd, 3rd and 4th input of SG. Fig lO(a) shows the design
ISBN: 978-81-909042-2-3 2012 IEEE
IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 324
of D-Latch with only Q output and Fig 10(b) shows the design
of reversible D-Latch with both the output present Q and next
Q+ .One FG is needed to copy and produce the complement of
Q from SG for the design of Fig lOeb)

CL
l -
_ -
g=
1
~
~
Fig IO(a): Proposed design of D-Latch with only output Q
I

SG
Fig I O(b): Proposed design of D-Latch with output Q and Q+
2) T-Flip Flop
As the name suggests, this fip-fop circuit used to
toggle the output when input is high (1) and retains the output
when input is low (0), thus it does two operation, it either
holds the last state or toggles the output. Essentially, it has a
logical symmetry with Controlled NOT kind operation.
Table I: Truth table of T flip-fop
The reversible realization of T Flip-fop has two SG gates
and one Feynman Gate is shown in fg 11[6].

f\1
^
"
Fig II: Reversible Positive Edge Triggered T Flip-fop

lP
V'
Figure 12: reversible T flip flop
1 FOUR BfT ASYNCHRONOUS UP/DOWN COUNTER
The implementation of reversible asynchronous Up/Down
Counter is shown in Fig. 13[6]. The Up/Down operation of
this reversible circuits is controlled by the control input
UP/DOWN. For UP operation, the control input should be 1
and for down operation, the control input should be O.
C:u
ne
.
num
'

s
:| .. ~~ ~ ~~ ~ ~~ ~~

Figure 1c. Four-bit Reversible Asynchronous Up/Down
Counter
V. SIMULATION ANALYSIS
Simulation is based on "TANNER TOOL V13".model fle
used is "0.35J"technology fle. Graph presented below are
input and output signal at respective input and output terminal
at each gate.
f) FEYNMN GATE
]..... . ..... .. .. .... .....
,_...._..... ......_.... .... . .. ..... ........-
r
.............
-
.......
l

.. ..... . .........._... . ....._.... ........_......_......_......_

..

......_....... - ........._......... ........

....... ........_....._......._....._

' L L
@ . 1 L 1 l 1
I 1 L
&
..
"
,. .

............
I
......... ... . ..
1
... ;,-
.

..
1
.........._............ ..........._......... ..........._..... ..... ...........
l
..........
l
. ,
r
..... ..._............ ... ........_............. ........._..... ......._...._.
| ' '

!
......._......... .. . . ._....... ......_....._

. _....._.. ..
'
...... ..._.. .... ._....._
.
_!_ _

B
..
. ... . ......p..........,..........."
.... ................m. _.. .--- . .....- ...... _ -. -.- _..... ._
\ '
1 1
.
-
-_ |
@ .._........_............_........._............ . . . ._.. ..._...._ .....,........_......_
, .. -.+=

~ ~
+
..... .._. .. ... _. _.._.. ,_.,. ._
.. ._....._..._..._. ....._.. .. _. ..._.... . . ._ .._
. .........._........._.................... ........_..........

.............. ...................._.

.
]
.

X
.
avgyower 1.196Ie-005
Figure 14: simulation of Feynman gate (forward direction)
ISBN: 978-81-909042-2-3 2012 IEEE
l
IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 325
^T
"
.

+
.
1
..

.
l
.

..

.
!
.

.
1
...........
|
..............._.......
1
........._.. ........ . ..............
1
.........
j
.......
1
, .................... ......._......._........._........ ......

.. ......... .._......
._.........._......... .........
T
......,
J
...........
T
......... ...........
!
..... ..

... .....

" ._........_..

.... ....

.......
f
....._...... .. ......._..,.._,.._......_.
. _..... .._........ ........
T
.......
r
.......
T
....... ....

....._.....

...._
.._....... ...._.......... .........._........._.......... .... ......_......._. ....... ._..... ._.
i

.
1

............._ .. ..... ._.... ._..... .... ......_ .. ........ ... .... ...... .. ...... ..
._ =

... .

.. . .. ._. .=....._..... .... . .... ..... .. .._..:~ ..

, ............
|
........._....... ..... ........._ ............. .. .. ...._.. ...._
a

.. . .._... ..... _ ..

. .._. .. _ ... .
|
.._..... ..._........_....._....... .......
1
....

....

...... ......

......._.
._..,. ....
+
....._...
'
.. ...... .,...._..,...
T
~,,....
T
. ....,._....._
._.... ......_..... _.... _.. .. ..................

...... ...... ...._... ....._.

` ! `1 ' ! T !
"
.
T`
.
J T
' . . . .. . . .= ..
1 i
''..,...,_...... ... _ .,.... ...`]*
............_........... ................ ................. .............. .......[-......1.
` "1
.
" '' | ! | `l '"+
@ .. .......... ...

. .............

. ... ...._ ........ .... ... ........ ......._.......

1
.
'
'_

| . l ` 1
B
W
avgyower 2.066Se-OOS
Figure IS: simulation of Feynman gate (backward direction)
2) FREDKN GATE
|-I1

1 V L D
I

t 5 !
Ins
|-I1|

V C 1.
In
avgyower 1.2270e-006
Figure 16: simulation of Fredkin gate (forward direction)

.... . .
.... `
` !
:

.....

! :
0+i1

`
avgyower -6.S332e-007
. ..-
...................
Figure 18: simulation of Fredkin gate (backward direction)
3) T FLIP-FLOP
I:
.
l

..
!:_
,.. ... .............,........ .. .......
., .......
,:.
*J
, ,
.....
1' ----1

.. ........... ....................... .. ........... .. ... ....................................
,; .................................. . ........... ...........................
. ................................., .... ......................v....
.?. ... ... ...

I
.

_

.... .... = .... ... = ..... .... .... ..

.... _
:.
..
. ..
:=....
...
....
,
-...
,....
..
-
.. ! ! ! ! !"
avgyower 2.9826e-004
Figure 17: simulation of T llip-lop
ISBN: 978-81-909042-2-3 2012 IEEE
IEEE-International Conference On Advances In Engineering, Science And Management (ICAESM -2012) March 30, 31, 2012 326
4) COUNTER OUTPUT
.... .... ..... ....
.. . ... .. .

f |
! 1LU LLLuJ
avgyower 1.9988e-003
Figure 18: simulation analysis of counter output
Likewise we will get simulation of other reversible logic
gates.
VI. APPLICA TlON
Reversible computing may have applications in computer
security and transaction processing, but the main long-term
beneft will be felt very well in those areas which require high
energy efciency, speed and performance .it include the area
like
1.
2.
.
4.
b.
O.
Low power CMOS.
Quantum computer.
Nanotechnology
Optical computing
Design of low power arithmetic and data path for digital
signal processing (DSP).
Field Programmable Gate Arrays (FPGAs) in CMOS
technology for extremely low power, high testability and
self-repair.
VII. CONCLUSION
This paper proposes designs of basic reversible sequential
elements such as latches, fip-fops and four bit reversible
asynchronous up/down counter. We have shown average
power dissipation in each gate in simulation part which
indicates negligible energy dissipation which in turn improves
performance of circuit. Basic reversible gate presented in this
paper can be used in regular circuits realizing Boolean
functions. The proposed asynchronous counter designs have
the applications in building reversible ALU, reversible
processor etc. 'n th|s papar, wa prasant a mathod of
asynchronous countar das|gn d|ractly from ravars|bla
gatas. This work forms an important move in building large
and complex reversible sequential circuits .
REFERENCES
[1] Landauer, R., "Irreversibility and heat generation in the computing
process", IBM 1. Research and Development, 5(3): pp. 183-191, 1961.
[2] Bennett, C.H., "Logical reversibility of Computation", IBM J.Research
and Development, 17: pp. 525-532, 1973.
[3] Thapliyal H, Ranganathan N.," Design of Reversible Latches Optimized
for Quantum Cost, Delay and Garbage Outputs" Centre for VLSI and
Embedded System Technologies International Institute of Information
Technology, Hyderabad, 500019, India
4j Mozammel H A Khan and Marek Perkowski" Synthesis of Reversible
Synchronous Counters" 2011 41st IEEE International Symposium on
Multiple-Valued Logic
[5] H. Thapliyal and A.P. Vinod, "Design of reversible sequential elements
with feasibility of transistor implementation," International Symposium on
Circuits and Systems (ISCAS 2007), 2007, pp. 625-628 .
[6) V.Rajmohan, V.Ranganathan,"Design of counter using reversible logic"
978-1-4244-8679-3/11/$26.00 2011 IEEE
[7] Siva Kumar Sastry, Hari Shyam Shroff ,Sk.Noor Mahammad, V.
Kamakoti" Efcient Building Blocks for Reversible Sequential Circuit
Design" 1-4244-0173-9106/$20.002006IEEE
[8] M.-L. Chuang and C.-Y. Wang, "Synthesis of reversible sequential
elements," ACM joural of Engineering Technologies in Computing Systems
(JETC), vol. 3, no. 4, 2008.
[9] S.K.S. Hari, S. Shroff, S.N. Mohammad, and V. Kamakoti, "Eficient
building blocks for reversible sequential circuit design," IEEE International
Midwest Symposium on Circuits and Systems (MWSCAS), 2006.
[10]Abu Sadat Md. Sayem, Masashi Veda "Optimization of reversible
sequential circuits" journal of computing, volume 2, issue 6, june 2010, issn
2151-9617
[11] Thapliyal H, M. B.Sshrinivas "Novel Reversible Multiplier Architecture
Using Reversible TSG Gate" Computer Systems and Applications, 2006.
IEEE Interational Conference on.
[12] Rangaraju H G, Venugopal V, Muralidhara K N, Raja K B "Low Power
Reversible Parallel Binary AdderlSubtractor"lnterational journal of VLSI
design &Communication Systems (VLSICS) YoU, No.3, September 2010
[13] h.r.bhagyalakshmi, m.k.venkatesha" an improved design of multiplier
using reversible logic gates" Interational Journal of Engineering Science and
Technology Vol. 2(8), 20 I 0, 3838-3845
[14] Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, and John P. Hayes"
Reversible Logic Circuit Synthesis" ICCAD 2002 Nov 1014, 2002, San Jose,
California, USA Copyright 2002 ACM XXXXXXXXX/XX/XX... $5.00.
ISBN: 978-81-909042-2-3 2012 IEEE