Altera Enabling High-Performance DSP Applications With Arria V or Cyclone V Variable-Precision DSP Blocks

Enabling High-Performance DSP Applications with Arria V or Cyclone V Variable-Precision DSP Blocks
WP-01159-1.0 White Paper
This document highlights the benefits of variable-precision digital signal processing (DSP) architecture in Alteras new Arria V and Cyclone V FPGAs. Altera's variableprecision DSP block allows designers to tailor the precision on a block-by-block basis, thereby saving resources and power while increasing performance.
Introduction
DSP designs use hundreds or thousands of multipliers as basic building blocks to implement filters, fast Fourier transforms (FFTs), and encoders that digitally process signals. Depending on the specific type of filter required, varying precision levels may be required within a design at each stage of FIR filters, FFTs, detection processing, adaptive algorithms, or other functions. In addition, DSP algorithms with varying precision levels often require precision higher than 18 bits. The following sections discuss the benefits of Alteras variable-precision DSP architecture available in Arria V and Cyclone V devices.
Key DSP Design Trends

The range of DSP precision requirements varies by application, as shown in Figure 1. Video applications use multipliers ranging from 9x9 to 18x18. Wireless and medical applications push precision requirements even further when implementing complex, multi-channel filters that must maintain data precision after each filter stage. Military, test, and high-performance computing also push the performance and precision requirements, sometimes requiring single- and double-precision floating-point calculations for implementing complex matrix operations and signal transforms.
Figure 1. Applications and Precision Range
9-Bit Precision 100 GMACS
Floating-Point Precision TeraFLOPS
Video Surveillance
Broadcast Systems
Wireless Basestations
Medical Imaging
Military Radar
High-Performance Computing
Applications Moving to Variable and Higher Precisions
101 Innovation Drive San Jose, CA 95134 www.altera.com May 2011
2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with Alteras standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
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Variable-Precision DSP at 28nm
Page 2
The DSP architecture of the 28-nm Arria V and Cyclone V FPGAs is optimized to support both high-performance and variable data precision that enables area and power efficient implementation of both fixed and floating-point operations.
High-Precision DSP Applications

Many cutting-edge applications require high-performance DSP designs that support higher than 18-bit precision, as shown in Figure 2. Precision in this context means the size of a multiplier, for example 9x9, 12x12, 18x18, 27x27, and other sizes. More specifically, precision refers to the width of each operand applied to a multiplier.
Figure 2. High-Performance Applications
HIGH-PERFORMANCE COMPUTING MILITARY
High-Precision Multiply Accumulate High-Precision Finite Impulse Response (FIR) Filters High-Precision Fast Fourier Transforms (FFTs) Floating-Point FFTs Floating-Point Matrix Operations
TEST AND MEASUREMENT WIRELESS
MEDICAL
Many traditional DSP functions such as FIR filters, FFTs, and custom signal processing datapaths have high-precision requirements. These functions are commonly implemented in military, medical, and wireless systems. When designs require precision higher than 18-bit, designers may implement floating-point signal processing to reach this precision level in high-end designs, such as military spacetime adaptive radars and MIMO processing on LTE channel cards. Alteras 28-nm silicon architecture introduces the industry's first variable-precision DSP architecture that allows designers to tailor the precision of each DSP block to perfectly suit the application.

The variable-precision DSP block in Arria V and Cyclone V FPGAs allow designers to select from 9x9 precision to implement a video processing design, all the way up to floating-point precision required for advanced radar designs. Designers can individually set each DSP block precision to efficiently accommodate bit growth and required precision increases within the DSP datapath. In addition, the Arria V and Cyclone V DSP block is backward-compatible with all modes supported by Alteras previous generation 65-nm and 40-nm device families. Figure 3 illustrates the precision ranges supported by a single Arria V or Cyclone V DSP block.
May 2011
Altera Corporation
Page 3
Figure 3. Architecture with Selectable Precision
Wireless
x25 18
27x2 7
Vid eo
ry lita Mi
36 6x
18x 18
54x54
Set the Precision Dial to Match Your Application
Variable-Precision DSP Blocks

Figure 4 maps the multiplier precision required by various FPGA markets to the supported multiplier precisions in Arria V DSP blocks. The Arria V DSP block natively supports nearly all of precision levels required by these applications. The following sections describe the full-precision, 18x18 with pre-adder mode that is effective in the wireless market.
Figure 4. Precision Requirements and Arria V Precisions
9x 9
Industrial Video
Broadcast Systems
Wireless Systems
Medical Imaging
Military Radar
HighPerformance Computing
Precision Requirements
9x9
12x12 16x16
18x18
18x18 18x25 18x36 27x27 18x18 18x25 18x36* 27x27 18x25
18x18 18x25 18x36 27x27 18x18 18x25 18x36* 27x27 18x25
27x27 54x54
Supported Precisions
9x9
12x12 16x16
18x18
27x27 36x36* 54x54* 18x25
Supported Precisions (Competitive FPGAs)
18x25
18x25
18x25
* Requires additional logic outside of the DSP block to implement
May 2011
Altera Corporation
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Variable-Precision Modes
The Arria V, Cyclone V, and Stratix V DSP block are the first to offer two native precision modes, as shown in Figure 5.
Figure 5. Arria V and Cyclone V DSP Modes
18 +/18
18x19 X
64 Bits 27
Output Multiplexer
27x27 X
64 Bits
Output Multiplexer
Output Register
Intermediate Multiplexer
Input Register
18 Bits
108 Bits
+ 18 Bits Coefficient Bank
+ -
74 Bits
Input Register
Coefficient Bank
Output Register
108 Bits
Coefficient Bank 27 bits
+ -
74 Bits
Feedback Register
Feedback Multiplexer
18
18x19
25
64 Bits
+/-
+/-
Feedback Register
18
25
64 Bits
18-Bit Precision Mode
High-Precision Mode
The available modes are 18-bit mode, and high-precision mode for 27x27 multiplications. Figure 6 shows the various multiplier precision modes available in the Arria V (and Cyclone V) DSP block. Designers can implement an 18x36 multiplier by using one DSP block plus additional logic outside the DSP block. Similarly, designers can implement a 36x36 multiplier by using two DSP blocks and additional logic outside the DSP block, or a 54x54 multiplier by using 4 DSP blocks and additional logic outside the DSP block.
Figure 6. Precisions Available in Arria V and Cyclone V FPGAs
Within 1 DSP Block
Quantity 3 2 2 2 1 1 1 Multiplier Mode 9x9 12x12 16x16 18x19 18x25 27x27 18x36* 1 1 1 1 1 1
Within 2 DSP Blocks

Quantity Multiplier Mode 18x18 complex multiply 36x36* complex multiply
4 Within 3 DSP Blocks

18x25* complex multiply 18x36* complex multiply 27x27 complex multiply 54x54* complex multiply
Variable-Precision Efficiency
While the key advantage of variable precision is the ability to take advantage of blockby-block implementation efficiencies, the Arria V variable-precision DSP block also provides the highest number of multipliers of different precisions compared to competing architectures, as shown in Figure 7.
May 2011
Altera Corporation
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Figure 7. Multiplier Precision Comparison
Multiplier Precision
9x9 (industrial video) 12x12 (broadcast) 16x16 (broadcast, digital cinema) 18x18 (wireless, medical, military) 18x25 (wireless, medical, military) 18x36 (medical, military) 27x27 (military, high-performance computing)
Arria V & Cyclone V Variable-Precision DSP Block

3 per block 2 per block 2 per block 2 per block 1 per block 1 per block* 1 per block
18x25 DSP48 Block

1 per block 1 per block 1 per block 1 per block 1 per block 0.5 per block 0.5 per block
2X to 3X Number of Multipliers per Variable-Precision DSP Block Means Power Reduction
DSP Multiplier Comparison

Variable-precision DSP blocks provide significant advantages when implementing multipliers of varying precision. Figure 8 compares an Arria V device of 363 KLEs and 1045 variable-precision DSP blocks, against a Kintex-7 device of 356 KLCs and 1440 DSP blocks. When compared with the Kintex-7 XC7K355T device, the Arria V 5AGXB3 device variable-precision DSP blocks provide a clear advantage when implementing multipliers of different precisions. Nearly across the board, variableprecision DSP blocks provide more multipliers per device.
Figure 8. Arria V FPGA Multiplier Count Comparison
Arria V FPGA 5AGXB3

3,135 2,090 2,090 2,090 1,045 1,045 1,045
Kintex-7 XC7K355T
1,440 1,440 1,440 1,440 1,440 720 720
More DSP Resources vs. the Competition
Although competing solutions may offer a few more multipliers in the 18x25 mode, this mode accounts for only a small portion of actual user configurations. Figure 9 provides a comparison of Cyclone V FPGA multipliers against competitive solutions. In general, the Cyclone V device offers more multipliers of different precisions than the Artix-7. The only exception is in the case of 18x25 precision.
May 2011
Altera Corporation
DSP Block Evolution
Page 6
Figure 9. Cyclone V FPGA Multiplier Count Comparison
Cyclone V FPGA 5CGXC4

210 140 140 140 70 70 70
Artix-7 XC7A50T
120 120 120 120 120 60 60
More DSP Resources vs. the Competition
DSP Block Evolution

Alteras DSP block architecture has evolved at each process node over time, as illustrated in Figure 10. The fundamental theme of this evolution is backwardscompatibility and new features that support the next generation of DSP system designs.
Figure 10. Evolution of DSP Blocks in Arria V FPGA
Arria GX FPGA
36 36 72
Arria II FPGA
36 108
Arria V FPGA
Variable-Precision DSP Block Variable-Precision DSP Block Variable-Precision DSP Block Variable-Precision DSP Block
74
36
36
72
DSP Half Block
36
108
74
DSP Block
36 36 72 36 108 74
DSP Half Block

36 36 72 36 108 74
Four 18x18 Multipliers (Independent)
Eight 18x18 Multipliers (Sum) Four 18x18 Multipliers (Independent)
Eight 18x19 Multipliers (Sum) Eight 18x19 Multipliers (Independent) Four High-Precision Mode Blocks
Historically, the Arria device DSP block implemented four independent 18x18 multipliers. The Arria II device DSP block continues to support this mode and adds more efficient implementation of eight 18x18 multipliers in sum mode via a 44-bit cascade bus. Designers can effectively use this mode to implement common FIR filter structures. The latest 28-nm, variable-precision DSP blocks in Arria V and Cyclone V devices maintain compatibility with previous generation devices, while increasing capability for higher precision signal processing. The Arria V and Cyclone V DSP block architecture fabric is enhanced to implement the highest performance and highest precision DSP application data paths.
May 2011
Altera Corporation
DSP Block Evolution
Page 7
Key DSP Enhancements

Arria V and Cyclone V DSP blocks include the following enhancements:

Pre-adders 18x19 Multipliers Coefficient Banks Feedback Registers Independent Multipliers
The following sections discuss these enhancements in greater detail.
Pre-adders
The Arria V and Cyclone V DSP block is enhanced to include pre-adders to reduce multiplier count in symmetric FIR filters, as shown in Figure 11. These pre-adders accept full 18-bit operands, including sign bits. These pre-adders are referred to as hard pre-adders because they are implemented in dedicated hardware resources, rather than as FPGA logic gates.
Figure 11. Pre-Adders High Level View
64 Bits
18 +/18
18x19 X
Output Multiplexer
Input Register
18 Bits
108 Bits
Coefficient Bank + -
Output Register
+ -
74 Bits
18 Bits
Coefficient Bank
18
18x19
Pre-Adders
+/-
Feedback Register 64 Bits
18
Figure 12 provides a more detailed view of the hard pre-adders. The next section provides an example application that uses pre-adders in a FIR filter design.
May 2011
Altera Corporation
Page 8
DSP Block Evolution
Figure 12. Hard Pre-Adder Detail
18 18
+/19
X 18 C0 + _ C1 18
18 18
+/19
X 18 +
Enhanced Pre-Adders
Enhanced Pre-Adders
38
38
18 18 18 +/19 X
18 18
+/19
Figure 13 illustrates the use of pre-adders in a FIR filter. Typically designers use preadders for building symmetric FIR filters. As the filter data is shifted across the coefficient set, two data samples can be multiplied by a common coefficient due to the symmetry. The pre-adder adds two samples prior to multiplication, which allows the use of one, rather than two, multipliers for every two data samples. Pre-adders reduce by half the number of required multipliers for symmetric FIR filters, and eliminate the need to implement such adders using the logic gates in the FPGA. This technique increases logic efficiency and performance. Designers can use this hard pre-adder as either a dual 18-bit pre-adder, or as a single 27-bit pre-adder, depending on the required precision.
Figure 13. Usage of Pre-adders in Symmetric FIR Filter
D3 D2 D1 D0 D3 D2
Pre-Adders 18x19 +/X

it t -B n 18 fficie e Co it t -B n 18 fficie e Co
D0
D1
+ C0
+ C1 X +
C0 X +
C1 X
C1 X +
C0 X +/-
X 18x19
Benefit: reduce from 4 to 2 multipliers
May 2011 Altera Corporation
DSP Block Evolution
Page 9
18x19 Multipliers
The Arria V and Cyclone V DSP block is enhanced to include an 18x19 multiplier, as shown in Figure 14.
Figure 14. 18x19 Multipliers
18 +/18
18x19 X
64 Bits
Output Multiplexer
Input Register
18 Bits
108 Bits
Output Register
+ -
74 Bits
18 Bits
Coefficient Bank
18
18x19
18x19 Multipliers
+/-
18
Previous generation devices included only an 18x18 multiplier. The 18x19 multiplier accepts 19-bit results from the output of the 18+18 pre-adder. Designers can use the extra bit in each pre-adder operand to represent the + or - sign of each operand. Figure 15 shows a close-up view of the 18x19 multiplier.
Figure 15. Close-up View of 18x19 Multiplier
18 18
+/19
X 18 C0 + _ C1 18 38
18x19 Multipliers
18 18
+/19
May 2011
Altera Corporation
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DSP Block Evolution
Figure 16 illustrates an example application of the 18x19 multiplier.

Figure 16. Usage of 18x19 Multiplier
Benefit: 18x19 multiplier accepts 18+18 data => full 18-bit add with 19-bit result
18
18x19 Multipliers
+
18
19
18x19
MLAB
MLAB
Coefficient Bank* 18
18
+
18
19 18x19
MLAB
MLAB
+
DSP Block MLAB: N accumulator registers for N channels
MLAB + MLAB
19 18x19
MLAB MLAB
* Use memory logic array block (MLAB) for cases where number of coefficients per multiplier > 8
Coefficient Banks
Arria V and Cyclone V DSP blocks include a coefficient storage bank that is dynamically selectable on each clock cycle, as illustrated by Figure 17.
Figure 17. Coefficient Blocks within the DSP Block
64 Bits
18 +/18
18x19 X
Output Multiplexer
Input Register
18 Bits
108 Bits
Output Register
+ -
74 Bits
18 Bits
Coefficient Bank
18
18x19
Coefficient Banks
+/-
18
This feature is especially helpful in DSP designs that include FIR filters implemented in hardware using a parallel or partially parallel structure, which often require only a small number of coefficients per multiplier. Alteras variable-precision DSP architecture provides an internal coefficient bank that designers can set to support 18bit and higher precision signal processing. In 18-bit mode, the coefficient bank is
DSP Block Evolution
Page 11
configured as two, 18-bit wide register banks, each capable of storing eight coefficients per multiplier. In the high-precision mode, the coefficient bank is configured as a single, 27-bit wide register bank capable of storing eight coefficients per multiplier. The coefficient banks allow designers to select which of the eight registers should be used as a coefficient source for the multiplier for every clock cycle. Use of the internal coefficient bank eases timing closure complexity and reduces onchip memory and register resource usage, both of which are critical in DSP designs. Figure 18 shows the coefficient bank in the 18-bit mode and in the 27-bit mode.
Figure 18. Structure of Coefficient Bank
18 Bits 0 1 2 3 4 5 6 7 18 Bits 0 1 2 3 4 5 6 7 27 Bits
OR
Figure 19 shows how a serial filter is implemented, making use of the two 18-bit coefficient banks. The DSP architecture of the Arria V and Cyclone V FPGA effectively supports this type of filter because the coefficient banks, the 18x19 multipliers, and the output register are all contained in one DSP block. In addition, the output can be cascaded to the next block in a sequential chain. Having the coefficient bank inside the DSP block reduces logic and routing utilization, thus improving filter performance.
Figure 19. Usage of Coefficient Bank in Filter
Benefit: reduce logic and routing utilization => improve filter performance Bias Register
Coefficient Banks 18 bits 18 bits 18 bits Input Register

it t -B n 18 fficie e Co
X 27x27
18-bit +/-
X 18x19
+ X 18x19
18 bits 18 bits 18 bits
it t -B n 18 fficie e Co
+
Feedback Register
Output Register
64 Bits
18-bit +/-
May 2011
Altera Corporation
Page 12
DSP Block Evolution
Feedback Registers
Arria V and Cyclone V DSP blocks include feedback registers that can serve as the second stage in a two-stage accumulator comprised of the output register and feedback registers. The relative position of the feedback register in the DSP block is illustrated in Figure 20.
Figure 20. Feedback Register
18 +/18
18x19 X
64 Bits
Output Multiplexer
Input Register
18 Bits
108 Bits
Output Register
+ -
74 Bits
18 Bits
Coefficient Bank
18
18x19
Feedback Register
+/-
18
Figure 21 shows how a polyphase serial filter is implemented, with the feedback register enabled to provide a feedback path. This structure enables two independent serial-filter channels in one single DSP block. Each channel has its own set of input. The feedback path is time multiplexed, allowing processing of the real part and the imaginary part of a complex signal in alternating clock cycles. Only N/2 adders are needed because the Arria V and Cyclone V DSP block in 18-bit mode has two 18x19 multipliers per DSP block. This implementation is efficient and saves resources.
Figure 21. Feedback Register Usage
DSP Block
M10K
+
18x19
N:1 Complex Input Data Demultiplexer
M10K
18x19
N/2:1 Multistage Adder, Using Complex Inputs and Outputs Feedback Register
M10K
+
M10K
18x19
DSP Block Evolution
Page 13
Independent Multipliers
Arria V and Cyclone V DSP blocks include independent multipliers. This means that the output(s) of the multiplier(s) can be routed to the output port of the DSP block directly, without going through any adder. Figure 22 shows two 18x19 multipliers which can be configured to work in the sum mode or independent mode
Figure 22. Input/Output Ports
18 +/18
18x19 X
64 Bits
Output Multiplexer
Input Register
18 Bits
108 Bits
Output Register
+ -
74 Bits
18 Bits
Coefficient Bank
18
18x19
Independent Multipliers
+/-
Feedback Register 64 Bits +/19 18 X 37 C0 C1 18 +/19 X 37
18
Each DSP Block contains two 18x19 multipliers. These blocks can be used as two completely independent multipliers with inputs fed from outside the DSP block, as shown on the left-hand side of Figure 23, or each multiplier having one operand fed from a coefficient bank, and the outputs of the multipliers delivered independently, as shown on the right hand side of Figure 23. The output port of the DSP block in Arria V and Cyclone V is 74-bits wide and therefore can accommodate the output of 37 bits of the two independent 18x19 multipliers. This means that all 37 bits from each multiplier are directly accessible on the output port.
Figure 23. Application Example
18 18 18 19 X 37
18x19 Multipliers
18 19 X 37 18 18
May 2011
Altera Corporation
Page 14
Altera Floating-Point Precision
Altera Floating-Point Precision

Depending on the application, the precision requirement may require that multiplications are performed with single-precision, floating-point multiplications, or double-precision, floating-point multiplications. The Arria V and Cyclone V DSP block is capable of both levels of precision, as described in the following sections. IEEE Standard 754 floating point is the most common representation of floating-point numbers. In this format, single-precision floating point is 32-bits wide with a 24-bit mantissa, while double-precision floating point is 64-bits wide and has a 53-bit mantissa. Floating-point computations involve mantissa multiplication and exponent addition. The Altera variable-precision DSP architecture can implement mantissa multiplication for a single-precision, floating-point number using one block OR mantissa multiplication for a double-precision, floating-point number.
Single-Precision Floating-Point Multiplication

Using the high-precision mode, the variable-precision block is uniquely suited for implementing single-precision, floating-point operations. Mantissa multiplication can be implemented using only one variable-precision block configured in the highprecision mode. This resource efficiency is an FPGA industry first. Traditionally designers had to cascade multiple blocks to implement this operation. The coefficients may be applied externally as shown on the left-hand side or internally as shown on the right-hand side in Figure 24. Competing DSP architectures with 18x25 bit resolution require multiple blocks, as well as external logic to implement a floatingpoint mantissa multiplication, resulting in a lower performance and higher power implementation.
Figure 24. Single-Precision Floating-Point Multiplication
27 27x27 X Output Multiplexer Intermediate Multiplexer Output Register 64 Bits
Input Register
108 Bits
+ -
74 Bits
25
+/-
25
CONFIGURABLE 27 Bits
Input Register
Input Register
X 27x27
Acc Reg
64
it t -B n 27 fficie oe C
X 27x27
Acc Reg
64
27 Bits
27 Bits
Competitive Summary
Page 15
Double-Precision Floating-Point Multiplication

Double-precision mantissa multiplication requires four DSP blocks all cascaded by using the dedicated 64-bit cascade bus in the DSP block, as shown in Figure 25.
Figure 25. Floating-Point Modes
27 27x27 X Output Multiplexer Intermediate Multiplexer Output Register 64 Bits
Input Register
108 Bits
+ -
74 Bits
25
+/-
Feedback Register 64 Bits 64 Bits
25
27
27x27 X
Output Multiplexer
Input Register
27
27x27 X
64 Bits
Output Register
108 Bits
+ -
74 Bits
Output Multiplexer
Output Register
25
Input Register
+/-
25
108 Bits
+ -
74 Bits
Output Multiplexer
Feedback Register
25 Feedback Multiplexer +/25
Input Register
Output Register
OR
108 Bits
27
27x27 X
+ -
74 Bits
25
+/-
25
64 Bits
27 27x27 X Output Multiplexer Intermediate Multiplexer Output Register
Input Register
108 Bits
+ Feedback Multiplexer
+ -
74 Bits
25 +/25
Single-Precision Mantissa Multiplication (27x27 Mode)
Double-Precision Mantissa Multiplication (54x54 Mode)
This technique is an FPGA industry first, because competing architectures require cascading two 18x25 blocks for single-precision, floating-point mantissa multiplication and up to nine blocks (with extra logic) to implement a 54x54 doubleprecision mantissa multiplier.
Competitive Summary
With the introduction of the variable-precision DSP architecture, Altera has opened a DSP technology gap against competing architectures, as summarized in Figure 26. Alteras latest 28-nm devices can natively, and within a single block, implement a 27x27 multiplier useful for high-precision, fixed-point DSP, or for emerging floatingpoint DSP applications. Variable precision means that designers set the DSP architecture precision to match the algorithm, not the other way around. Also with a 64-bit cascade bus and accumulator, designers don't have to forgo precision when the algorithm implementation requires multiple DSP blocks.
May 2011
Altera Corporation
Page 16
Conclusion
Figure 26. Competitive Comparison

Arria V and Cyclone V FPGAs
Feature Native support for 27x27 multiply mode Variable-precision multiplier size: 27x27 or 18x19 (dual) Efficient implementation of floating point Coefficient register banks within the DSP block Efficient 2-stage accumulator (feedback register) Accumulator size Width of cascade bus Pre-adder support for symmetric filters Support for systolic FIR filters
Xilinx
48 bits 48 bits
64 bits 64 bits
Conclusion
Altera's variable-precision DSP block allows the designer to tailor the precision on a block-by-block basis. For symmetric filters, hard pre-adders in the DSP block reduce the required multiplier count by 50%, thus saving resources and power. The 18x19 multipliers accommodate full 18+18 addition, including sign bits. Internal coefficient banks enable higher multiplier performance and save logic resources. The Arria V and Cyclone V DSP block is optimized for FIR filters, and the feedback register allows implementation of two independent serial-filter channels per DSP block. The independent multipliers allow operands to be applied directly to the multipliers and allow the multiplier outputs to be observed directly on the DSP block output port. Finally, Altera offers the industry's first floating-point function in an FPGA architecture.
Further Information
Arria V FPGA Family Overview http://www.altera.com/products/devices/arria-fpgas/arria-v/overview/arrvoverview.html Arria V Device Family Advance Information Brief http://www.altera.com/literature/hb/arria-v/av_51001.pdf Cyclone V FPGA Family Overview http://www.altera.com/products/devices/cyclone-v-fpgas/overview/cyvoverview.html Cyclone V Device Family Advance Information Brief http://www.altera.com/literature/hb/cyclone-v/cyv_51001.pdf
Acknowledgements
Pat Fasang, Senior Member of Technical Staff, DSP Marketing, Altera Corporation

Altera Enabling High-Performance DSP Applications With Arria V or Cyclone V Variable-Precision DSP Blocks

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Enabling High-Performance DSP Applications with Arria V or Cyclone V Variable-Precision DSP Blocks

WP-01159-1.0 White Paper

Key DSP Design Trends

9-Bit Precision 100 GMACS

Floating-Point Precision TeraFLOPS

Applications Moving to Variable and Higher Precisions

101 Innovation Drive San Jose, CA 95134 www.altera.com May 2011

Variable-Precision DSP at 28nm

High-Precision DSP Applications

Variable-Precision DSP at 28nm

Variable-Precision DSP at 28nm

Figure 3. Architecture with Selectable Precision

Set the Precision Dial to Match Your Application

Variable-Precision DSP Blocks

18x18 18x25 18x36 27x27 18x18 18x25 18x36* 27x27 18x25

18x18 18x25 18x36 27x27 18x18 18x25 18x36* 27x27 18x25

27x27 36x36* 54x54* 18x25

Supported Precisions (Competitive FPGAs)

* Requires additional logic outside of the DSP block to implement

Variable-Precision DSP at 28nm

+ 18 Bits Coefficient Bank

Coefficient Bank 27 bits

18-Bit Precision Mode

Within 2 DSP Blocks

4 Within 3 DSP Blocks

* Requires additional logic outside of the DSP block to implement

Variable-Precision DSP at 28nm

Figure 7. Multiplier Precision Comparison

Arria V & Cyclone V Variable-Precision DSP Block

18x25 DSP48 Block

* Requires additional logic outside of the DSP block to implement

2X to 3X Number of Multipliers per Variable-Precision DSP Block Means Power Reduction

DSP Multiplier Comparison

Arria V FPGA 5AGXB3

More DSP Resources vs. the Competition

DSP Block Evolution

Figure 9. Cyclone V FPGA Multiplier Count Comparison

Cyclone V FPGA 5CGXC4

More DSP Resources vs. the Competition

DSP Block Evolution

DSP Half Block

DSP Half Block

Four 18x18 Multipliers (Independent)

Eight 18x18 Multipliers (Sum) Four 18x18 Multipliers (Independent)

DSP Block Evolution

Key DSP Enhancements

Pre-adders 18x19 Multipliers Coefficient Banks Feedback Registers Independent Multipliers

The following sections discuss these enhancements in greater detail.

Feedback Register 64 Bits

DSP Block Evolution

Figure 12. Hard Pre-Adder Detail

Pre-Adders 18x19 +/X

Benefit: reduce from 4 to 2 multipliers

May 2011 Altera Corporation

DSP Block Evolution

Feedback Register 64 Bits

DSP Block Evolution

Figure 16 illustrates an example application of the 18x19 multiplier.

Feedback Register 64 Bits

May 2011 Altera Corporation

DSP Block Evolution

Coefficient Banks 18 bits 18 bits 18 bits Input Register

18 bits 18 bits 18 bits