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STP12PF06 STF12PF06
Figure 1:Package
RDS(on) < 0.20 < 0.20 ID 12 A 12 A
VDSS 60 V 60 V
TYPICAL RDS(on) = 0.18 EXCEPTIONAL dv/dt CAPABILITY 100% AVALANCHE TESTED LOW GATE CHARGE APPLICATION ORIENTED CHARACTERIZATION
3 1 2
1 2
TO-220
TO-220FP
DESCRIPTION This Power MOSFET is the latest development of STMicroelectronis unique "Single Feature Size" strip-based process. The resulting transistor shows extremely high packing density for low onresistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility APPLICATIONS MOTOR CONTROL DC-DC & DC-AC CONVERTERS
Value STF20PF06
() Pulse width limited by safe operating area. NOTE:For the P-CHANNEL MOSFET actual polarity of voltages
and current has to be reversed.
March 2005
Rev. 2.0
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Table 4: THERMAL DATA
TO-220 Rthj-case Rthj-amb Tl Thermal Resistance Junction-case Thermal Resistance Junction-ambient Maximum Lead Temperature For Soldering Purpose Max Max 2.5 62.5 300 TO-220FP 5.35 C/W C/W C
Table 5: OFF
Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 250 A, VGS = 0 VDS = Max Rating VDS = Max Rating TC = 125C VGS = 20V Min. 60 1 10 100 Typ. Max. Unit V A A nA
Table 6: ON (*)
Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS VGS = 10 V ID = 250 A ID = 10 A Min. 2 Typ. 3.4 0.18 Max. 4 0.20 Unit V
Table 7: DYNAMIC
Symbol gfs (2) Ciss Coss Crss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions VDS = 15 V ID = 6 A Min. 2.5 Typ. 6 850 230 75 Max. Unit S pF pF pF
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ELECTRICAL CHARACTERISTICS (continued)
Table 8: SWITCHING ON
Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 30 V ID = 6 A VGS = 10 V RG = 4.7 (Resistive Load, Figure 19) VDD= 48 V ID= 12 A VGS= 10 V Min. Typ. 20 40 16 4 6 21 Max. Unit ns ns nC nC nC
Test Conditions
Min.
Typ.
Max. 10 40
Unit A A V ns nC A
ISD = 12 A
2.5
ISD = 12 A di/dt = 100A/s Tj = 150C VDD = 30 V (see test circuit, Figure 21)
(1 )Pulse width limited by safe operating area. (2) Pulsed: Pulse duration = 300 s, duty cycle
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Figure 5: Thermal Impedance Figure 6: Thermal Impedance for TO-220FP
Figure 9: Transconductance
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Figure 11: Gate Charge vs Gate-source Voltage Figure 12: Capacitance Variations
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Figure 17: Unclamped Inductive Load Test Circuit
Figure 18: Unclamped Inductive Waveform
Figure 21: Test Circuit For Inductive Load Switching And Diode Recovery Times
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L3 L6 L7
F1
G1
E F2
1 2 3 L2 L4
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Table 11:Revision History
Date
March 2005 March 2005
Revision
1.0 2.0 FIRST ISSUE MINOR REVISION
Description of Changes
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners.
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