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The format used to present the logic output for the various combinations of logic inputs to a gate is called a(n): A. B. C. D. truth table. input logic function. Boolean constant. Boolean variable.
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 2.
What is the basic difference between AHDL and VHDL? A. B. C. D. ADHL is used in all PLD's. VHDL is used in all PLD's. ADHL is proprietary. VHDL is proprietary.
Answer: Option C Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
3.
A small circle on the output of a logic gate is used to represent the: A. B. C. D. Comparator operation. OR operation. NOT operation. AND operation.
Answer: Option C Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
4.
For a three-input OR gate, with the input waveforms as shown below, which output waveform is correct?
A. C.
a c
B. D.
b d
Answer: Option B Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
5.
A.
B.
C.
D.
6.
Answer: Option D Which of the figures (a to d) is the DeMorgan equivalent of Figure (e)?
A. C.
a c
B. D.
b d
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 7.
A. C.
a c
B. D.
b d
Answer: Option C Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
8.
In VHDL, the mode of a port does not define: A. B. C. D. an input. an output. both an input and an output. the TYPE of the bit.
Answer: Option D Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
9.
Which of the following equations would accurately describe a 4-input OR gate when A = 1, B = 1, C = 0, and D = 0? A. B. C. D. 1+1+0+0=1 1 + 1 + 0 + 0 = 01 1+1+0+0=0 1 + 1 + 0 + 0 = 00
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
10. Which of the examples below expresses the distributive law? A. B. C. (A + B) + C = A + (B + C) A(B + C) = AB + AC A + (B + C) = AB + AC
D.
A(BC) = (AB) + C
Answer: Option B 11. Which of the examples below expresses the associative law of addition: A. B. C. D. A + (B + C) = (A + B) + C A + (B + C) = A + (BC) A(BC) = (AB) + C ABC = A + B + C
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 12. How are the statements between BEGIN and END not evaluated in VHDL? A. C. Constantly Concurrently B. D. Simultaneously Sequentially
Answer: Option D Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
A. C.
AND NAND
B. D.
OR NOR
Answer: Option D Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
14. For a 3-input NAND gate, with the input waveforms as shown below, which output waveform is correct?
A. C.
a c
B. D.
b d
Answer: Option C Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
A. C.
a c
B. D.
b d
Answer: Option A Explanation: 16. Which timing diagram shown below is correct for an inverter?
A. C.
a c
B. D.
b d
Answer: Option B Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 17. A NOR gate with one HIGH input and one LOW input: A. B. C. D. will output a HIGH functions as an AND will not function will output a LOW
Answer: Option D Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
18. A NAND gate has: A. B. C. D. active-LOW inputs and an active-HIGH output. active-LOW inputs and an active-LOW output. active-HIGH inputs and an active-HIGH output. active-HIGH inputs and an active-LOW output.
Answer: Option D Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
A. C.
a c
B. D.
b d
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
B.
C.
D.
Answer & Explanation
Answer: Option C Explanation: 21. The logic gate that will have HIGH or "1" at its output when any one of its inputs is HIGH is a(n): A. B. C. D. NOR gate OR gate AND gate NOT operation
Answer: Option B Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 22. Which of the symbols shown below represents an AND gate?
A. C.
a c
B. D.
b d
Answer: Option D Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
23. For a three-input AND gate, with the input waveforms as shown below, which output waveform is correct?
A. C.
a c
B. D.
b d
Answer: Option C Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
24. An OR gate with inverted inputs functions as: A. B. C. D. an AND gate. a NAND gate. a NOR gate. an inverter.
Answer: Option B
Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
25. The special software application that translates from HDL into a grid of 1's and 0's, which can be loaded into a PLD, is called a: A. B. C. D. formatter. compiler. programmable wiring. CPU.
Answer: Option B Explanation: 26. The Boolean equation for a NOR function is: A.
B.
C. D.
Answer & Explanation
Answer: Option B Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum 27. Which step in this reduction process is using DeMorgan's theorem?
A. B. C. D.
Answer: Option A Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
B.
C.
D.
Answer & Explanation
Answer: Option B Explanation: No answer description available for this question. Let us discuss. View Answer Workspace Report Discuss in Forum
29. For a three-input NOR gate, with the input waveforms as shown below, which output waveform is correct?
A. C.
a c
B. D.
b d
Answer: Option A