International Journal of Power and Energy Systems, Vol. 28, No.

4, 2008

VOLTAGE SAG AND SWELL MITIGATION USING MULTI-LEVEL INVERTER-BASED CUSTOM POWER CONDITIONERS
C. Sharmeela and M.R. Mohan

Abstract
The main purpose of the Distribution STATic COMpensator (DSTATCOM) and Static Series Compensator (SSC) commercially called as Dynamic Voltage Restorer (DVR) is that it injects reactive power in shunt and series, respectively, with a distribution feeder to reduce the eect of short-term voltage sags, swells and momentary interruptions in the distribution system. This paper presents a Voltage Source Converter (VSC) based multi-level D-STATCOM and DVR controlled by sinusoidal PWM for the mitigation of voltage sag/swell and voltage sag respectively. The modelling and transient simulation have been carried out by PSCAD/EMTDC. The eectiveness of multi-level D-STATCOM for the mitigation of voltage sag/swell and DVR for the mitigation of voltage sag has been demonstrated by case studies.

Key Words
Custom power, D-STATCOM, SSC, multi-level inverter, SPWM, PSCAD/EMTDC

1. Introduction Power quality has become an increasingly important topic to be considered for the performance improvement of many industrial applications. One of the major issues in improving power quality in distribution networks is the mitigation of voltage sags and swells. In automated industries, the eect of voltage sag and swell can lead to production downtime and equipment damage. The problem of power quality can be alleviated by custom power conditioners. Custom power conditioners are either series active or shunt active lters. They are used in distribution system to provide better voltage regulation, near zero power interruptions, low harmonic voltages and to improve the power factor. The recent trends are growing towards the use of Voltage Source Converter (VSC) based custom power devices [1]. The conventional two-level inverter has practical
Engineering Division, Department of Chemical Engineering, A.C. College of Technology, Anna University, Chennai 600 025, India; e-mail: sharmeela20@yahoo.com DEEE, Anna University, Chennai 600 025, India; e-mail: mohan@annauniv.edu Recommended by Dr. Dariusz Czarkowski (paper no. 203-3907)

limitations in achieving higher output voltage. The use of series connection of devices to increase its rating would not result in better performances [2, 3]. Multi-step inverters discussed in [4] are able to meet these requirements, but they suer from the limitations of occupying large area, having slow dynamic response and are very expensive [5, 6]. The multilevel inverters attempt to overcome some of the limitations addressed above and are found to be the most suitable for medium-voltage and high-power applications such as STATic COMpensator (STATCOM), Active Power Filter (APF) [710] and motor drives [1113]. The Multilevel Diode-Clamped Inverter (MLDCI) is simple and easy to control [14, 15]. This conguration is reported to be an eective solution for voltage-sourced converters connected to high voltage distribution networks and widely employed in several FACTS devices [16]. This paper presents the ve-level diode-clamped DSTATCOM for the voltage sag/swell mitigation and Static Series Compensator (SSC) commercially called as Dynamic Voltage Restorer (DVR) for the voltage sag mitigation. A simple ProportionalIntegral (PI) control scheme is proposed for closed loop voltage control and the gating pulses for MLDCI are generated by Sinusoidal Pulse Width Modulation (SPWM)technique. The paper is organized as follows. The principle of operation of MLDCI has been discussed in Section 2. The application and the simulation studies of multilevel VSCbased D-STATCOM for voltage sag/swell mitigation and SSC (DVR) for voltage sag mitigation have been discussed in Section 3. The conclusions and scope for further work have been presented in Section 4. 2. Multi-Level Diode-Clamped Inverter The multi-level diode-clamped VSC is preferred over the two-level VSC for high power applications as it reduces the Total Harmonic Distortion (THD) in Point of Common Coupling (PCC) voltage and source current for a given DC link voltage and inverter switching frequency. 2.1 Basic Conguration The simplest diode-clamped inverter is known as the Neutral Point Clamped converter (NPC) [17]. Fig. 1 shows 384

Table 1 Five-Level Inverter Parameters Number of main switches per leg Device ON resistance () Device OFF resistance () Forward voltage drop (kV) 20 0.01 1.0E6 0.0

Forward break over voltage (kV) 1.0E5 Reverse withstand voltage (kV) Snubber resistance () Snubber capacitance (F) 1.0E5 500 25

Figure 1. One phase leg of an m-level diode-clamped inverter. one phase of an m-level diode-clamped inverter. Node p indicates the positive bus, Node n indicates the negative bus and o is the mid point of the dc bus. All the capacitors shown in Fig. 1 are of equal voltage rating. In Fig. 1, the switching states Sa1 , Sa2 , Sa(m2) and Sa(m1) take the value 1 if the corresponding switch is conducting and 0 otherwise. For a ve-level inverter, the switch combinations given in [14, 15, 17] are used to synthesize the output voltage Vao of phase a with respect to the neutral point o. The ve-level inverter parameters are given in Table 1. An m-level MLDCI requires (m 1) pairs of power semiconductor devices and 2(m 2) clamping diodes per phase leg in addition to (m 1) main DC capacitors of equal value. The number of switches to be turned ON at a time is (m 1) to produce m-level output phase voltage in the case of MLDCI. The line-to-line output voltage of the inverter varies from +Vdc to Vdc and has (2m 1) levels in the output, while the phase voltage varies from +Vdc /2 to Vdc /2 with m-levels. Of the various strategies developed to improve the output voltage waveform of a VSI multiple carrier method of SPWM strategy is employed here [17]. In this method, (m 1) triangular carrier signals (Vt ) are compared with a controlled sinusoidal modulating signal (Vr ). All of the carriers have the same frequency and amplitude. The carrier signal used is In Phase (IPSPWM) [1820]. Hence the multi-level inverter is capable of generating a more sinusoidal waveform with lower device ratings and required switching frequency. The % THD can be further minimized by increasing the carrier wave frequency. The 5-level diode-clamped inverter is simulated using PSCAD/EMTDC [21]. 3. MLDCI-based D-STATCOM and DVR This section presents the MLDCI-based custom power controllers such as D-STATCOM and DVR. Although theoretically, it is possible to realize an m-level diode-clamped 385

inverter, there exists few diculties from the hardware implementation point of view. As the number of levels increases, the number of devices to be turned ON/OFF also increases. The generations of gating signals at higher carrier frequency become a dicult task resulting in narrow pulse width for each turn ON and turn OFF of the device. Also the practical issues such as capacitor voltage unbalance, unequal and high voltage rating for clamping diodes have restricted the maximum number of levels to ve in the proposed work. 3.1 MLDCI-based D-STATCOM The proposed D-STATCOM conguration is based on a ve-level VSC. The ve-level VSC converts the DC voltage across the capacitor in to a set of three-phase AC output voltages. These voltages are phase coupled with AC system through the reactance of the coupling transformer. By varying the phase and magnitude of the output voltages of D-STATCOM eective control of active and reactive power exchange between the D-STATCOM and the AC system is achieved [22]. Voltage regulation and reactive power compensation are also achieved by controlling the multi-level VSC connected in shunt with the AC system. The basic block diagram of the distribution system with multi-level D-STATCOM is shown in Fig. 2. In the present work, ve-level D-STATCOM is used to regulate voltage at the PCC. The control is based on SPWM. 3.1.1 SPWM Control The block diagram of the overall system with D-STATCOM and DVR are shown in Figs. 2 and 12, respectively. The aim of the control scheme is to maintain the constant voltage at the PCC. The multi-level VSC switching strategy is based on the SPWM technique, which oers simplicity and good response. The PCC voltage regulator (PI controller) generates the required delay angle . In the SPWM controller, the sinusoidal signal is phase modulated by means of the angle and generates the switching pulses for the multi-level VSC. The main parameters of the SPWM scheme are the amplitude modulation index ma of the modulating signal and the frequency modulation index

Figure 2. System under study with multi-level D-STATCOM.

Figure 3. RMS voltage at PCC without D-STATCOM. mf (integral multiple of the fundamental frequency 50 Hz) of the carrier signal. The ma can vary from 0 to 1 pu. The carrier frequency of 450 Hz with mf = 9 is used for the present study. For the balanced network, the ring pulses for the phases B and C are shifted by 120 and 240 , respectively. The control implementation is kept very simple by using only voltage signal as the feedback variable in the control scheme. 3.1.2 Simulation Results The main functions of the proposed D-STATCOM are reactive power compensation and the mitigation of voltage sag/swell. The test system comprises of 230 kV transmission system, represented by Thevenin equivalent, feeding the primary side of transformer. A varying load of (0.482 + j1.769) is connected to the 11 kV, secondary side of the transformer. A ve-level D-STATCOM is connected through a coupling transformer to the 11 kV secondary winding to provide instantaneous voltage support at the load point. An 800 F capacitor on the DC side provides the required DC voltage for D-STATCOM. The performance evaluation of the proposed multilevel D-STATCOM is investigated by the following test case conditions. The simulation results of the RMS voltage at the PCC for without and with ve-level diode-clamped D-STATCOM are shown in Figs. 3 and 4(a), respectively. A zoom in 386 the parts in which sag and swell occurred is shown in Fig. 4(b, c) for evidencing the dynamic response of the system. During the simulation period of 0.30.6 s, a step increase in load of 165% is applied. In this case the RMS voltage drops by 25% with respect to the reference voltage value of 1.0 pu. At 0.6 s, the heavy load is withdrawn. In this case, the RMS voltage at the PCC is very close to the reference voltage value of 1.0 pu. In the simulation period of 0.91.2 s the capacitor banks are connected to the high voltage side of the network. In this case, the RMS voltage increases by 23% with respect to the reference voltage value of 1.0 pu. The phase voltage at PCC during the voltage sag/swell for without and with D-STATCOM connected is shown in Fig. 5 to give a better idea of the D-STATCOM performance. The source current and the D-STATCOM output current are shown in Figs. 6 and 7, respectively. In Figs. 6 and 7, it is observed that the source current magnitude remains practically constant irrespective of the changes in the load as the D-STATCOM compensates for the reactive power requirement. The performance of the system response for short duration voltage sag (0.40.5 s) and voltage swell (1.01.1 s) is tested and the results of the RMS voltage and phase voltage at PCC during short duration voltage sag/swell for without and with D-STATCOM are shown in Figs. 8 and 9, respectively. It is to be noted that the performance of the D-STATCOM is found to be satisfactory during short duration voltage sag/swell condi-

Figure 4. (a) RMS voltage at PCC with D-STATCOM. (b) Zoomed version of the RMS voltage at voltage sag. (c) Zoomed version of the RMS voltage at voltage swell.

Figure 5. Phase voltage at PCC. (a) Without D-STATCOM; (b) with D-STATCOM. tions. In Figs. 49 it is be noted that the D-STATCOM injects/absorbs reactive current so as to maintain the PCC voltage constant during voltage sag/swell conditions. It is found that the performance of ve level DSTATCOM is satisfactory in providing eective and con387 tinuous voltage regulation of the RMS voltage at the load point (PCC). When voltage sag occurs, the D-STATCOM supplies reactive power to the system. During voltage swell, the D-STATCOM absorbs reactive power to maintain the PCC voltage to the reference value (see Fig. 4). In

Figure 6. Source current with D-STATCOM.

Figure 7. D-STATCOM output current.

Figure 8. RMS voltage at PCC for short duration sag and swell. (a) Without D-STATCOM; (b) with D-STATCOM. spite of sudden load variations, the regulated RMS voltage shows a reasonably smooth prole, with less transient overshoot. The magnitude of these transients is kept within 5% with respect to the reference voltage and they do not last for more than two cycles. The PI controller settings 388 works satisfactorily for 20% of impedance variations during voltage sag and 25% of capacitance variations during voltage swell conditions. The FFT analysis of PCC voltage and source current with the D-STATCOM is shown in Figs. 10 and 11, respectively. The % THD for PCC voltage

Figure 9. Phase voltage at PCC for short duration sag and swell. (a) Without D-STATCOM; (b) with D-STATCOM.

Figure 10. Harmonic spectrum of PCC voltage with D-STATCOM. and source current have been computed and found to be 2.108% and 7.825%, respectively. This indicates that the harmonics originated due to the switching action of the D-STATCOM is within the acceptable IEEE 519 limits. 3.2 MLDCI-based SSC (DVR) The SSC (DVR) is a series custom power controller that is commonly used for voltage sag mitigation at the point of connection. The DVR employs the same blocks as the D-STATCOM, with the coupling transformer connected in series with the AC system. The basic block diagram of the distribution system with multi-level DVR is illustrated in Fig. 12. The VSC generates a three-phase AC output voltage, which is controllable in phase and magnitude. These voltages are injected into the AC distribution system to maintain the load voltage at the desired voltage reference. The control and the generation of gating signals of the multilevel DVR are similar to that used for D-STATCOM. 389

Figure 11. Harmonic spectrum of source current with D-STATCOM. 3.2.1 Case Study for DVR The main function of the ve-level DVR is voltage sag mitigation at the load point. The DVR coupling transformer is connected in delta in the DVR side, with a leakage reactance of 10%. A unity transformer turns ratio is used. The capacity of the DC storage device is 5 kV. During the simulation period of 0.30.6 s, a symmetrical short circuit fault is applied at point F and F through a fault resistance of 0.33 near the sensitive load and non-sensitive load, respectively. In this case the RMS voltage drops by almost 27% with respect to the reference voltage value of 1 pu. At 0.6 s, the fault is withdrawn. In this case, the RMS voltage at the load is very close to the reference voltage value of 1.0 pu. The simulation results of the RMS voltage at the load point for without and with DVR connected to the system are shown in Fig. 13(ac). It is to be noticed that, the ve-level VSC-based DVR is found to oer eective and continuous voltage regulation of the RMS voltage at the

Figure 12. Basic block diagram of the proposed multi-level DVR.

Figure 13. Load RMS voltage. (a) Without DVR; (b) with DVR; (c) zoomed version during voltage sag. 390

Figure 14. Phase voltage of the load. (a) Without DVR; (b) with DVR. load and the RMS voltage at the sensitive load is closely maintained at the reference value as shown in Fig. 13(b). The phase voltage at the load for without and with DVR are shown in Fig. 14(a and b). The variations of the RMS voltage at the load for a short duration of voltage sag (0.450.55 s) is tested and the results for without and with DVR are shown in Fig. 15(a and b). In Figs. 14 and 15, it is to be noted that the injected voltage by DVR mitigates the voltage sag and the load voltage is regulated constant. Extensive simulations are carried out to assess the performance of the DVR as a function of short circuit proximity. The DVR required a higher rating of DC storage device to provide appropriate levels of sag mitigation when the fault was applied at point F near sensitive load. This is due to the short electrical distance between the point of fault and the DVR coupling transformer. The designed controller performance is found to be satisfactory due to the most stringent case of the voltage sag generated by a fault occurring quite close to the sensitive load. However, these results are not reported here. It is observed that the capacity for reactive power compensation and voltage regulation of DVR depends mainly on two factors. They are the rating of the DC storage device and the characteristics of the coupling transformer. 3.2.2 Discussion The DVR is capable of injecting voltage in quadrature with the line current to ensure zero real power interaction except 391 for the losses when the DC voltage is maintained by the capacitor. The exchange of real power by DVR requires an energy source at the DC bus which can supply/absorb real power. In general, during swell conditions there is a requirement for absorption of real power and some of DVR structures may not allow this [20]. Hence, there is a limitation on absorption of real power by some of the DVR topologies and voltage swells may not be eectively compensated. It is observed, based on the case studies carried out under voltage sag, the kVA rating of the compensating VSC is found to be less for DVR (129 kVA) when compared with the D-STATCOM (272.8 kVA). Hence for the mitigation of voltage sag, the DVR is preferred over D-STATCOM. 4. Conclusions The D-STATCOM and DVR using ve-level VSC have been modeled. A SPWM-based control scheme has been designed for D-STATCOM and DVR. The eectiveness of the D-STATCOM and DVR in mitigating the voltage sag/swell has been demonstrated through PSCAD/ EMTDC simulation results. The performance of DSTATCOM has been evaluated for a wide range of operating conditions and is observed to be robust and work satisfactorily for sudden impedance variations of the network by 20% resulting in to voltage sag and voltage swell. The simulation results show that, the DVR provides excellent voltage regulation capabilities during voltage sag

Figure 15. Load RMS voltage for short duration sag. (a) Without DVR; (b) with DVR. conditions. The exchange of real power by DVR requires an energy source at the DC bus which can supply/absorb real power. In practice, during voltage swell conditions, there is a requirement for absorption of real power. There is a limitation on absorption of real power by the DVR and voltage swells may not be eectively compensated. References
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[20] A. Ghosh & G. Ledwich, Power quality enhancement using custom power devices (USA: Kluwer Academic Publishers, 2002). [21] Manitoba HVDC Research Centre, PSCAD/EMTDC: Electromagnetic transients program including dc system, www.pscad. com, 2001. [22] R.M. Mathur & R.K. Varma, Thyristor-based FACTS controllers for electrical transmission systems (New York: IEEE Press, 2002).

Biographies C. Sharmeela received her M.E. degree in Power Systems from Annamalai University, Chidambaram, India, in 2001. At present, she is pursuing her Ph.D. in Electrical Engineering, Anna University, Chennai, India. Her elds of interest include power system stability studies, voltage stability dynamics, power electronics applications to power systems, harmonics in power systems.

M.R. Mohan obtained his Doctoral degree from Anna University, Chennai, India. Presently, he is working as a Professor and Chairman, FEE, Anna University, Chennai, India. His elds of interest are optimal generation scheduling using conventional and articial intelligence techniques, unit commitment of thermal systems, power quality enhancement and service restoration in distribution networks. He is a Member of IEE, UK, Charted Engineer and Member of IE (I), Calcutta, India.

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