Mosfet Thesis

Chapter 1
Introduction
1.1 History
MetalOxideSemiconductorFieldEffectTransistor (MOSFET) is used in a vast manner
in VLSI design for high speed performance, safe operating area, unipolarity and easiness
to be used in parallel. For the study of MOSFET characteristics and operations various
models have been proposed. All these models have their own assumptions and
predictions. Due to scaling of MOSFETs, it has become very significant to consider the
effect of generated traps in SiSiO2 junction. The interface states although are not of
significance in case of thicker gate oxides but study of devices with tunneling oxide
thickness (~ 2 nm) shows that these almost negligible states have remarkable impact on
the drive current. As the oxide thickness is reduced these interfacetrapped charges
become significant gradually. In earlier times, gate oxide thickness was so large that this
phenomenon was not noticeable, but introduction of nanotechnology puts a barrier in
determining the nature of the MOSFETs with ultra thin oxides. As a result, now a day it
is a matter of importance to consider the interface states during MOS operation.
1.2 A glimpse of previous works on interface trapped charges
A theoretical treatment on the process of hotelectron emission from silicon into SiO2
was carried out by Ning [1]. He considered avalanche and nonavalanche injection
mechanism to calculate emission probability of the carriers at SiSiO2 interface. Yambae
and Miura [2] observed experimentally the flat band voltage shift due to the generation of
interface states because of electron trapping in the SiO2 film. They suggested that the
1
interface states, where electrons can be trapped, are generated due to the collisions of
electrons at the SiSiO2 interface.
Khosru and others [3] observed that holes are created by ionizing radiation that produces
new electronic states at the SiSiO2 interface resulting in the formation of interface traps.
They also found a threshold voltage shift due to the trapping of carriers inside the SiO2
layer.
In a recent approach, KueiShan Wen and others [4] showed that the generated electron
traps at the SiSiO2 interface enhance the degradation of MOSFET characteristics. To
determine the interface trapped charges in a SiSiO2 interface Guido Goreseneken and
others [5] used the charge pumping method introduced by Brugler and Jespers [6] and
represented a very keen analysis of energy distribution of interface trapped charges.
1.3 Outline of the report
In this report, we represented our work in a few chapters. These chapters are as follows:
· Chapter 2: In this chapter, the physics and operation of MOS devices
are studied in detail. Especially, the theory of MOS capacitor is
presented. The dependency of MOS capacitance on frequency and
applied voltage is also showed. A brief description on the MOSFET
operation is discussed in the end.
· Chapter 3: The physical alphapower law MOSFET model is explained
in detail in this chapter. The expressions of the model along with
compact mathematical analyses and plots of IDS vs. VGS curves and IDS
vs. VDS curves for two different devices (3.5 nm oxide and 2.2 nm oxide)
are presented. Discussing briefly about the plots, an outline of the
operation of the ultrathin oxide MOSFETs are understandable. In the end
2
portion of this chapter an analysis of the subthreshold slope of the
devices is presented.
· Chapter 4: This chapter deals with the development of the physical
alphapower law MOSFET model. The incorporation of depletion
capacitance (Cd) and interface trapped charge capacitance (Cit) shows an
amount of difference in the IDS vs. VGS and IDS vs. VDS curves for both
the devices. Respective plots in this purpose are included.
· Chapter 5: A detailed description on the location and properties of the

interface states in a MOS device is discussed here. Also, it includes a
glimpse in the Si – SiO2 interface.
· Chapter 6: This chapter deals with two types of determination process
of interface trapped charges: 1) The Charge Pumping Method or CP
Method, 2) The Capacitance Voltage Method or CV Method. Later in
this chapter an analytical study and comparison between this two
methods is presented.
3
Chapter 2
MOS Device Physics and Operations
2.1 Introduction
A field effect transistor (FET) operates as a conducting semiconductor channel with two
ohmic contacts the source and the drain – where the number of charge carriers in the
channel is controlled by a third contact – the gate. In the vertical direction, the gate
channelsubstrate structure (gate junction) can be regarded as an orthogonal twoterminal
device, which is either a MOS structure or a reversebiased rectifying device that controls
the mobile charge in the channel by capacitive coupling (field effect). Examples of FETs
based on these principles are MetalOxideSemiconductor FET (MOSFET), junction FET
(JFET), metalsemiconductor FET (MESFET), and heterostructure FET (HFETs). In all
cases, the stationary gatechannel impedance is very large at normal operating conditions.
The basic FET structure is shown schematically in figure 2.1.
Figure 2.1: Schematic illustration of a generic field effect transistor
4
The most important FET is the MOSFET. In a silicon MOSFET, the gate contact is
separated from the channel by an insulating silicon dioxide (SiO2) layer. The charge
carriers of the conducting channel constitute an inversion charge, that is, electrons in the
case of a ptype substrate (nchannel device) or holes in the case of an ntype substrate
(pchannel device), induced in the semiconductor at the siliconinsulator interface by the
voltage applied to the gate electrode. The electrons enter and exit the channel at n + source
and drain contacts in the case of an nchannel MOSFET, and at p+ contacts in the case of
a pchannel MOSFET.
MOSFETs are used both as discrete devices and as active elements in digital and analog
monolithic integrated circuits (ICs). In past decade, the device feature size of such
circuits has been scaled down into the deep submicrometer range. Presently, the 0.13mm
technology node for complementary MOSFET (CMOS) is used very large scale Ics.
(VLSIs) and, within a few years, sub0.1mm technology will be available, with a
commensurate increase in speed and in integration scale. Hundreds of millions of
transistors on a single chip are used in microprocessors and in memory ICs today.
CMOS technology combines both nchannel and pchannel MOSFETs to provide very
low power consumption along with high speed. New silicononinsulator (SOI)
technology may help achieve threedimensional integration, that is, packing of devices
into many layers with a dramatic increase in integration density. New improved device
structures and the combination of bipolar and field effect technologies (BiCMOS) may
lead to further advances, yet unforeseen. One of the rapidly growing areas of CMOS is in
analog circuits, spanning a variety of applications from audio circuits operating at the
kilohertz (kHz) range to modern wireless applications operating at gigahertz (GHz)
frequencies.
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2.2 The MOS Capacitor
To understand the MOSFET, it is convenient to analyze the MOS capacitor first, which
constitutes the important gatechannelsubstrate structure of the MOSFET. The MOS
capacitor is a two terminal semiconductor device of practical interest in its own right. As
indicated in figure 2.2, it consists of a metal contact separated from the semiconductor
substrate. Almost universally, the MOS structure utilizes doped silicon as the substrate
and its native oxide, SiO2, as the insulator. In the siliconsilicon dioxide system, the
density of surface states at the oxidesemiconductor interface is very low compared to the
typical channel carrier density in a MOSFET. Also, the insulating quality of the oxide is
quite good.
Figure 2.2: Schematic view of a MOS capacitor
We assume that the insulator layer has infinite resistance, preventing any charge carrier

transport across the dielectric layer when a bias voltage is applied between the metal and
semiconductor. Instead, the applied voltage will induce charges and counter charges in
the metal and in the interface layer of the semiconductor, similar to what is expected in
the metal plates of a conventional parallel plate capacitor. However, in the MOS
capacitor we may use the applied voltage to control the type of interface charge we
induce in the semiconductor – majority carriers, minority carriers and depletion region.
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Indeed, the ability to induce and modulate a conducting sheet of minority careers at the
semiconductor – oxide interface is the basis of the operation of the MOSFET.
2.2.1 Interface Charge
The induced interface charge in the MOS capacitor is closely linked to the shape of the

electron energy bands of the semiconductor near the interface. At zero applied voltage,
the bending of the energy bands are ideally determined by the difference in the work
functions of the metal and the semiconductor. This band bending changes with the
applied bias and the bands become flat when we apply the socalled flatband voltage
given by
V FB = (F m - F s ) / q = (F m - X s - E C + E F ) / q (2.1)
where F m and FS are the work functions of the metal and the semiconductor,
respectively, XS is the electron affinity for the semiconductor, Ec is the energy of the
conduction band edge and EF is the Fermi level at zero applied voltage. The various
energies involved are indicated in figure 2.3, where we show typical band diagrams of
MOS capacitor at zero bias and with the voltage V=VFB applied to the metal contact
relative to the semiconductoroxide interface.
At stationary conditions, no net current flows in the direction perpendicular to the
interface owing to the very high resistance of the insulator layer. Hence, the Fermi level
will remain constant inside the semiconductor, independent of the biasing conditions.
However, between the semiconductor and the metal contact, the Fermi level is shifted by
EFM – EFS = qV (see Figure 2.3(b)). Hence, we have a quasiequilibrium situation in
which the semiconductor can be treated as if in thermal equilibrium.
A MOS structure with a ptype semiconductor will enter the accumulation regime of
operation when the voltage applied between the metal and the semiconductor is more
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negative than the flatband voltage (VFB < 0 in Figure 2.3). In the opposite case, when
V > VFB, the semiconductoroxide interface first becomes depleted of holes and we enter
the socalled depletion regime.
Figure 2.3: Band diagram of MOS capacitor (a) at zero bias and (b) with an applied
voltage equal to the flatband voltage. The flat band voltage is negative in this
example.
By increasing the applied voltage, the band bending becomes so large that the energy
difference between the Fermi level and the bottom of the conduction band at the
insulatorsemiconductor interface becomes smaller than that between the Fermi level and
the top of the valance band. This is the case indicated for V = 0V in Figure 2.3 (a).
Carrier statistics tells us that the electron concentration then will exceed the hole
concentration near the interface and we enter the inversion regime. At still larger applied
voltage, we finally arrive at a significant conducting sheet of inversion charge at the
interface.
The symbol y is used to signify the potential in the semiconductor measured relative to
the potential at a position x deep inside the semiconductor. To note that y becomes
positive when the bands bend down, as in the example of a ptype semiconductor shown
in Figure 2.4.
8
Figure 2.4: Band diagram for MOS capacitor in weak inversion (j b < y s < 2j b)
from equilibrium statistics, we find that the intrinsic Fermi level Ei in the bulk
corresponds to an energy separation qjb from the actual Fermi level EF of the doped
semiconductor,
æ N a ö
j b = V th lnçç ÷÷ (2.2)
n
è i ø
where Vth is the thermal voltage, Na is the shallow acceptor density in the ptype
semiconductor and ni is the intrinsic carrier density of silicon. According to the usual
definition, strong inversion is reached when the total band bending equals 2qjb,
corresponding to the surface potential y s = 2jb. Values of the surface potential such that
0 < y s < 2jb correspond to the depletion and the weak inversion regimes, y s = 0 is the
flatband condition, and y s < 0 corresponds to the accumulation mode.
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The surface concentrations of holes and electrons are expressed in terms of the surface
potentials as follows using equilibrium statistics,
p s = N a exp (- y s V th ) (2.3)
n s = n i 2 p s = n p 0 exp (y s V th ) (2.4)
where n p 0 = n i 2 N a is the equilibrium concentration of the minority carriers (electrons) in
the bulk.
The potential distribution y (x) in the semiconductor can be determined from a solution of
the onedimensional Poisson’s equation:
d 2 y (x ) r ( x )

2
= - (2.5)
dx e s
where es is the semiconductor permittivity and the space charge density r(x) is given by
r (x ) = q (q - n - N a ) (2.6)
The positiondependent hole and electron concentrations may be expressed as
p = N a exp (- y V th ) (2.7)
n = n p 0 exp (y V th ) (2.8)
It is to be noted that, deep inside the semiconductor, we have y(a) = 0.
In general, the above equations do not have an analytical solution for y(x). However, the

following expression can be derived for the electric field Fs at the insulator
semiconductor interface, in terms of the surface potential,
10
V th æ y ö
Fs = 2 f çç s ÷÷ (2.9)
L Dp è V th ø
where the function f is defined by
n p 0
f (u ) = ± [exp (- u ) + u - 1 ] + [exp (u ) - u - 1 ] (2.10)
N a
and
e s V th
LDp = (2.11)
qN a
is called the Debye length. In (2.10), a positive sign should be chosen for a positive y s

and a negative sign corresponds to a negative y s.
Using Gauss’ law, we can relate the total charge Qs per unit area (carrier charge and
depletion charge) in the semiconductor to the surface electric field by
Qs = -e s F s (2.12)
At the flatband condition (V=VFB), the surface charge is equal to zero. In accumulation
(V < VFB ), the surface charge is positive, and in depletion and inversion (V>VFB), the
surface charge is negative. In accumulation (when y s exceeds a few times Vth) and in
strong inversion, the mobile sheet charge density is proportional to exp[y s (2 V th )] . In
depletion and weak inversion, the depletion charge is dominant and its sheet density
varies as y s . Figure 1.5 shows Qs versusy s for ptype silicon with a doping density of
10 16 cm 3 .
In order to relate the semiconductor surface potential to the applied voltage V, we have to
investigate how this voltage is divided between the insulator and the semiconductor.
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Using the condition of continuity of the electric flux density at the semiconductor
insulator interface, we find
e s Fs = e i F i (2.13)
where e i is the permittivity of the oxide layer and F s is the constant electric field in the
insulator (assuming no space charge). Hence with an insulator thickness d i , the voltage
drop across the insulator becomes F i d i . According for the flatband voltage, the applied
voltage can be written as
V = V FB + y s + e s F s c i (2.14)
where ci = e i d i is the insulator capacitance per unit area.
Figure 2.5: Normalized total semiconductor charge per unit area vs.normalized
surface potential for ptype Si with Na=10 16 /cm 3
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2.2.2 Threshold Voltage
The threshold voltage V=VT, corresponding to the onset of the strong inversion, is one of
the most important parameters characterizing metalinsulatorsemiconductor devices. As
discussed above, strong inversion occurs when the surface potential y s becomes equal to
2 j b . For this surface potential, the charge of the free carriers induced at the insulator –
semiconductor interface is still small compared to the charge in the depletion layer, which
is given by
QdT = -qN a d dT = - 4e s qN a j b (2.15)
where (4 e s j b qN a ) is the width of the depletion layer at threshold. Accordingly, the

1 2
electric field at the semiconductor –insulator interface becomes
FsT = - Q dT e s = 4qN a j b / e s (2.16)
Hence, substituting the threshold values of y s and Fs in (2.14), we obtain the following

expression for the threshold voltage:
VT = V FB + 2j b + 4 e s qN a j b c i (2.17)
Figure 2.6 shows typical calculated dependencies of VT on doping level and dielectric
thickness.
For the MOS structure shown in figure 2.2, the application of a bulk bias VB is simply
equivalent to changing the applied voltage from V to VVB . Hence, the threshold referred
to the ground potential is simply shifted by VB. However, the situation will be different in
a MOSFET where the conducting layer of mobile electrons may be maintained at some
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Figure 2.6: Dependence of MOS threshold voltage on the substrate doping level for
different thickness of the dielectric layer.
constant potential. Assuming that the inversion layer is grounded, VB biases the effective
junction between the inversion layer and the substrate, changing the amount of charge in
the depletion layer. In this case, the threshold voltage becomes
VT = V FB + 2 j b + 2 e s qN a (2 j b - V B ) c i (2.18)
Note that the threshold voltage may also be affected by socalled fast surface states at the
semiconductoroxide interface and by fixed charges in the insulator layer. However, this
is not a significant concern with modern day fabrication technology.
As discussed above, the threshold voltage separates the subthreshold regime, where the

mobile carrier charge increases exponentially with increasing applied voltage, from the
abovethreshold regime, where the mobile carrier charge is linearly dependent on the
applied voltage.
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2.2.3 MOS Capacitance
In a MOS capacitor, the metal contact and the neutral region in the doped semiconductor
substrate are separated by the insulator layer, the channel, and the depletion region.
Hence, the capacitance Cmos of the MOS structure can be represented as a series
connection of the insulator capacitance C i = S e i d i , where S is the area of the MOS
capacitor, and the capacitance of the active semiconductor layer C s,
C i C s
C mos = (2.19)
C i + C s
The semiconductor capacitance can be calculated as
dQ s
C s = S (2.20)
d y s
where Qs is the total charge per unit area in the semiconductor and y s is the surface
potential. Using (2.9) to (2.12) for Q s and performing the differentiation , we obtain
C s 0 ìï æ y s ö n p 0 é æ y s ö ù üï
C s = í1 - exp çç - ÷÷ + êexp çç ÷÷ - 1 ú ý (2.21)
2 f (y s V th ) ïî è V
th ø N
a ë è V
th ø û ïþ
here, C s 0 = S e s L Dp is the semiconductor capacitance at the flatband condition (i.e., for
y s=0) and LDp is the Debye length given by (2.11), equation (2.14) describes the
relationship between the surface and the applied bias.
The semiconductor capacitance can formally be represented as the sum of two
capacitances a depletion layer capacitance, Cd and a free carrier capacitance Cfc. Cfc
together with a series resistance RGR describes the delay caused by the
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generation/recombination mechanisms in the buildup and removal of inversion charge in
response to changes in the bias voltage. The depletion layer capacitance is given by
C d = S e s / d d (2.22)
where
2e s y s
d d = (2.23)
qN a
is the depletion layer width. In strong inversion, a change in the applied voltage will
primarily affect the minority carrier charge at the interface, owing to the strong
dependence of this charge on the surface potential. This means that the depletion width
reaches a maximum value with no significant further increase in the depletion charge.
This maximum depletion width ddT can be determined from (2.23) by applying the
threshold condition, y s= 2jb. the corresponding minimum value of the depletion
capacitance is CdT = Ses / d dT.
The free carrier contribution to the semiconductor capacitance can be formally expressed
as
Cfc = C s Cd (2.24)
As indicated, the variation in the minority carrier charge at the interface comes from the
processes of generation and recombination mechanisms, with the creation and removal of
electronhole pairs. Once an electronhole pair is generated, the majority carrier (a hole in
ptype material and an electron in ntype material) is swept from the space charge region
into the substrate by the electric field of this region. The minority carrier is swept in the
opposite direction toward semiconductorinsulator interface. The variation in the minority
carrier charge in the semiconductorinsulator interface therefore proceeds at a rate limited
by the time constants associated with the generation/recombination processes. This finite
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rate represents a delay, which may be represented electrically in terms of an RC product
consisting of the capacitance Cfc and the resistance RGR, as reflected in the equivalent
circuit of the MOS structure shown in figure 2.7. The capacitance Cfc becomes important
in the inversion regime, especially in strong inversion where the mobile charge is
important. The resistance Rs in the equivalent circuit is the series resistance of the neutral
semiconductor layer and the contacts.
Figure 2.7: Equivalent circuit of the MOS capacitor
This equivalent circuit is clearly frequencydependent. In the lowfrequency limit, we can
neglect the effects of RGR and Rs to obtain (using Cs = Cd + Cfc)
o C s C i
C mos = (2.25)
C s + C i
In strong inversion, we have Cs >> Ci, which gives
o
C mos = C i (2.26)
at low frequencies.
In the highfrequency limit, the time constant of the generation/recombination
mechanisms will be much longer than the signal period (RGRCfc >> 1/f) and Cd effectively
17
shunts the lower branch of the parallel section of the equivalent in figure 2.7. Hence, the
highfrequency, strong inversion capacitance of the equivalent circuit becomes
¥ C dT C i
C mos = (2.27)
C dT + C i
The calculated dependence of C mos on the applied voltage for different frequencies is
shown in figure 2.8. For applied voltages well below threshold, the device is in
accumulation and Cmos equals Ci. As the voltage approaches threshold, the semiconductor
passes the flatband condition where Cmos has the value CFB, and then enters the depletion
and weak inversion regimes where the depletion width increases and the capacitance
value drops steadily until it reaches the minimum value at threshold given by (2.27). The
calculated curves clearly demonstrate how the MOS capacitance in the strong inversion
¥
regime depends on the frequency, with a value of C mos at high frequencies to Ci at low
frequencies.
Figure 2.8: Calculated dependence of Cmos on the applied voltage for different
frequencies.
We note that in a MOSFET, where the highly doped source and drain regions act as
reservoirs of minority carriers for the inversion layer, the time constant RGRCfc must be
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substituted by a much smaller time constant corresponding to the time needed for
transporting carriers from these reservoirs in and out of the MOSFET gate area.
Consequently, highfrequency strong inversion MOSFET gatechannel CV
characteristics will resemble the zero frequency MOS characteristics.
Since the lowfrequency MOS capacitance in the strong inversion is close to Ci, the
induced inversion charge per unit area can be approximated by
qn s » c i (V - V T ) (2.28)
This equation serves as the basis of a simple charge control model (SCCM) allowing us
to calculate MOSFET currentvoltage characteristics in strong inversion.
From measured MOS CV characteristics, we can easily determine important parameters
of the MOS structure, including the gate insulator thickness, the semiconductor substrate
doping density, and the flatband voltage. The maximum measured capacitance C max
(capacitance Ci in figure 2.7) yields the insulator thickness
d i » S e i C max (2.29)
The minimum measured capacitance Cmin (at high frequency) allows us to find the doping
concentration in the semiconductor substrate. First, we determine the depletion
capacitance in the strong inversion regime using (2.27),
1 C min = 1 C dT + 1 C i (2.30)
From CdT we obtain the thickness of the depletion region at threshold as
d dT = S e s C dT (2.31)
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Then we calculate the doping density Na using (2.23) with y s = 2jb and (2.2) for jb. this
results in the following transcendental equation for Na:
4 e s V th æ N a ö
N a = 2
ln çç ÷÷ (2.32)
qd dT è n i ø
This equation can easily be solved by iteration or by approximate analytical techniques.
Once d i and Na have been obtained, the device capacitance CFB under flatband
conditions can be determined using Cs = C s0 ((2.21) at flatband condition) in
combination with (2.19):
C s 0 C i S e s e i

C FB = = (2.33)
C s 0 + C i e s d i + e i L Dp
The flatband voltage VFB is simply equal to the applied voltage corresponding to this
value of the device capacitance.
We note that the above characterization technique applies to ideal MOS structures.
Different nonideal effects, such as geometrical effects, nonuniform doping in the
substrate, interface states, and mobile charges in the oxide may influence the CV
characteristics of the MOS capacitor.
2.2.4 MOS Charge Control Model
Well above threshold, the charge density of the mobile carriers in the inversion layer can
be calculated using the parallel plate charge control model of (2.28). This model gives an
adequate description for the strong inversion regime of the MOS capacitor, but fails for
applied voltages near and below threshold (i.e. in the weak inversion and depletion
regimes). Several expressions have been proposed for a unified charge control model
(UCCM) that covers all the regimes of operation, including the following:
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æ n ö
V - V T = q (n s - n 0 ) c a + h V th ln çç s ÷÷ (2.34)
è n 0 ø
where, c a » c i is approximately the insulator capacitance per unit area (with a small
correction for the finite vertical extent of the inversion channel), n0 = ns(V = VT) is the

density of minority carriers per unit area at threshold, and h is the socalled subthreshold
ideality factor, also known as the subthreshold swing parameter. The ideality factor
accounts for the subthreshold division of the applied voltage between the gate insulator
and the depletion layer, and the 1/h represents the fraction of this voltage that contributes
to the interface potential. A simplified analysis gives
h = 1 + C d C i (2.35)
n 0 = hV th c a 2 q (2.36)
In the subthreshold regime, (2.34) approaches the limit
æ V - V T ö
n s = n 0 exp çç ÷÷ (2.37)
è h V
th ø
We note that (2.34) does not have an exact analytical solution for the inversion charge in
terms of the applied voltage. However, for many purposes, the following approximate
solution may be suitable:
é 1 æ V - V T öù
n s = 2 n 0 ln ê1 + exp çç ÷÷ú (2.38)
ë 2 è h V th øû
21
Figure 2.9: Comparison of various charge control expression for the MOS
capacitor.
This expression reproduces the correct limiting behaviour both in strong inversion and
the subthreshold regime, although it deviates slightly from (2.34) near threshold. The
various charge control expressions of the MOS capacitor are compared in the above
figure.
2.3 Basic MOSFET Operation
In the MOSFET, an inversion layer at the semiconductoroxide interface acts as a
conducting channel. For example, in an nchannel MOSFET, the substrate is ptype
silicon and the inversion charge consists of electrons that form a conducting channel
between the n + ohmic source and the drain contacts. At DC conditions, the depletion
regions and the neutral substrate provide isolation between devices fabricated on the
same substrate. A schematic view of the nchannel MOSFET is shown in Figure 2.10.
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As described above for the MOS capacitor, inversion charge can be induced in the
channel by applying a suitable gate voltage relative to other terminals. The onset of
strong inversion is defined in terms of a threshold voltage VT being applied to the gate
electrode relative to the other terminals. In order to assure that the induced inversion
channel extends all the way from source to drain, it is essential that the MOSFET gate
structure either overlaps slightly or aligns with the edges of these contacts (the latter is
achieved by a selfaligned process). Selfalignment is preferable since it minimizes the
parasitic gatesource and gatedrain capacitance.
Figure 2.10: Schematic view of an nchannel MOSFET with conducting channel and
depletion region
When a drainsource bias VDS is applied to an nchannel MOSFET in the abovethreshold
conducting state, electrons move in the channel inversion layer from source to drain. A
change in the gatesource voltage VGS alters the electron sheet density in the channel,
modulating the channel conductance and the device current. For VGS > VT in an n
channel device, an application of a positive VDS gives a steady voltage increase from
source to drain along the channel that causes a corresponding reduction in the local gate
channel bias VGX (here X signifies a position x within the channel). This reduction is
greatest near drain where VGX equals the gatedrain bias VGD.
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Somewhat simplistically, we may say that when VGD = VT, the channel reaches threshold
at the drain and the density of inversion charge vanishes at this point. This is the socalled
pinchoff condition, which leads to a saturation of the drain current Ids. The
corresponding drainsource voltage, VDS = VSAT , is called the saturation voltage. Since
VGD = VGS – VDS, we find that VSAT = VGS – VT .
When VDS > VSAT, the pinchedoff region near drain expands only slightly in the
direction of the source, leaving the remaining inversion channel intact. The point of
transition between the two regions, x = x p, is characterized by V XS (x p ) » V SAT , where
V XS (x p ) is the channel voltage relative to source at the transition point. Hence, the drain
current in saturation remains approximately constant, given by the voltage drop VSAT
across the part of the channel that remains in inversion. The voltage VDS – VSAT across
the pinchedoff region creates a strong electric field, which efficiently transports the
electrons from the strongly inverted region to the drain.
Typical currentvoltage characteristics of a longchannel MOSFET, where pinchoff is

the predominant saturation mechanism, are shown in the following figure.
Figure 2.11: Currentvoltage characteristics of an nchannel MOSFET with current
saturation caused by pinchoff (longchannel case)
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However, with shorter MOSFET gate lengths, typically n the submicrometer range,
velocity saturation will occur in the channel near drain at lower VDS than that causing
pinchoff. This leads to more evenly spaced saturation characteristics than those shown in
this figure, more in agreement with those observed for modern devices. Also, phenomena
such as a finite channel conductance in saturation, a drain biasinduced shift in the
threshold voltage, and an increased subthreshold current are important consequences of
shorter gate lengths.
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Chapter 3
The Physical AlphaPower Law MOSFET Model
3.1 Introduction
In 1999, the proposal of the physical alphapower law MOSFET model [8] eliminated the
drawbacks of the previously widely utilized alphapower law MOSFET model [9]. In this
regard, it included the helpful features of the low power transregional MOSFET model
[10]. The addition of the low power transregional model brings in the salient features of
operation in all the regions (subthreshold, triode and saturation). To mention that the low
power transregional model [10] was an advantageous choice for predicting performance
of future technology generations and in particular for analyzing on/off drain current
tradeoffs. Due to the complex drain current equations the involvement with the alpha
power law MOSFET model brought the physical alphapower law MOSFET model. This
model included these salient features: 1) extension into the subthreshold region of
operation, 2) the effects of vertical and lateral high field mobility degradation and
velocity saturation and 3) threshold rolloff.
3.2 Model Derivation
The physical alphapower law MOSFET model was derived by coupling the simple
empirical alphapower law MOSFET model [9] and the more complex physics based low
power transregional MOSFET model [10]. The derivation of the model started by
equating the saturation drain current of the alphapower law MOSFET model [9],
equation (3.1) and the low power transregional model [10], equation (3.2)
26
a
æ V - V T ö
I D 0 çç GS ÷÷ = I D SAT (3.1)
è V DD - V T ø
Where ID0 (3.5) is a modified drive current that includes an effective mobility dependence
on VGS. Neglecting the small weak inversion contribution and performing a three term
binomial expansion of the bulk charge terms in I D SAT , the low power transregional
model’s saturation drain current [10] was simplified as
( ) [
I D SAT » W C OX m eff V DS SAT V GS - V T - (h / 2 ) V DS SAT
L
] (3.2)
Where, (W/L) is the channel widthtolength ratio, Cox is the oxide capacitance per unit

area, meff is the effective mobility. meff depends on the gate bias voltage (VGS) as the
influence of gate bias is dominant in the expression of meff. Rather we can say for a more
accurate expression that meff depends on the transverse field, which, in turn, depends on
all terminal voltages [11]. A general expression of meff is given as follows:
m 0
m eff = (3.3)
1 + q (VGS - V T ) + q B V SB
Including the vertical [12] and lateral [13] high field degradation effects, the expression
of meff proved to be:
m0
m eff = (3.4)
[1 + q (V GS - V T )][1 + V DS / (E C L )]
SAT
And the saturation voltage is given by the following equation:
ìï 2 æ V GS - V T ö üï
V DS SAT = E C L í 1 + ç ÷ - 1 ý (3.5)
ïî E C L çè h ÷ø ïþ
27
The combination of equation (3.1) and (3.2), for VGS=VDD, obtains,
I D 0 = (W L )C OX m eff V D 0 [V DD - V T - (h 2 )V D 0 ] (3.6)
Where, V D 0 = V DS SAT (3.7)

V GS =V DD
From (3.1),
a
æ V GS - V T ö I
çç ÷÷ = D SAT (3.8)
I D 0
è V DD - V T ø
From the above equation the value of a at VGS is obtained. The expression comes out to

be,
[
æ V DS SAT V GS - V T - (h 2 )V DS SAT
ln çç
]ö÷
V D 0 [V DD - V T - (h 2 )V D 0 ] ÷
a V = è ø (3.9)
GS
æ V - V T ö
ln çç GS ÷÷
V - V
è DD T ø
The above equation expresses the parameter, a, as a function of VGS. A simplified and
accurate expression of a is determined by selecting VGS equal to the middle value
between the end points (VDD,VT ) such that VGS=(VDD+VT)/2. Substituting
VGS=(VDD+VT)/2 into equation (3.9),
1 æ 2 V [V - V - (h 2 )V D 0 ] ö

a = ln çç D 0 DD T ÷ (3.10)
ln( 2 ) è V Da [V DD - V T - hV Da ] ÷ø
Where, V Da = V DS SAT (3.11)

V GS = (V DD +V T ) / 2
28
A feature of the physical alphapower law MOSFET model describes that dependence of
carrier velocity on VGS is jointly described by ID0, (3.3)(3.6), as well as a (3.10). This
yields improved accuracy of the model for VGS near VT compared to the original alpha
power law model [8] that describes carrier velocity as a function of VGS solely through a.
Therefore, the values of a calculated by the physical alphapower law model re slightly
larger than the measured a values of the original alphapower law model [8] for short
channel MOSFETs.
For further insight into the a parameter, analyses of the long channel MOSFET with
negligible carrier velocity saturation (ECL >> VDD VT) and the short channel MOSFET
with severe carrier velocity saturation (ECL << VDD VT) are performed in the model. In
the long channel case, the saturation voltage (3.4) may be simplified by performing a two
term binomial expansion such that
V DS SAT » (1 h )(V GS - V T ) (3.12)

E C L >>V GS -V T
Substituting (3.12) into (3.10) gives
ln(4 )
a E » = 2 (3.13)
C L >> V DD -V T
ln( 2 )
Thus, for long channel MOSFETs with negligible carrier velocity saturation the exponent
a converges to the value for the classical Shockley squarelaw MOSFET model [12]. For
the short channel MOSFET with VGS sufficiently larger than VT, the saturation voltage
(3.4) may be simplified as
V DS SAT
E C L <<V GS -V T
» (2 E C L / h )(V GS - V T ) (3.14)
29
Substituting (3.14) into (3.10) gives
1 3 2
a E » ln (2 ) = 3 2 (3.15)
C L << V DD -V T
ln (2 )
Substituting (3.14) and (3.15) as well as (3.3)(3.6) into the expression for saturation
drain current (3.1) gives
I D SAT » WC OX (V GS - V T ) u sat (3.16)

E C L << V DD -V T
where u sat is the saturation velocity. Thus, for the short channel MOSFET with severe
carrier velocity saturation the drain current in the saturation region approaches a linear
dependence of VGS – VT [8].
30
3.3 Representation of the model
3.4 Simulations
We have chosen two MOS devices of ultrathin oxides: 1) a 3.5 nm device and 2) a 2.2 nm
device. For both the devices we simulated the IV characteristics plots in all the three
operating regions. We considered the 3.5 nm device as the first sample and the 2.2 nm
device as the second sample. We ran the simulations on both the devices under a common
ambient temperature which is of the value T = 20 o C (293 K).
31
3.4.1 IDS vs. VGS curve:
While determining the IDS – VGS curves we considered the constant drain to source
voltage, VDS = 50 mV.
0.1
0.01
1E3
1E4
1E5
Drain Current, I DS (A)
1E6
1E7
1E8 3.5 nm
1E9
2.2 nm
1E10
1E11 o
T = 20 C
1E12
1E13 V DS = 0.05 Volt
1E14
1E15
1E16
1E17
0.0 0.5 1.0 1.5 2.0
Gate to Source Voltage, V GS (Volt)
Figure 3.1: IDS vs. VGS curve for 3.5 nm device (hollow circle) and 2.2 nm device

(hollow up triangle)
32
3.4.2 IDS vs. VDS curve:
In case of determining the nature of the IDS – VDS curves the gate to source voltage, VGS

was kept constant for a full operating range of drain to source voltage. We have taken
four distinct values of gate to source voltage for the determination of IDS – VDS curve.
These are: 0.8 volt, 1 volt, 1.5 volt & 2volt.
3.4.2.1 IDS vs. VDS curve (VGS = 0.8 volt):
1E3
3.5 nm
2.2 nm
o
T = 20 C
1E4 V GS = 0.8 Volt
0.0 0.5 1.0 1.5 2.0
Drain to Source Voltage, V DS (Volt)
Figure 3.2: IDS vs. VDS curve for 3.5 nm device (hollow circle) and 2.2 nm device

(hollow up triangle) with 0.8volt gate bias
33
3.4.2.2 IDS vs. VDS curve (VGS = 1 volt):
0.01
3.5 nm
2.2 nm
o
T = 20 C
V GS = 1 Volt
1E3
0.0 0.5 1.0 1.5 2.0

(hollow up triangle) with 1volt gate bias
34
0.1
0.01 3.5 nm
2.2 nm
o
T = 20 C
V GS = 1.5 Volt
1E3
0.0 0.5 1.0 1.5 2.0

(hollow up triangle) with 1.5volt gate bias
35
0.1
3.5 nm
2.2 nm
o
T = 20 C
V GS = 2 Volt
0.01
0.0 0.5 1.0 1.5 2.0

(hollow up triangle) with 2volt gate bias
As we see, from the mathematical representation of the alpha powerlaw MOSFET
model, the active region current and the saturation region current in IDS vs. VDS curves
and the subthreshold region current and the active region current in the IDS vs. VGS curve
are linearly proportional to the determined oxide capacitance of the respective devices.
So, the amount of current decreases with the increase of oxide thickness as oxide
capacitance is inversely proportional to the oxide thickness.
Also, the amount of access of both the devices in the active region in case of IDS vs. VDS
curves increase with the increment of applied gate bias voltages. Similarly, the increment
36
of the gate voltage increases also increases the value of the output current IDS (See figure
3.2, 3.3, 3.4 & 3.5).
3.4.3 Subthreshold slope
From the representation of the model, we find that, subthreshold current I DS SUB depends
exponentially on gate bias voltage VGS. However, VDS has little influence once VDS
kT
exceeds a few b = . Obviously, we find a linear behaviour in the subthreshold regime
q
from figure 3.1 when we plot IDS – VGS. The slope of this line (or more precisely the
reciprocal of the slope) is known as the subthreshold slope, S, which has typical value of
~70 mV/decade at room temperature for stateoftheart MOSFETs. This means that a
change in the input VGS of 70 mV will change the output IDS by an order of magnitude.
Clearly, the smaller the value of S, the better the transistor is as a switch. A small value
of S means a small change in the input bias can modulate the output current considerably.
It can be shown that S is expressed by
dV GS dV GS kT é C + C it ù

S = = ln 10 = 2 . 3 ê1 + d ú (3.17)
d (log I DS ) d (log I DS ) q ë C ox û
The elaborated expression gives us an idea of representing the electrical equivalent circuit
of the MOSFET in terms of capacitors. The expression in brackets in the above equation
is simply the capacitor divider ratio that tells what the fraction of the applied gate bias
appears at the Si – SiO2 interface as the surface potential. Ultimately it is the surface
potential that is responsible for modulating the barrier between the source and drain, and
therefore the drain current, IDS. Hence, S is a measure of the efficacy of the gate potential
in modulating IDS. From equation (3.17) we find that S is improved by reducing the gate
oxide thickness, which is reasonable because if the gate electrode is closer to the channel,
the gate control is obviously better. The value of S is higher for heavy channel doping
(which increases the depletion capacitance) or if the silicon – oxide interface has many
37
fast interface states. In our observations, we obtained the value of S to be 59.9
mV/decade for 3.5 nm devices and 59.4 mV/decade for 2.2 nm devices. So, we find that
the decrement of the oxide thickness results in a better responsive MOSFET as a switch.
38
Chapter 4
Modification of The Physical AlphaPower Law
MOSFET Model
4.1 Introduction
The modifications of the physical alphapower law MOSFET model was obvious due to
the incorporation of the fast interface states in the model. Although, the model was quite
right in its manners to determine the MOS characteristics, the interface capacitance
determines the current response in a quite realistic manner.
4.2 Interface trapped charges
A detailed study of the MOS interface states is presented in chapter 5 in the following.

But for the convenience of our discussion we would like to have a bird’s eye view on it.
Generally, an interfacetrapped charge (also called fast interfacestate charge) exists at
the oxidesemiconductor interface. It is caused by the defects at the interface, which gives
rise to charge “traps”; these can exchange mobile carriers with the semiconductor, acting
as donors or acceptors [14]. The interface trapped charges are very negligible in effect in
case of strong inversion but if we consider the case of very thin gate oxides then we find
the trapped charges playing a vital role in case of determining MOS capacitance.
39
The energy band diagram for a MOS structure at positive voltage is as follows:
Figure 4.1: Energy band diagram of a MOS structure.
From the above figure, we see the existence of interface trapped charges in the oxide
region of the MOSFET. Usually in case of significantly thick gate oxides these charges
are not of any significance in calculating the MOS capacitance. But, as we see, when the
oxide thickness is very thin then these charges existing near to the edge of the oxide
surface strongly take part during the application of electric field [5]. So, we see that
negligence about the existence of these charges is not quite always right to determine a
better current response from a MOSFET operation.
4.3 Modification of the alphapower law model
Our study of the physical alphapower law MOSFET Model includes a modification
about MOS capacitance. In the subthreshold region, the effects of depletion capacitance
and capacitance due to interface trapped charges are not included. As a consequence
revised model is presented with the employment of interface trapped charge capacitance
40
(Cit) and depletion capacitance (Cd). The revised model includes the arrangement of
capacitances in the following manner [15]:
Figure 4.2: Arrangement of capacitances in a MOS transistor
Now it comes to a point of determining the different components of the total capacitance
(C). Oxide capacitance is varied from the flatband capacitance (CFB) to the intrinsic
value of the oxide capacitance (ei/tox). The flatband capacitance is a series combination
of Debye capacitance (Cdebye) and insulator capacitance (Ci) [15]. It is assumed that the
oxide capacitance (Cox) varies linearly with the application of the gate bias voltage (VGS).
In our proposal we determine the gate to substrate voltage (VGS) or the gate bias from
surface potentials (fs) by the following equation [14]:
VGS = V FB + f s + g f s + f t exp((f s - 2 f F ) / f t ) (4.1)
Depletion capacitance (Cd) is determined by calculating depletion width (Wm) that is
directly proportional to the square root of the surface potential (fs) [3]:
1
æ 2 e f ö 2 e
Wm = çç s s ÷÷ ; C d = s (4.2)
è qN a ø W m
41
Then we analyzed the interface trap distribution and measured its value to be equal to
65.771 nF (See Chapter 5 for detail). Thus we take interface trapped charge capacitance,
Cit = 65.771 nF. Then following the capacitor arrangement of figure 4.2 we measured the
equivalent MOS capacitance (Cmos). The calculated value of the Cmos is then used in the
expressions of the various expressions of physical alphapower law MOSFET model in
places of Cox. And thus we obtained a quite remarkable deviation in the measured values
of the drain current, IDS.
4.4 Revised simulations
We used the same devices use in chapter 3 (3.5 nm oxide and 2.2 nm oxide) with similar
ambient conditions and performed the revised expressions for the operations and then
compared the obtained results with that obtained through the simulations of physical
alphapower law MOSFET model.
42
4.4.1 IDS vs. VGS curve:
a) For 3.5 nm device
0.01
1E3
1E4
1E5
1E6
1E7
1E8
1E9
1E10 Alpha Model
1E11 Revised Model
1E12 o
T = 20 C
1E13
V DS = 50 mV
1E14
1E15 t OX = 3.5 nm
1E16
1E17
0.0 0.5 1.0 1.5 2.0
Figure 4.3: IDS vs. VGS curve for 3.5 nm device
43
b) For 2.2 nm device
0.01
1E3
1E4
1E5
1E6
1E7
1E8
1E9
Alpha Model
1E10 Revised Model
1E11
o
1E12 T = 20 C
1E13
V DS = 50 mV
1E14
1E15
t OX = 2.2 nm
1E16
1E17
0.0 0.5 1.0 1.5 2.0
Figure 4.4: IDS vs. VGS curve for 2.2 nm device
Studying the IDS vs. VGS curves, we find a good impact of the newly engaged trapped
charges and depletion capacitance. For both of the specimens, the proposed model shows
lower values at the initial points of the subthreshold region. In the initial region, physical
alphapower law MOSFET model shows a quite constant rise in the values of drain
current, where the proposed model shows a slightly curved rise in the values of drain
current. This may be taken as an effect of the appearance of the newly introduced
capacitances that are varied with the applied gate bias. These plots show that the
subthreshold slope for proposed model shows a higher value (63.5 mV/decade) than the
alphapower law MOSFET model (59.9 mV/decade) in case of 3.5 nm oxide. Similarly,
44
revised model shows a higher value (62.4 mV/decade) in case of 2.2 nm devices than the
previous model (59.4 mV/decade).
4.4.2 IDS vs. VDS curve:
The IDS vs. VDS curves also show a slightly reduced amount of current when devices are

operated under fixed gate bias voltage, VGS.
1E3
Alpha Model
Revised Model
1E4
o
T = 20 C
V GS = 0.8 V
t OX = 3.5 nm
1E5
0.0 0.5 1.0 1.5 2.0
Figure 4.5: IDS vs. VDS curve for 3.5 nm device (VGS = 0.8 volt)
45
1E3
Alpha Model
Revised Model
1E4
o
T = 20 C
V GS = 0.8 V
1E5 t OX = 2.2 nm
0.0 0.5 1.0 1.5 2.0
46
0.01
Alpha Model
Revised Model
1E3
o
T = 20 C
V GS = 1V
t OX = 3.5 nm
1E4
0.0 0.5 1.0 1.5 2.0
Figure 4.7: IDS vs. VDS curve for 3.5 nm device (VGS = 1 volt)
47
0.01
Alpha Model
Revised Model
1E3
o
T = 20 C
V GS = 1V
t OX = 2.2 nm
1E4
0.0 0.5 1.0 1.5 2.0
48
Alpha Model
0.01 Revised Model
o
T = 20 C
1E3
V GS = 1.5 V
t OX = 3.5 nm
1E4
0.0 0.5 1.0 1.5 2.0
49
0.1
Alpha Model
0.01 Revised Model
o
T = 20 C
1E3
V GS = 1.5 V
t OX = 2.2 nm
1E4
0.0 0.5 1.0 1.5 2.0
50
0.1
Alpha Model
Revised Model
0.01
o
T = 20 C
V GS = 2 V
1E3
t OX = 3.5 nm
1E4
0.0 0.5 1.0 1.5 2.0
51
0.1
Alpha Model
Revised Model
0.01
o
1E3 T = 20 C
V GS = 2 V
t OX = 2.2 nm
0.0 0.5 1.0 1.5 2.0
Al l the above IDS vs. VDS curves show a good adjustment with the calculated capacitance

for the MOS devices model. As we have proceeded with the combination of the
capacitances, we obtained a decrement by an order of 10 in the value of the total
capacitance to that of the capacitance used in the alphapower law MOSFET model. All
the plots here show same amount of decrement in drain current value than that of the
alpha model.
52
Chapter 5
Interface States in MOSFETs
5.1 Introduction
The SiSiO2 interface is the only known interface that is good enough to enable operation
of MOSFETs to industrial standards. Thus, the properties of silicon dioxide are
fundamental to the success of silicon integrated circuit technologies [16].
5.2 Properties of SiSiO2 interface
Although the oxide is not a crystal, the silicon and oxygen atoms are packed in an orderly
manner, each silicon atom is bonded to four oxygen atoms and each oxygen atom is
bonded to two silicon atoms [16].
As the average distance between the oxygen atoms is larger than the average distance
between the silicon atoms in the silicon, this means that some of the interface atoms from
the silicon will inevitably miss oxygen atoms to create SiO bonds. This is also known as
dangling bond [16].
Atoms from the silicon that remain bonded only to three silicon atoms with the fourth
bond unsaturated, represents interface defects. The energy levels associated with the
fourth unsaturated bond of the trivalent silicon atoms do not appear in the conduction or
the valance band, rather in the silicon energy band gap [16].
53
Every trivalent silicon atom introduces a pair of energy levels; one can be occupied by an
electron (acceptor type) and the other can be occupied by a hole (donor type) [17].
Electrons and holes that appear on these levels cannot move freely as there is a relatively
large distance between the neighbouring interfacial trivalent silicon atoms (these levels
are localized and isolated from each other) [16, 17].
As these levels can effectively trap the mobile electrons and holes (from the conduction
and valence bands respectively), these are called interface states. Impurity atoms and
groups (such as H, OH and N) can be bonded to the unsaturated bonds of the interfacial
trivalent silicon atoms, which result in a shift of the corresponding energy levels into the
conduction and valence band. Although this process effectively neutralizes the interface
states, it is not possible to enforce such a saturation of all the interfacial trivalent atoms,
which means that the density of the interface states can never be reduces to zero [17].
5.3 Properties of interface states
Generally there are two types of interface states, the acceptor type and the donor type. An
acceptor type interface state is electrically neutral when it is empty and negatively
charged when filled with an electron [16, 18].
A donor type interface state is electrically neutral when it is filled with electron and
positively charged when empty [18].
Besides being donor or acceptor, a particular interface state is also characterized by
1) Its precise energy level in the bandgap (eg: eV from the valence band edge)
2) Its spatial location (eg: distance from the drain)
3) Its density (eg: number of states per cm 2 for discrete states)
In MOSFETs, these interface states are also caused by hot carrier impacting on the
surface. Interface states are known to cause degradation in device parameters such as
54
transconductance, carrier mobility and threshold voltage and generally reduce device
reliability and lifetime [17, 18 and 19].
5.4 Location of interface traps
Figure 5.1: Location of Interface States in MOSFETs
Interface states are located at the SiSiO2 layer which separates the gate contact from the
conducting channel, which is underneath the gate and between the source and drain
region.
5.5 Energy distribution of the interface states
The net charge in the interface states is a function of the position of the Fermi level in the
bandgap [18].
The energy or band gap of silicon is 1.12 eV and generally, acceptor states exist in the
upper half of the bandgap and donor states exist in the lower half of the bandgap [18].
55
An acceptor type interface state is neutral if the Fermi level is below the state and
becomes negatively charged if the Fermi level is above the state [18].
A donor type interface state is neutral if the Fermi level is above the state and becomes
positively charged is the Fermi level is below the state [18].
According to the journal by Duval, by using hightemperature conductance spectroscopy,
the Fermi level of the acceptor type interface states was found to be 0.4 eV below the
conduction band of the silicon, while the donor type interface states is 0.38 eV above the
valence band [20].
Figure 5.2: Energy distribution of the interface states [20]
56
5.6 Changes in Occupancy and Charge State with Gate Bias
This section will illustrate the change in occupancy and charge state with different gate

bias voltage. For this section we apply a small DrainSource Voltage (VDS) of 0.1 volt
and ground the source terminal.
5.6.1 Accumulation
When the gate voltage, VG is less than zero, the MOSFET is said to operate in the
Accumulation mode. Holes are drawn to the SiSiO2 interface and no electron flows from
source to drain [8].
Donor type interface states that are above Fermi level of the silicon, EFS, will be empty of
electrons and become positively charged, while those that are below E FS will be filled
with electrons and be neutral [18].
Acceptor type interface states will be above EFS and be empty of electrons thus being
neutral [18].
Figure 5.3: Energyband diagram in a ptype semiconductor showing the charge
trapped in the interface states when the MOSFET gate bias is VG < 0 [18]
57
5.6.2 Depletion
When the gate voltage, VG, is slightly more than zero, this causes a net negative charge at
the surface of the semiconductor due to the depletion of holes from the region near the
surface leaving behind uncompensated ionized acceptors [8]. The MOSFET is said to
operate in the depletion mode.
Donor type interface states will be below E FS and will be filled with electrons and be
neutral. Acceptor type interface states will be above EFS and be empty of electrons thus
being neutral [18].
trapped in the interface states when the MOSFET gate bias is VG > 0 [18]
5.6.3 Inversion
When the gate voltage, VG, is further increased, the semiconductor surface is inverted
from ptype to ntype. The MOSFET is said to operate in the Inversion mode [8].
Donor type interface states will be below E FS and will be filled with electrons and be
neutral. Acceptor type interface states that are below EFS will be filled with electrons and
become negatively charged. The acceptor type interface states that are above EFS will still
be empty of electrons and remain neutral [18].
58
trapped in the interface states when the MOSFET gate bias is VG >> 0 [18]
5.7 Relationship between Gate Leakage Current and Interface States
Gate leakage current had not been a major concern in the past as the amount is small and
insignificant. However, it increases in integration density of the Integrated Circuits and
reduction of size of the MOSFETs makes leakage current associated to the interface
states to be significant [21].
Reduction in transistor size entails very important electric field in the transistor channel.
This caused injection of hot carriers in the gate oxide and creates defects in the SiSiO2
interface (interface states). The defects I the SiSiO2 interface in turn cause leakage
current in the gate [19, 21].
This gate current is responsible for the degradation in device operating characteristics
with time. This “reliability” issue is of considerably importance as the lifetime of
electronic parts has to be guaranteed [19, 21].
59
5.7.1 Gate Current, IG
Based on the lucky electron model, electrons acquire enough energy from the electric
field in the channel to surmount the SiSiO2 barrier. Once the required energy to
surmount the barrier has been obtained the electrons are redirected towards the SiSiO2
interface by some from of phonon scattering [17, 21].
These electrons, which surmount the SiSiO2 barrier, are injected into the oxide causing
gate current, IG [21].
5.8 Fixed Oxide charge (Qf, Nf)
Fixed Charge is a positive charge in the oxide layer less than 2nm from the SiSiO2
interface. This charge is not in electrical communication with underlying charge. It is also
assumed to be unchanged by gate bias [22]. Typically, a value of 1.82x10 10 eV 1 cm 2 is
representative for the interface charge found in ultrathin oxide silicon MOS devices.
60
Chapter 6
Determination of Interface Trapped Charges in
Ultrathin Oxide MOSFETs
6.1 Introduction
Traps at the SiSiO2 interface play an important role in determining the threshold voltage,
inversionlayer mobility and lowfrequency noise of MOSFETs. Proper device modeling
requires the knowledge of the density of interface states throughout the bandgap.
In MOSFETs, interface traps have been characterized in three ways:
1) As an average value over both the surface energy bandgap and
channel length, Nit (cm 2 ) [23, 5]
2) As an average over the bandgap, but not channel length,
Nit(x) (cm 2 ) [5]
3) As an average over channel length, but not surface potential energy
in the bandgap, Dit(y) (eV 1 cm 2 ) [24, 25 and 26]
Usually two methods are widely in use as deterministic tools for interface trapped
charges. These are:
1) Charge Pumping or CP Method
2) CapacitanceVoltage or CV Method
To mention that in place of using CV method, we have employed an improved version
of lowfrequency CV method.
61
This chapter deals with different experiments run on different ultrathin oxide MOSFETs
with the above processes.
6.2 Charge Pumping or CP Method
In 1969, Brugler and Jespers [6] presented the idea of charge pumping in MOS devices

and thus it became quite helpful day by day and this process is still used in some
modified [27, 28] versions to determine the interface state density, interface trap capture
cross sections etc. In the charge pumping technique, a pulse is applied to the gate of the
MOSFET which alternatively fills the traps with electrons and holes, thereby causing a
recombination current (Icp) to flow in the substrate. If we further discuss the basic
experiment of CP method the following setup would be quite helpful.
Figure 6.1: Basic MOS Charge Pumping Experiment
In this experiment, the substrate current of a MOS transistor is smoothed by a capacitor
and is fed to a dc ammeter. Source and drain are shorted and reverse biased (VR < 0). In
the absence of any gate pulses, the ammeter simply indicated the junction’s negative
leakage currents. When the ntype substrate is periodically inverted by negative gate
62
pulses of width T S, the current reverses polarity and becomes positive. It is also observed
that its magnitude increases with frequency.
1.20E05
1.00E05
8.00E06
6.00E06
4.00E06
2.00E06
0.00E+00
0 2000000 4000000 6000000 8000000 10000000 12000000
Figure 6.2: DC substrate current (IB in Yaxis) in A vs.
Gate pulse frequency (f in Xaxis) in Hz
This linearity is clearly indicative of a “Charge Pumping” action whereby a fixed charge
is measured at each gate pulse. Since no DC component of the measured magnitude can
flow through the oxide, this charge must be injected across the junctions. A current of 1.3
nA is measured at a 1kHz frequency, so we have obtained the record of the amount of
charge stored to be 1.3 pC per pulse. Interesting to note that this current is able to flow in
the forward direction, opposite to the leakages even if the junctions are reverse biased. So
we can say that at this situation, power is being transferred from the pulse source to the
battery. A study of the gate leakage current shows that the ratio of the leakage currents
from two individual devices with different amount of gate areas is roughly equal to the
ratio of their respective gate areas.
Coming to the description of the basic experiment, the “pumped current” phenomenon is
related to the charge stored under the gate electrode at each cycle. This is underlined by
the fact that the current is a linear function of the frequency (Fig: 6.2) and also by the fact
63
that this current is roughly proportional to the gate area. The phenomenon may be
interpreted as a loss of a fraction of the total charge stored under the gate which
recombines with majority carriers of the substrate at the end of each cycle. To see widely,
the sudden application of a gate voltage producing inversion generally results in a
situation of nonequilibrium. In the absence of a junction and without illumination the
required minority carriers may only come from the following various sources:
1. Surface generation
2. Generation in the depleted region
3. Diffusion in the bulk within a diffusion length from the
borderline of the depleted region, followed by a sweep
across the depleted region.
It is evident that after sudden application of a dc voltage to the gate, a nonequilibrium
situation occurs in which no inversion layer at all exists but only a depletion layer
extending far beyond its steady state width. Then, with the increase of time the various
sources of minority carriers listed above contribute to the formation of the inversion
layer, while the depletion region reduces in width.
If there is a junction present it is easy to understand that the transient behaviour of a MOS
device will be quite different from that described above, since the opposite conductivity
region provides a fourth source of minority carriers for the substrate inversion layer.
When a negative gate voltage is applied, the potential barrier across the junction will be
reduced under its equilibrium value for a very short time according to the considerations
developed above, and this will allow a large flow of free carriers from the p+ region to
the n region in order to restore equilibrium. The inversion layer can now build up fast and
it seems a reasonable assumption to consider that the contribution of the substrate to the
inversion layer may be completely neglected. This is the situation in MOS transistor
structures, where the gate area is populated by carriers drawn from the source and the
drain.
64
When the gate pulse is removed there is evidence that the inversion layer disappears in
the same manner as it was created. As long as the field applied to the semiconductor is
large, the carriers flow back to the region they came from through the contact provided
by the p+ region (Fig: 6.1). Progressively, the boundary between the p+ and the inverted
n regions again gets the characteristics of a junction. A minority carrier, however,
continue to flow back to the p+ region until a new and opposite situation of non
equilibrium occurs that sweeps the minority carriers finding themselves within a
diffusion length from the transition across the slightly reverse biased junction. Before
reaching the final steadystate conditions, some of the excess minority carriers are lost in
the substrate where they recombine with majority carriers, giving rise to the “pumped
current”.
So as an essence of the charge pumping methods, we can say, when the gate pulse is
applied, charge is drawn into the inversion layer from the transistor source and drain
regions, and when the gate pulse is removed, some of the charge recombines with the
majority carriers in the substrate.
6.2.1 Determination of interface state distribution using CP method
The briefly discussed method of CP in the previous section was proposed by Brugler and
Jespers [6] who have suggested the determination of interface state distribution from the
rising edge of the current vs. gate voltage characteristics, using the surface potential vs.
gate voltage dependence. But Elliot [29] proved this process to be defective as during the
rise of this characteristic, the potential barrier between source and drain and the substrate
prevents the carriers from flowing into the channel to fill the empty states. He suggested
using the rising edge of his current vs. gate pulse base level I order to obtain the surface
state distribution. This includes the dependence of surface potential on gate voltage
which is to be obtained by low frequency CV method. However, in view of the emission
phenomenon, this method by Elliot is equally invalid, for the same reasons as those
mentioned earlier. Indeed, as long as the channel remains in the depletion region, the
majority carriers of the substrate cannot recombine with the trapped carriers in the
65
surface states because of the potential barrier between the substrate and the surface. Only
when the surface potential reaches the flatband condition will trapping occur and the
filled states can recombine with holes. Thos means that the rising edge of the current vs.
gate pulse base level only gives information in a very small region of a few kiloteslas
around the flatband position, and not over the whole range from flatband to inversion.
Now taking the emission process in account we can obtain the surface state distribution
over a large part of the forbidden energy gap by doing a simple experiment and without
needing the dependence of surface potential on gate voltage.
When applying square pulses with variable fall times while keeping the rise time
constant, the scanning of the energy range in the upper half of the bandgap between
conduction band and midgap. On the other hand, when varying the rise time while
keeping the fall time constant, the energy states in the lower half of the bandgap are also
scanned. The charge which recombines during each cycle can be written as
E 2
Q ss = qA G ò D it (E )dE (6.1)

E 1
where E 1 and E2 are the boundaries of the energy range which is scanned and Dit(E) is the

interface state density at energy E. the derivative of Qss with respect to the fall time ti of
the gate pulse is given by
dQ ss é dE dE ù

= qA G ê D it (E 2 ) 2 - D it (E 1 ) 1 ú (6.2)
dt i ë dt i dt i û
When keeping the rise time constant, for example, while changing the fall time, it is
obtained
dQ ss dE
= qA G D it (E 2 ) 2 (6.3)
dt f dt f
66
Since E1 is dependent of fall time.
According to the simple theory of emission of carriers from surface states, the following
expressions can be derived by using a Taylor series expansion of the exponent time
dependence term in [30, equation (31)]
( (E i - E F , inv ) / kT

E em , e - E i = -kT ln u th s n n i t em , e + e ) (6.4)
and
(
E em , h - E i = -kT ln u th s p n i t em , h + e
(E F , acc - E i ) / kT
) (6.5)
where tem,e and tem,h are the times of nonsteadystate emission for electrons and holes,
respectively, and the exponential terms are introduced to account for the case when the
emission levels are situated closer to the band edges than the quasiFermi levels. Now,
according to equation (6.4) E2 can be written as
é V FB - V T ù
E 2 = E i - kT ln êu th s n n i t f ú (6.6)
êë DV G úû
V FB - V T
where, t em , e = t f (6.7)
DV G
dE 2 kT
and so, = - (6.8)
dt f t f
Therefore, according to equation (6.3), while taking into account equation (6.8), Dit(E2)

can be found from
t f dQ ss
Dit (E 2 ) = - (6.9)
qA G kT dt f
67
Since, Qss=Icp/f, Dit(E 2) is given by,
t f dI cp
Dit (E 2 ) = - (6.10)
qA G kTf dt f
By keeping the fall time of the gate pulse constant and changing the rise time, in a similar
manner we obtain,
t r dI cp
Dit (E 1 ) = - (6.11)
qA G kTf dt r
By measuring the charge pumping current with variable fall and rise times consecutively,
the energy distribution of the surface states in a large part of the forbidden energy gap can
be easily obtained.
Now it’s our destination to account for the charge pumping current, Icp. Considering all

the variables we find that charge pumping current basically varies according to the shape
of the gate pulse. From calculation we find that for square and saw tooth shaped pulses,
the expression for the charge pumping current comes out to be as follows respectively:
é æ V - V öù
( )
I cp = 2q D it f . A G . kT êln u th n i s n s p + ln çç FB T t f : t r ÷÷ ú (6.12)
ëê è DV G ø ûú
é æ V FB - V T öù
( )
I cp = 2 q D it f . A G . kT êln u th n i s n s p + ln ç
ç DV
a (1 - a ) ÷÷ú (6.13)
ëê è G øûú
These expressions have been verified for an nchannel device. It can be done for p
channel MOSFETs.
68
To mention that sn and sp, the capture cross sections for electrons and holes respectively,
are energy independent, which is probably not correct. It is observed that around the
middle of the forbidden gap, these capture cross sections are almost energy independent
and therefore the obtained energy dependent Dit is reliable in this region. As an example
of the discussed model above, the following figure shows the distribution of interface
states obtained in case of an nchannel device (on the conduction band side):
1E11
D it [cm eV ]
1
1E10
2
1E9
0.4 0.3 0.2 0.1 0.0 0.1 0.2 0.3 0.4
Energy (eV)
Fig 6.3: Energy distribution of interface trapped charge densities
The above distribution is obtained using 1 KHz frequency and at 20 o C (293 K). Our
studies also revealed that by decreasing frequency one could measure closer towards
bandgap because maximum fall and rise time increase. By increasing the temperature,
deeper levels can also be reached because of the temperature dependence of the emission
process.
69
6.3 Low Frequency CapacitanceVoltage (LFCV) Method
An improved version of the lowfrequency Capacitance–Voltage (LFCV) method [31,
32] for MOS interface trap extraction is discussed here. A robust procedure is employed
to determine the integration constant in the calculation of surface potential, while an
accurate physical model is used to obtain a theoretical CV curve, properly accounting for
quantization effects. The technique represents a substantial advance over the
conventional LFCV and highlow frequency methods for fast and reliable
characterization of MOS interface traps.
The LFCV technique of two steps [31, 32]. First, the surface potential y s, defined as the
potential drop between the substrate and the SiSiO2 interface, is obtained by integration
of the gate capacitance, that is
V
1 G
y s (V G ) = y + (V G - V ) -
0 0
C g , tot (V G ' ) dV G ' (6.14)
C ox V ò0
s G
G
Where VG is the gate voltage, Cg.tot is the total lowfrequency capacitance measured at the

gate and C ox is the oxide capacitance. After the y s (VG ) has been determined, the
interfacetrap capacitance, Cit, can be obtained from a splitCV measurement [32] as
C gc C ox
C it = - C inv (6.15)
C ox - C g , tot
Where Cinv is the inversionlayer capacitance, defined as the derivative of the inversion

charge with respect to the surface potential and Cgc is the gatechannel capacitance.
The conventional LFCV model suffers in practice from several limitations. Fringe effects
and overlap capacitances can be an important source of error. Also, most practical
70
devices exhibit polysilicon gate depletion, with an associated voltage drop inside the gate.
To account for these effects, (6.14) must be replaced by
V
1 G
y s (V G ) = y s 0 + (V G - V G 0 ) - ò (C g , tot -C par )dV G ' - (V poly - V poly
0
) (6.16)
C ox V 0
G
The parasitic capacitance, Cpar, in equation (6.16) if often markedly nonlinear, therefore

the improvement is partial unless Cpar is accurately measured or computed for all bias
points. Also, the correction for the polysilicon voltage dropVpoly (typically 100200 mV
from accumulation to inversion) cannot always be very accurate, since in practice only an
effective doping concentration inside the polysilicon can be measured [33]. We finally
noted that the error due to the neglect of the polysilicon series capacitance in (6.15) is of
the order of a few percent at most, since in the near–threshold regime the polysilicon
depletion is still weak and the series capacitance is much higher than the oxide
capacitance.
The calculation of y s requires the precise knowledge of the surface potential y s 0 at some

gate voltage VG 0 . Usually, a bias point in strong inversion or accumulation is used, where
the surface potential is known with good accuracy [31, 34 and 35]. As an alternative, the
flatband voltage [35] or the point where the surface becomes intrinsic [32] may be used.
However, it is clear from (6.16) that the larger is the difference between VG and VG 0 , the
larger is the effect of Vpoly and Cpar. Fro most practical purposes, only traps in the
minoritycarrier side of the bandgap are of interest (i.e., for VG very close to inversion).
These considerations, along with the wellknown difficulties in the accurate
determination of the flatband voltage, discourage the use of a reference voltage VG 0 , the
conventional method is till affected by an important inaccuracy, due to channel
quantization. In fact, heavy doping of the substrate leads to a narrowing of the potential
well at the silicon/oxide interface and to a splitting of the electron states. With current
values of substrate doping of the order of 10 17 10 18 cm 3 , an error of 50100 mV on y s 0 is
made if the classical model is assumed [37], affecting (6.16) directly.
71
For the above reasons, the modifications of conventional LFCV model were done in two
respects. First, the surface potential and inversion capacitance have been obtained from a
self consistent solution of the coupled Schrodinger and Poisson equations [38], thus
accounting for quantization effects. The simulation also includes the effect of gate
polysilicon depletion, allowing the direct estimation of Vpoly from the numerical
simulation. The doping concentration of the polysilicon is determined from an
experimental technique such as that of [33], while the oxide thickness is obtained by
fitting the theoretical curve to the experimental data in the strong inversion region. This
procedure is more accurate than approximating the oxide capacitance with the measured
capacitance in strong inversion or accumulation, since the series capacitances of the gate
and substrate are also taken into account.
The second modification of the LFCV method regards the determination of the
integration constant in (6.16). As discussed above, to reduce the error to a minimum, a
reference voltage VG 0 close to threshold must be used. Lets observe the following figure:
Figure 6.4: Crosses: measured gate capacitances, Cgc. Solid line: simulated
capacitance. Dash – dot line: position of the Fermi level with respect to the
conduction band edge, from the numerical simulation
72
The previous figure compares the experimental gatechannel capacitance Cgc (crosses)
with the theoretical result (solid line), for a psubstrate MOS capacitor with channel
doping 3.8 X 10 10 cm 3 and a 12nm oxide. The npolysilicon gate doping was estimated
as 4 X 10 19 cm 3 . The steep rising edge between 1.0 and 1.3 V corresponding to the onset
of strong inversion can be used as a common reference for the theoretical and
experimental curves. So we have assumed that the surface potential is the same for the
two curves when Cgc reaches a fixed fraction of g of the oxide capacitance Cox. This
assumption is valid with excellent accuracy if the trap capacitance is smaller than Cox,
which is certainly the case for devicegrade oxides.
1E12
D it (states cm 2 eV 1 )
1E11
1E10
0.5 0.4 0.3 0.2 0.1
E E C (eV)
Figure 6.5: Solid line: density of interface states obtained from the improved LFCV
method, shown as a function of energy with respect to the conduction bandedge EC.
Star line: density of interface states, also accounting for interfacial nonuniformities.
Crosses: result obtained with the improved method, when an intentional error of
10% is introduced in the doping concentration.
73
The solid line in the above figure shows the experimental interface state density extracted
from the data of fig. 6.4, using (6.14) and (6.15) with the improved method for the
calculation of the integration constant, y s 0 . For all the results of fig. 6.5 and the following
fig. 6.6, Cpar was approximated by a constant value.
1E12
D it (states cm 2 eV 1 )
1E11
1E10
0.50 0.45 0.40 0.35 0.30 0.25 0.20
E E C (eV)
Fig 6.6: Solid line: result obtained from the improved LFCV method (same as the

solid line in fig. 6.5). Up triangle: LFCV result not including polysilicon voltage
drop, and using a conventional calculation of the surface potential. (O): Not
including poly voltage drop, but with the improved method for computing y s. (e):
LFCV result obtained from the improved method for the calculation of y s, but
without accounting the effects of quantum effects.
At the measurement frequency 1 KHz, assuming a capture cross section of 10 15 cm 2 , the
method can detect electron traps in the upper half of the bandgap, starting about 0.45 eV
below the conduction band. The upper limit of validity is given by the point were the
74
inversion capacitance Cinv becomes comparable with Cit [12], which is around VG=0.9 V
for the simulated curve of fig. 6.4. The figure also shows on the right hand axis the
position of the Fermi level, as obtained from numerical simulation. At a gate voltage of
0.9 V the Fermi level lies about 0.2 eV below the conduction band. Above this energy,
the extracted value of Dit can be affected by inaccuracies in the modeling of the inversion
capacitance in (6.15). To illustrate this point the star line in fig. 6.5 shows the trap density
obtained by taking into account he effect of interfacial nonuniformities [39]. These
effects were modeled as a Gaussian fluctuation of the threshold voltage. The rms
amplitude of the fluctuation (85 mV) was obtained by an empirical fitting, assuming the
worst case (i.e. the largest fluctuation consistent with the experimental data). The
discrepancy between the two results defines the largest error that can be expected, and
confirms the good accuracy of the method over an energy range of about 300 meV.
The curve shown as crosses in fig. 6.5 was obtained by introducing an intentional error of
10% in the substrate doping concentration, still maintaining an excellent match. In fact,
the calculation based on (6.15) and (6.16) only depends on the local behavior of the
y s(VG ) curve at threshold, which is very weakly affected by changes in the doping
profile. A negligible error was also observed by introducing artificial errors in the oxide
thickness and polysilicon doping.
Fig. 6.6 compares the result of the improved LFCV method (solid line) with the results of
other techniques. The triangles represent the result of a trap extraction using the
conventional method for the surfacepotential calculation [31], neglecting the polysilicon
voltage drop in (6.16). The reference point VG 0 was taken at VG = +3V, i.e. about 2 V
above threshold. A large horizontal distortion of the trap density can be observed, mostly
due to the effect of Vpoly. For comparison, the curve shown as circles was also obtained
neglecting Vpoly, but using the improved method for the determination of y s 0 . The good
agreement with the more accurate result confirms the robustness of the technique with
respect to nonidealities of the device. The result shown in squares in fig. 6.6 was obtained
from the LFCV procedure previously described, but without accounting for channel
quantization. The neglect of the finite electron eigenenergies results in a corresponding
75
shift toward midgap, and to an overestimation of the trap density by about a factor of two.
Therefore we may conclude that while the impact of Cpar and Vpoly is largely reduced, the
modeling of quantization effects is critical to this technique.
6.4 Experimental comparison between CP and CV method:
Capacitance – Voltage (CV) and charge – pumping (CP) techniques are widely employed
for the characterization of MOS interface of interface traps [5, 32]. However, since the
test structures are different (large area capacitors for CV and smaller transistors for CP).
Over a number of experiments, performed on samples of varying doping and oxide
thickness, CV and CP measurements were found to show systematic differences.
Figure 6.7 shows typical results of the two methods when applied to the same test
structures. The samples were nMOS gateddiodes with a channel doping of 8 ´ 10 16 cm 3
o
and a 200 A dry gate oxide. The device area was 4 ´ 10 4 cm 2 with an n + contact perimeter
of 2 cm. Samples A have standard thermal oxide, while the oxide of batch B was nitrided
at N2O, 1000 o C. Figure 6.7 shows that: (a) CP gives an interface state density about 10
times higher in the direction of the midgap region, (b) the CP curves feature a weaker
energy dependence.
76
1E12
1E11
D it [cm 2 eV 1 ]
1E10
A: CP
1E9 B: CP
A: CV
B: CV
1E8
0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10
E E C [eV]
Figure 6.7: Interface state densities derived from CV and CP measurements on the
same samples. The energies are referred to the silicon conduction band edge.
The CV extractions were based on the comparison between the experimental low
frequency CV curves measured at 1 KHz, and the theoretical capacitance numerically
computed by a self consistent Schrodinger – Poisson simulator, accounting for channel
quantization and polysilicon depletion [32, 38, 40]. CP characterizations were performed
along the lines of [5], using triangular waveforms.
77
Chapter 7
Proposal and Evaluation
7.1 Discussion
A detailed study on ultrathin MOSFET structure, operation and modeling has been
performed throughout this thesis. For MOSFET modeling, a highly reliable model
(Physical alphapower law model) has been studied and modified with some necessary
changes in the expressions. The role of interface trapped charges, raised due to impurities
in MOSFETs, has been considered with high importance as their impact on ultrathin
MOS devices is very significant.
A wellorganized study of the two major processes to determine interface trapped charges
has been presented. These two processes being the Charge Pumping Technique and
Capacitance Voltage Method have also been led to a comparative analysis between them
for a set of similar samples. Their comparative studies raise a good interest.
7.2 Future scope of work
A good prospect lies in this work as it deals with the reliable approach of modeling the

ultrathin oxide MOSFETs. Further studies may lead to a set of more accurate
expressions. In many cases approximately equal values have been used and this leaves a
scope for the determination of perfect energy band distribution of interface trap charges
in ultrathin MOSFETs. Besides, we performed an analysis of energy band distribution.
78
But a study can be performed on the distribution of trapped charges along the channel
length also.
Ultrathin oxide MOSFETs are widely used today. So, a sound approach to reduce the
existence of interface trapped charges through the introduction of advanced fabrication
would make a wide scope of research in this respective sector of solid state physics.
79
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Mosfet Thesis

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Mosfet Thesis

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Chapter 1

· Chapter 5: A detailed description on the location and properties of the

We assume that the insulator layer has infinite resistance, preventing any charge carrier

The induced interface charge in the MOS capacitor is closely linked to the shape of the

V FB = (F m - F s ) / q = (F m - X s - E C + E F ) / q (2.1)

p s = N a exp (- y s V th ) (2.3)

n s = n i 2 p s = n p 0 exp (y s V th ) (2.4)

where n p 0 = n i 2 N a is the equilibrium concentration of the minority carriers (electrons) in

d 2 y (x ) r ( x )

where es is the semiconductor permittivity and the space charge density r(x) is given by

r (x ) = q (q - n - N a ) (2.6)

p = N a exp (- y V th ) (2.7)

n = n p 0 exp (y V th ) (2.8)

It is to be noted that, deep inside the semiconductor, we have y(a) = 0.

In general, the above equations do not have an analytical solution for y(x). However, the

is called the Debye length. In (2.10), a positive sign should be chosen for a positive y s

Qs = -e s F s (2.12)

e s Fs = e i F i (2.13)

where e i is the permittivity of the oxide layer and F s is the constant electric field in the

insulator (assuming no space charge). Hence with an insulator thickness d i , the voltage

V = V FB + y s + e s F s c i (2.14)

where ci = e i d i is the insulator capacitance per unit area.

QdT = -qN a d dT = - 4e s qN a j b (2.15)

where (4 e s j b qN a ) is the width of the depletion layer at threshold. Accordingly, the

FsT = - Q dT e s = 4qN a j b / e s (2.16)

Hence, substituting the threshold values of y s and Fs in (2.14), we obtain the following

VT = V FB + 2j b + 4 e s qN a j b c i (2.17)

VT = V FB + 2 j b + 2 e s qN a (2 j b - V B ) c i (2.18)

As discussed above, the threshold voltage separates the subthreshold regime, where the

here, C s 0 = S e s L Dp is the semiconductor capacitance at the flat­band condition (i.e., for

C d = S e s / d d (2.22)

Cfc = C s ­ Cd (2.24)

qn s » c i (V - V T ) (2.28)

d i » S e i C max (2.29)

1 C min = 1 C dT + 1 C i (2.30)

d dT = S e s C dT (2.31)

C s 0 C i S e s e i

correction for the finite vertical extent of the inversion channel), n0 = ns(V = VT) is the

n 0 = hV th c a 2 q (2.36)

V XS (x p ) is the channel voltage relative to source at the transition point. Hence, the drain

Typical current­voltage characteristics of a long­channel MOSFET, where pinch­off is

Where, (W/L) is the channel width­to­length ratio, Cox is the oxide capacitance per unit

I D 0 = (W L )C OX m eff V D 0 [V DD - V T - (h 2 )V D 0 ] (3.6)

Where, V D 0 = V DS SAT (3.7)

From the above equation the value of a at VGS is obtained. The expression comes out to

1 æ 2 V [V - V - (h 2 )V D 0 ] ö

Where, V Da = V DS SAT (3.11)

V DS SAT » (1 h )(V GS - V T ) (3.12)

I D SAT » WC OX (V GS - V T ) u sat (3.16)

Figure 3.1: IDS vs. VGS curve for 3.5 nm device (hollow circle) and 2.2 nm device

In case of determining the nature of the IDS – VDS curves the gate to source voltage, VGS

3.4.2.1 IDS vs. VDS curve (VGS = 0.8 volt):

0.0 0.5 1.0 1.5 2.0

Figure 3.2: IDS vs. VDS curve for 3.5 nm device (hollow circle) and 2.2 nm device

Figure 3.3: IDS vs. VDS curve for 3.5 nm device (hollow circle) and 2.2 nm device

Figure 3.4: IDS vs. VDS curve for 3.5 nm device (hollow circle) and 2.2 nm device

Figure 3.5: IDS vs. VDS curve for 3.5 nm device (hollow circle) and 2.2 nm device

dV GS dV GS kT é C + C it ù

A detailed study of the MOS interface states is presented in chapter 5 in the following.

VGS = V FB + f s + g f s + f t exp((f s - 2 f F ) / f t ) (4.1)

Figure 4.3: IDS vs. VGS curve for 3.5 nm device

Figure 4.4: IDS vs. VGS curve for 2.2 nm device

4.4.2 IDS vs. VDS curve:

here, C s 0 = S e s L Dp is the semiconductor capacitance at the flatband condition (i.e., for

Cfc = C s Cd (2.24)

Typical currentvoltage characteristics of a longchannel MOSFET, where pinchoff is

Where, (W/L) is the channel widthtolength ratio, Cox is the oxide capacitance per unit

Where VG is the gate voltage, Cg.tot is the total lowfrequency capacitance measured at the

Where Cinv is the inversionlayer capacitance, defined as the derivative of the inversion

(14) Yannis Tsividis, “The MOS Transistors,” WCB/McGrawHill, 2 nd Edition,