MOS Transistor

MOS Transistor

Professor Chris H. Kim

University of Minnesota Dept. of ECE chriskim@umn.edu www.umn.edu/~chriskim/ Source Body Gate

Drain
Kuroda, IEDM panel
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Basic Operation (1)

MOS Transistor Current Equation

Device is in cut-off region Simply, two back-to-back reverse biased pn diodes.

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Basic Operation (2)

Basic Operation (3)

With a positive gate bias, electrons are pulled toward the positive gate electrode Given a large enough bias, the electrons start to invert the surface (p n type), a conductive channel forms Threshold voltage Vt
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Current flows from drain to source with a positive drain voltage What is current in terms of Vgs, Vds, Vbs?
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MOS Current

Channel Length Modulation

Ids = 0 : cut-off Vgs< Vt Ids = eCoxW/L ((Vgs-Vt) Vds-0.5Vds2) : triode (linear) mode 0 < Vds < Vgs- Vt 2 Ids = eCoxW/(2L) (Vgs-Vt) 0 < Vgs- Vt < Vds : saturation mode
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Pinch-off depletion layer width increases as the drain voltage increases Extreme case of this is punch-through

L = Lo Vds

I ds = I dsat

Lo = I dsat (1 + Vds ) Lo Vds

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Simulation versus Model (NMOS)

Simulation versus Model (PMOS)

The square-law model doesnt match well with simulations Only fits for low Vgs, low Vds (low E-field) conditions
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Not as bad as the NMOS device Still large discrepancies at high E-field conditions
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Simulation versus Model (Ids vs. Vgs)

Velocity Saturation

Saturation current does not increase quadratically The simulated curves looks like a straight line Main reason for discrepancy: velocity saturation
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E-fields have gone up as dimensions scale Unfortunately, carrier velocity in silicon is limited Electron velocity saturates at a lower E-field than holes Mobility (e=v/E) degrades at higher E-fields Simple piecewise linear model can be used
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Velocity Saturation
v =

Velocity Saturation
Plug it into the original current equation

e E
n 1 n

E 1 + Ec = vsat for E > Ec

for E < Ec

Ec =

2vsat

[Toh, Ko, Meyer, JSSC, 8/1988]

2 W Vds 1 eCox (Vgs Vt )Vds L 2 1 + Vds I ds = Ec L CoxWvsat (Vgs Vt Vdsat )

(Vds < Vdsat ) (Vds > Vdsat )

Equate the two expressions to get

Modeled through a variable mobility n=1 for PMOS, n=2 for NMOS To get an analytical expression, lets assume n=1
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Vdsat =

(Vgs Vt ) Ec L (Vgs Vt ) + Ec L

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Simulation versus Model

700 600 500 IDS [V] 400 300 200 100 0

Unified MOS Model

unified model simulation
1.2V

linear

1.0V

vel. saturation

0.8V

0.6V

saturation
0.2

0.4V 1.2

Model incorporating velocity saturation matches fairly well with simulation

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Vdsat0.4

0.6 VDS [V]

0.8

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Unified MOS Model Equations

I ds =

Alpha Power Law

Simple empirical model for short channel MOS

W eCox (Vgs Vt ) 2L

[Sakurai and Newton, JSSC 1990]

- body effect parameter

Model presented is compact and suitable for hand analysis. Still have to keep in mind the main approximation: that VDSat is constant. But the model still works fairly well.
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Parameter is between 1 and 2 =1-1.2 for short channel devices Parameters and Vt are fitted to measured data for minimum square error fitted Vt can be different from physical Vt

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