Digital Conversiona Using FPGA

DIGITAL
CONVERSIONS
DIGITAL CONVERSION 2012
For KLNCE-ECE (2013 Batch)
This is not a compilation of Truth tables, Boolean

Expressions, and programs relentlessly copied from
world wide web..
INDEX
1. Brief Introduction. 5-6
2. Binary to BCD .................................................................................................. 7-10
a. Truth Table 7
b. Gate Level Program 8
c. Data flow 9
d. Behavioral 10
3. Binary to Gray to Binary 11-18
a. Binary To Gray. 11-14
i. Truth Table.. 11
ii. Gate Level Program 12
iii. Data flow 13
iv. Behavioral 14
b. Gray to Binary..15-17
i. Truth Table 15
iii. Data flow 17
iv. Behavioral. 18
4. BCD to Gray.. 19-22
a. Truth Table 19
b. Gate Level Program 20
c. Data flow.. 21
d. Behavioral. 22
5. BCD to Excess-3 to BCD... 23-30
a. BCD to Excess-3 23-26
i. Truth Table.. 23
iii. Data Flow Program. 25
iv. Behavioral Program 26
b. Excess-3 to BCD.. 27-30
i. Truth Table.. 27
iii. Data Flow Program. 29
iv. Behavioral Program 30
6. BIBLIOGRAPHY31
Before You Proceed..

I.
Check the comments before proceeding, it provides useful information.
II.
Unless stated (check for header comment) , in all the conversions, inputs
range from 0d to 15d i.e 0000b to 1111b.
III.
BCD wherever used means PACKED BCD.
IV.
Knowledge of K-Map reeduction, General Digital Electronic knowledge and

the knowledge of various abstraction (Gate,Data Flow, Behavioral) used in
Verilog would be HELPFULL.
V.
In all the truth tables provided, Left table represents INPUT and right
represents OUTPUT.
VI.
Check Comments before proceeding to avoid redundant doubts.
VII.
All the programs are written in VERILOG.
VIII.
All programs are tested & simulated using XILINX 9.2i.
IX.
Dyslexic Warning : due to close position of operators & operands it is highly

advised to check comment(s) to avoid dyslexic errors especially in programs
written using Data flow Abstraction.
If you have reached this far .
X.
Please READ & UNDERSTAND before your WRITE or TYPE and use of
common sense is highly advised, no offence.
A BRIEF INTRODUCTION
What is Binary ?
In laymans term, Binary means two(2), and in computer engineering parlance means, a signal
which can attain at max 2 values over a particular set time interval .It is represented digitally as
1,0 and physically +5V or 0V or any other voltage as required as long it has 2 values .
Ex:
1101b , 1111b ,0000b - 4 bit size ( 4bX)
What is BCD ?
BCD means binary coded decimal. It is method of encoding binary into decimal format. In this
coding, each binary sequence represents a decimal notation.
How to convert?
In packed BCD, each 4 bit binary sequence represents a decimal number (0-9). For binary to
BCD conversion, following example will illustrate the procedure.
Ex :
1111b
First, write down the decimal equivalent of the binary sequence using
8421 logic,
Therefore,
1111b 15d
Now, we have two decimal number (0-9), and in packed BCD each decimal is represented in 4 bit
sequence
5d 0101b
1d 0001b
Combining both we have
00010101b or 10101b
What is a Gray Code?
It is a binary sequence, in which two successive values or sequence differs only by a bit. It is also
called as reflected binary code. They are mostly used for error correction.
How to Convert?
The nth bit is kept as it is, the (n-1)th bit is added with nth bit and (n-2)th bit is added with (n1)th bit and this process is carried on till LSB is obtained.
The process of conversion is illustrated with an example below
1101b
th
th
N bit = 1, keep as it is and add (n-1) bit i.e 1 to MSB
1+1= 0
( neglect carry) 2nd bit
Now,
add 0 + 1 = 1 3rd bit
Now for last bit, add last two bit of the input
0+1=1
1011b --> OUTPUT
What is Excess -3?

Its a binary sequence obtained adding 3 (0011b), as the name indicates excess of 3.
How to convert?
It just involes adding 3 (0011b) to a binary sequence.
Ex:
0100b (4d) Input
Add 0011b (3d)
0111b (4d) Output
BINARY TO BCD
THE TRUTH TABLE
B3
B2
B1
B0
Y4
Y3
Y2
Y1
Y0
GATE LEVEL
timescale 1ns / 1ps
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE - ECE - B
// Engineer*:
Praveen Kumar K K
// Create Date:
21:44:43 02/5/2012
// Design Name:
Binary to BCD Convertor
// Module Name:
bi_bcd
// Project Name:
Digital Convertors
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
The following code is to convert 4 bit binary input to 5 bit packed BCD
// MODEL:
GATE LEVEL
// Additional Comments:
Input Range 0000b 1111b
/////////////////////// BINARY TO BCD CONVERTOR///////////////////////////////////////////////////////////////////
module bi_bcd(y,b);
output [4:0]y;
// 5 bit wide output
input [3:0]b;
// 4 bit widde input
wire a,c,d,e,f,g;
// Interconnections or nets ;
//////////////////////PRE-REQIUSITES//////////////////////////////////////////////////////////////////////////////////
not(v1,b[1]);
//This is to
not(v2,b[2]);
//have negated version of input
not(v3,b[3]);
//to heed the process of conversion
//////////////////////LOGICAL OUTPUT////////////////////////////////////////////////////////////////////////////////
//----Y0----//////////////////////////////////////////////////////////////////////////////////////////////////////////////
buf buf_1(y[0],b[0]);
// Y0 = B0
//----Y1----//////////////////////////////////////////////////////////////////////////////////////////////////////////////
and a_1(a,b[3],b[2],v1);
//
and a_2(c,v3,b[1]);
// Y1= (~B3).B2.(~B1) + (~B3).B1
or or_1(y[1],a,c);
//
//----Y2----//////////////////////////////////////////////////////////////////////////////////////////////////////////////
and a_3(d,v3,b[2]);
//
and a_4(e,b[2],b[1]);
// Y2= (~B3).B2 + B2.B1
or or_2(y[2],d,e);
//
//----Y3----//////////////////////////////////////////////////////////////////////////////////////////////////////////////
and a_5(y[3],b[3],v1,v2);
// Y3 = B3.(~B2).(~B1)
//----Y4----//////////////////////////////////////////////////////////////////////////////////////////////////////////////
and a_6(f,b[3],b[2]);
//
and a_7(g,b[3],b[1]);
// Y4 = B3.B3 + B3.B1
or or_3(y[4],f,g);
//
//////////////////////END//////////////////////////////////////////////////////////////////////////////////////////////
endmodule
DATA FLOW LEVEL

///////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE - ECE - B
// Engineer*:
Praveen Kumar K K
// Create Date:
21:44:43 02/5/2012
// Design Name:
// Module Name:
bi_bcd
// Project Name:
Digital Convertors
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
Code to convert 4 bit binary input to 5 bit packed BCD
// MODEL:
DATAFLOW LEVEL
Input Range 0000b - 1111b
////////////////////////////////////////////////////////////////////////////////////////////////////////// /////
/////////////////////// BINARY TO BCD CONVERTOR/////////////////////////////////////////////////////////
module bi_bcd_dataflow(y,b);
output [4:0]y;
input [3:0]b;
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
///////////////ASSIGNING THE LOGIC////////////////////////////////////////////////////////////////////////
assign y[0] = b[0];
// Y0 = B0
assign y[1] = (( b[3]&b[2] )&( ~b[1] ))|((~b[3])&b[1]);
// Y1= (~B3).B2.(~B1) + (~B3).B1
assign y[2] = ( (~b[3])&b[2] ) | ( b[2]&b[1] );
// Y2= (~B3).B2 + B2.B1
assign y[3] = ( b[3]& ( (~b[2])&(~b[1]) ) );
// Y3 = B3.(~B2).(~B1)
assign y[4] = ( b[3]&b[2] )|( b[3]&b[1] );
// Y4 = B3.B3 + B3.B1
/////////////////////////END/////////////////////////////////////////////////////////////////////////////////
Endmodule
BEHAVIORAL LEVEL
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE - ECE - B
// Engineer*:
Praveen Kumar K K
// Create Date:
21:44:43 02/5/2012
// Design Name:
// Module Name:
bi_bcd
// Project Name:
Digital Convertors
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
The following code is to convert 4 bit binary input to 5 bit packed BCD
// MODEL:
BEHAVIORAL LEVEL
/////////////////////// BINARY TO BCD CONVERTOR////////////////////////////////////////////////////////
module bi_bcd_behavioral(y,b);
output [4:0]y;
input [3:0]b;
reg [4:0]y;
///////////////ASSIGNING THE LOGIC////////////////////////////////////////////////////////////////////////
always@(b[3],b[2],b[1],b[0])
case({b[3],b[2],b[1],b[0]})
4'b0000:{y[4],y[3],y[2],y[1],y[0]}= 5'b00000;
4'b0001:{y[4],y[3],y[2],y[1],y[0]}= 5'b00001;
4'b0010:{y[4],y[3],y[2],y[1],y[0]}= 5'b00010;
4'b0011:{y[4],y[3],y[2],y[1],y[0]}= 5'b00011;
4'b0100:{y[4],y[3],y[2],y[1],y[0]}= 5'b00100;
4'b0101:{y[4],y[3],y[2],y[1],y[0]}= 5'b00101;
4'b0110:{y[4],y[3],y[2],y[1],y[0]}= 5'b00110;
4'b0111:{y[4],y[3],y[2],y[1],y[0]}= 5'b00111;
4'b1000:{y[4],y[3],y[2],y[1],y[0]}= 5'b01000;
4'b1001:{y[4],y[3],y[2],y[1],y[0]}= 5'b01001;
4'b1010:{y[4],y[3],y[2],y[1],y[0]}= 5'b10000;
4'b1011:{y[4],y[3],y[2],y[1],y[0]}= 5'b10001;
4'b1100:{y[4],y[3],y[2],y[1],y[0]}= 5'b10010;
4'b1101:{y[4],y[3],y[2],y[1],y[0]}= 5'b10011;
4'b1110:{y[4],y[3],y[2],y[1],y[0]}= 5'b10100;
4'b1111:{y[4],y[3],y[2],y[1],y[0]}= 5'b10101;
default : $display("input out of range");
endcase
_////////////////////////END/////////////////////////////////////////////////////////////////////////////////
endmodule
10
BINARY TO GRAY CONVERTOR

TRUTH TABLE
B3
B2
B1
B0
Y3
Y2
Y1
Y0
11
GATE LEVEL
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE - ECE - B
// Engineer:
Praveen Kumar K K
// Create Date:
00:08:02 02/7/2012
// Design Name:
Binary to Gray Convertor
// Module Name:
gatelvl_bin_to_gray
// Project Name:
Digital COnversions
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
Code forconverting binary sequence to Gray sequence
// MODEL:
GATE LEVEL
// Additional Comments: Input Range 0000b - 1111b
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
module gatelvl_bin_to_gray(y,b);
output [3:0]y;
// Y is output 4 bit wide
input [3:0]b;
// B is input 4 bits wide
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
//--Y0---///////////////////////////////////////////////////////////////////////////////////////////////////////
xor x_1(y[0],b[0],b[1]);
// Y0 = B1 (+) B0
//--Y1---///////////////////////////////////////////////////////////////////////////////////////////////////////
xor x_2(y[1],b[2],b[1]);
// Y1 = B2 (+) B1
//--Y2---///////////////////////////////////////////////////////////////////////////////////////////////////////
xor x_3(y[2],b[3],b[2]);
// Y2 = B3 (+) B2
//--Y3---///////////////////////////////////////////////////////////////////////////////////////////////////////
buf b_1(y[3],b[3]);
// Y3 = B3
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
Endmodule
12
DATAFLOW LEVEL
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE - ECE - B
// Engineer:
Praveen Kumar K K
// Create Date:
00:08:02 02/7/2012
// Design Name:
// Module Name:
dataflow_bin_to_gray
// Project Name:
Digital Conversions
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
This code is for converting binary sequence to Gray sequence
// MODEL:
DATA FLOW LEVEL
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
module dataflow_bin_gray(y,b);
output [3:0]y;
input [3:0]b;
///////////////////ASSIGNING THE LOGIC////////////////////////////////////////////////////////////////////
assign y[0] = b[1]^b[0];
//Y0 = B1 (+) B0
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[1] = b[2]^b[1];
//Y1 = B2 (+) B1
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[2] = b[3]^b[2];
//Y2 = B3 (+) B2
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[3] = b[3];
//Y3 = B3
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
Endmodule
13
BEHAVIORAL MODEL
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE - ECE - B
// Engineer:
Praveen Kumar K K
// Create Date:
00:08:02 02/7/2012
// Design Name:
// Module Name:
behavioral_bin_to_gray
// Project Name:
Digital Conversions
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
Code is for converting binary sequence to Gray sequence
// MODEL:
BEHAVIORAL LEVEL
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
module behavioral_bin_to_gray(y,b);
output [3:0]y;
input [3:0]b;
reg [3:0]y;
// storing output momentarily
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
always@(b[3],b[2],b[1],b[0])
case({b[3],b[2],b[1],b[0]})
4'b0000:{y[3],y[2],y[1],y[0]}= 4'b0000;
4'b0001:{y[3],y[2],y[1],y[0]}= 4'b0001;
4'b0010:{y[3],y[2],y[1],y[0]}= 4'b0011;
4'b0011:{y[3],y[2],y[1],y[0]}= 4'b0010;
4'b0100:{y[3],y[2],y[1],y[0]}= 4'b0110;
4'b0101:{y[3],y[2],y[1],y[0]}= 4'b0111;
4'b0110:{y[3],y[2],y[1],y[0]}= 4'b0101;
4'b0111:{y[3],y[2],y[1],y[0]}= 4'b0100;
4'b1000:{y[3],y[2],y[1],y[0]}= 4'b1100;
4'b1001:{y[3],y[2],y[1],y[0]}= 4'b1101;
4'b1010:{y[3],y[2],y[1],y[0]}= 4'b1111;
4'b1011:{y[3],y[2],y[1],y[0]}= 4'b1110;
4'b1100:{y[3],y[2],y[1],y[0]}= 4'b1010;
4'b1101:{y[3],y[2],y[1],y[0]}= 4'b1011;
4'b1110:{y[3],y[2],y[1],y[0]}= 4'b1001;
4'b1111:{y[3],y[2],y[1],y[0]}= 4'b1000;
endcase
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
Endmodule
14
GRAY TO BINARY
TRUTH TABLE
B3
B2
B1
B0
Y3
Y2
Y1
Y0
15
GATE LEVEL
`
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE-ECE-B
// Engineer:
Praveen Kumar K K
// Create Date:
10:36:17 02/9/2012
// Design Name:
Gray to binary
// Module Name:
gray_bin_gate
// Project Name:
Digital Conversion
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
Code for converting GRAY to BINARY
// Model:
GATE LEVEL
// Comments:
Input/Output range 0000b - 1111b
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
module gray_bin_gate(y,b);
output [3:0]y ;
//4 bit output
input [3:0]b ;
//4 bit input
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
//---Y0----/////////////////////////////////////////////////////////////////////////////////////////////////////
xor x_1(y[0],b[3],b[2],b[1],b[0]);
// Y0 = B0^B1^B2^B3
//---Y1----/////////////////////////////////////////////////////////////////////////////////////////////////////
xor x_2(y[1],b[3],b[2],b[1]);
// Y1 = B3^B2^B1
//---Y2----/////////////////////////////////////////////////////////////////////////////////////////////////////
xor x_3(y[2],b[3],b[2]);
// Y2 = B3^B2
//---Y3----/////////////////////////////////////////////////////////////////////////////////////////////////////
buf b_1(y[3],b[3]);
// Y3 = B3
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
Endmodule
16
DATA FLOW LEVEL

///////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE-ECE-B
// Engineer:
Praveen Kumar K K
// Create Date:
10:36:17 02/9/2012
// Design Name:
Gray to binary
// Module Name:
gray_bin_gate
// Project Name:
Digital COnversion
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
Code for converting GRAY to BINARY
// Model:
DATA FLOW LEVEL
// Comments:
Input/Output range 0000b - 1111b
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
module gray_bin_data(y,b);
output [3:0]y ;
//4 bit output
input [3:0]b ;
//4 bit input
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
//---Y0----/////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[0] = ( b[0]^b[1] )^( b[2]^b[3] );
// Y0 = B0^B1^B2^B3
//---Y1----/////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[1] = b[3]^( b[2]^b[1] );
// Y1 = B3^B2^B1
//---Y2----/////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[2] = b[3]^b[2];
// Y2 = B3^B2
//---Y3----/////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[3] = b[3];
// Y3 = B3
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
Endmodule
17
Behavioral
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE - ECE - B
// Engineer:
Praveen Kumar K K
// Create Date:
00:08:02 02/7/2012
// Design Name:
Gray to Binary Convertor
// Module Name:
behavioral_bin_to_gray
// Project Name:
Digital Conversions
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
This code is for converting Gray to Binary sequence
// MODEL:
BEHAVIORAL LEVEL
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
module gray_bin_behavioral(y,b);
output [3:0]y;
input [3:0]b;
reg [3:0]y;
// storing output momentarily
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
always@(b[3],b[2],b[1],b[0])
case({b[3],b[2],b[1],b[0]})
4'b0000:{y[3],y[2],y[1],y[0]}= 4'b0000;
4'b0001:{y[3],y[2],y[1],y[0]}= 4'b0001;
4'b0011:{y[3],y[2],y[1],y[0]}= 4'b0010;
4'b0010:{y[3],y[2],y[1],y[0]}= 4'b0011;
4'b0110:{y[3],y[2],y[1],y[0]}= 4'b0100;
4'b0111:{y[3],y[2],y[1],y[0]}= 4'b0101;
4'b0101:{y[3],y[2],y[1],y[0]}= 4'b0110;
4'b0100:{y[3],y[2],y[1],y[0]}= 4'b0111;
4'b1100:{y[3],y[2],y[1],y[0]}= 4'b1000;
4'b1101:{y[3],y[2],y[1],y[0]}= 4'b1001;
4'b1111:{y[3],y[2],y[1],y[0]}= 4'b1010;
4'b1110:{y[3],y[2],y[1],y[0]}= 4'b1011;
4'b1010:{y[3],y[2],y[1],y[0]}= 4'b1100;
4'b1011:{y[3],y[2],y[1],y[0]}= 4'b1101;
4'b1001:{y[3],y[2],y[1],y[0]}= 4'b1110;
4'b1000:{y[3],y[2],y[1],y[0]}= 4'b1111;
endcase
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
Endmodule
18
BCD (Packed) to GRAY

TRUTH TABLE
Input Range* : 0000b 1001b
B3
B2
B1
B0
Y3
Y2
Y1
Y0
*The rest of the inputs/output from 10d 15d X ( Dont Care)

*Input so chosen to avoid complex Boolean expression, hence logic circuit
19
GATE LEVEL
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE - ECE - B
// Engineer:
Praveen Kumar K K
// Create Date:
00:18:30 02/18/2012
// Design Name:
BCD to Gray Convertor
// Module Name:
bcd_to_gray
// Project Name:
Digital Conversions
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
This code is for converting BCD to GRAY sequence
// MODEL:
GATE LEVEL
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
module bcd_to_gray(y,b);
output [3:0]y;
//4 bit output
input [3:0]b;
//4 bit input
//Y0--/////////////////////////////////////////////////////////////////////////////////////////////////////////
xor x_1(y[0],b[1],b[0]);
// Y0 = B2^B1
//Y1--/////////////////////////////////////////////////////////////////////////////////////////////////////////
xor x_2(y[1],b[1],b[2]);
// Y0 = B2^B3
//Y2--/////////////////////////////////////////////////////////////////////////////////////////////////////////
or or_1(y[2],b[2],b[3]);
// Y2 = B2+B3
//Y3--/////////////////////////////////////////////////////////////////////////////////////////////////////////
buf b_1(y[3],b[3]);
// Y3 = B3
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
Endmodule
20
DATA FLOW
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE - ECE - B
// Engineer:
Praveen Kumar K K
// Create Date:
00:18:30 02/18/2012
// Design Name:
// Module Name:
bcd_to_gray_data
// Project Name:
Digital Conversions
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
// MODEL:
DATA FLOW LEVEL
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
module bcd_to_gray_data(y,b);
output [3:0]y;
//4 bit output
input [3:0]b;
//4 bit input
//Y0--/////////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[0] = b[1]^b[0];
// Y0 = B1^B0
//Y1--/////////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[1] = b[2]^b[1];
// Y1 = B2^B1
//Y2--/////////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[2] = b[2]|b[3];
// Y2 = B2 + B3
//Y3--/////////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[3] = b[3];
// Y3 = B3&(~B2)&(~B1)
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
Endmodule
21
BEHAVIORAL
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE - ECE - B
// Engineer:
Praveen Kumar K K
// Create Date:
00:19:30 02/18/2012
// Design Name:
// Module Name:
bcd_to_gray_behavioral
// Project Name:
Digital Conversions
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
// MODEL:
BEHAVIORAL LEVEL
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
module bcd_gray_behavioral(y,b);
output [3:0]y;
//4 bit output
input [3:0]b;
//4 bit input
reg [3:0]y;
//For Storing output Momentarily
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
always@(b[3],b[2],b[1],b[0])
case({b[3],b[2],b[1],b[0]})
4'b0000:{y[3],y[2],y[1],y[0]}= 4'b0000;
4'b0001:{y[3],y[2],y[1],y[0]}= 4'b0001;
4'b0010:{y[3],y[2],y[1],y[0]}= 4'b0011;
4'b0011:{y[3],y[2],y[1],y[0]}= 4'b0010;
4'b0100:{y[3],y[2],y[1],y[0]}= 4'b0110;
4'b0101:{y[3],y[2],y[1],y[0]}= 4'b0111;
4'b0110:{y[3],y[2],y[1],y[0]}= 4'b0101;
4'b0111:{y[3],y[2],y[1],y[0]}= 4'b0100;
4'b1000:{y[3],y[2],y[1],y[0]}= 4'b1100;
4'b1001:{y[3],y[2],y[1],y[0]}= 4'b1101;
default: $display("input out of range");
endcase
///////////////////////////////////////////////////////////////////////////////////////////////////////////////
Endmodule
22
BCD TO EXCESS 3
TRUTH TABLE
INPUT RANGE* 0000b 1001b
B3
B2
B1
B0
Y3
Y2
Y1
Y0
The rest of the inputs/output from 10d 15d X ( Dont Care)

Input so chosen to avoid complex Boolean expression, hence logic circuit
23
GATE LEVEL
//////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE - ECE - B
// Engineer:
Praveen Kumar K K
// Create Date:
20:30:34 02/18/2012
// Design Name:
BCD to Excess3 Convertor
// Module Name:
bcd_to_excess3
// Project Name:
Digital Conversions
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
// MODEL:
GATE LEVEL
//////////////////////////////////////////////////////////////////////////////////////////////////////////
module bcd_to_xcess3_gate(y,b);
output [3:0]y;
//4 bit output
input [3:0]b;
//4 bit input
wire a,c,d,e,f,g,h;
//Nets for gate interconnections
//////////////////////////////////////////////////////////////////////////////////////////////////////////
/* input [3:0]n ---> negated version of vector [3:0]b------------------------------------------------------------*/
not n_0(n0,b[0]);
//
not n_1(n1,b[1]);
//Negation of inputs to heed
not n_2(n2,b[2]);
//conversion process
not n_3(n3,b[3]);
//
//Y0--////////////////////////////////////////////////////////////////////////////////////////////////////
buf b_1(y[0],n0);
// Y0 = ~B0
//Y1--////////////////////////////////////////////////////////////////////////////////////////////////////
and a_1(a,n0,n1);
//
and a_2(c,b[0],b[1]);
// Y1 = (~B1)&(~B2) + B1&B2
or or_1(y[1],a,c);
//
//Y2--////////////////////////////////////////////////////////////////////////////////////////////////////
or or_2(e,b[0],b[1]);
//
and a_3(f,e,n2);
// Y2 = B2&(~B1)&(~B0) + (~B2)&(B0+B1)
and a_4(d,b[2],n1,n0);
//
or or_3(y[2],d,f);
//
//Y3--////////////////////////////////////////////////////////////////////////////////////////////////////
or or_5(g,b[1],b[0]);
//
and a_5(h,g,b[2]);
// Y3 = B3 + B2&(B0+B1)
or or_4(y[3],b[3],h);
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
endmodule
24
DATA FLOW
//////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE - ECE - B
// Engineer:
Praveen Kumar K K
// Create Date:
21:16:23 02/18/2012
// Design Name:
BCD to Ecxess3 Convertor
// Module Name:
bcd_to_excess3
// Project Name:
Digital Conversions
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
This code is for converting BCD to EXCESS 3 sequence
// MODEL:
DATA FLOW LEVEL
//////////////////////////////////////////////////////////////////////////////////////////////////////////
module bcd_to_xcess3_data(y,b);
output [3:0]y;
//4 bit output
input [3:0]b;
//4 bit input
//Y0--////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[0] = ~b[0];
// Y0 = ~B0
//Y1--////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[1] = (~b[1])&(~b[2])|(b[1]&b[2]);
// Y1 = (~B1)&(~B2) + B1&B2
//Y2--////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[2] = (b[2]&(~b[1])&b[0])|(~b2)&(b[0]|b[1]) ;
//Y2 = B2&(~B1)&(~B0) + (~B2)&(B0+B1)
//Y3--////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[3] = b[3]|(b[2]&(b[0]|b[1]));
// Y3 = B3 + B2&(B0+B1)
//////////////////////////////////////////////////////////////////////////////////////////////////////////
Endmodule
25
BEHAVIORAL
//////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE - ECE - B
// Engineer:
Praveen Kumar K K
// Create Date:
22:20:34 02/18/2012
// Design Name:
BCD to Excess3 convertor
// Module Name:
bcd_to_excess3
// Project Name:
Digital Conversions
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
This code is for converting BCD to Excess-3 sequence
// MODEL:
BEHAVIORAL LEVEL
//////////////////////////////////////////////////////////////////////////////////////////////////////////
module bcd_xcess3_behavioral(y,b);
output [3:0]y;
//4 bit output
input [3:0]b;
//4 bit input
reg
[3:0]y;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
/////
always@(b[3],b[2],b[1],b[0])
case({b[3],b[2],b[1],b[0]})
4'b0000:{y[3],y[2],y[1],y[0]}= 4'b0011;
4'b0001:{y[3],y[2],y[1],y[0]}= 4'b0100;
4'b0010:{y[3],y[2],y[1],y[0]}= 4'b0101;
4'b0011:{y[3],y[2],y[1],y[0]}= 4'b0110;
4'b0100:{y[3],y[2],y[1],y[0]}= 4'b0111;
4'b0101:{y[3],y[2],y[1],y[0]}= 4'b1000;
4'b0110:{y[3],y[2],y[1],y[0]}= 4'b1001;
4'b0111:{y[3],y[2],y[1],y[0]}= 4'b1010;
4'b1000:{y[3],y[2],y[1],y[0]}= 4'b1011;
4'b1001:{y[3],y[2],y[1],y[0]}= 4'b1100;
endcase
//////////////////////////////////////////////////////////////////////////////////////////////////////////
Endmodule
26
Excess-3 to BCD (Packed)

TRUTH TABLE
INPUT RANGE* 0000b 1001b
B3
B2
B1
B0
Y3
Y2
Y1
Y0
The rest of the inputs/output from 10d 15d X ( Dont Care)

Input so chosen to avoid complex Boolean expression, hence logic circuit
27
GATE LEVEL
//////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE-ECE-B
// Engineer:
Praveen Kumar K K
// Create Date:
13:46:00 02/19/2012
// Design Name:
Excess3 to BCD(packed) Convertor
// Module Name:
xcess3_to_bcd_gate
// Project Name:
Digital Conversion
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
Code to Convert Excess 3 sequence to BCD(packed)
// Model:
GATE LEVEL
//////////////////////////////////////////////////////////////////////////////////////////////////////////
module xcess3_to_bcd_gate(y,b);
output [3:0]y;
//4 bit output
input [3:0]b;
//4 bit input
wire
a,c,d,e,f,g,h,i;
//Nets for gate interconnections
//////////////////////////////////////////////////////////////////////////////////////////////////////////
/* input [3:0]n ---> negated version of vector [3:0]b--------------------------------------------------------------*/
not n_0(n0,b[0]);
//
not n_1(n1,b[1]);
//Negation of inputs to heed
not n_2(n2,b[2]);
//conversion process
not n_3(n3,b[3]);
//
//Y0--////////////////////////////////////////////////////////////////////////////////////////////////////
buf b_1(y[0],n0);
// Y0 = (~B0);
//Y1--////////////////////////////////////////////////////////////////////////////////////////////////////
xor x_1(y[1],b[1],b[0]);
// Y1 = B1^B0
//Y2--////////////////////////////////////////////////////////////////////////////////////////////////////
and a_1(a,n1,n2);
//
and a_2(e,b[2],b[0]);
//
and a_3(f,b[3],n0);
// Y2 = (~B2).(~B1) + B1.(B2.B0 + B3.(~B0))
or or_2(d,e,f);
//
and a_4(g,b[1],d);
//
or or_1(y[2],a,g);
//
//Y3--////////////////////////////////////////////////////////////////////////////////////////////////////
and a_5(h,b[1],b[0]);
//
or or_3(i,b[2],h);
// Y3 = B3.(B2 + B1.B0)
and a_6(y[3],b[3],i);
//
//////////////////////////////////////////////////////////////////////////////////////////////////////////
Endmodule
28
DATA FLOW
//////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE-ECE-B
// Engineer:
Praveen Kumar K K
// Create Date:
15:00:54 02/19/2012
// Design Name:
Excess3 to BCD(packed) Convertor)
// Module Name:
xcess3_to_bcd_data
// Project Name:
Digital Conversion
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
// Model:
DATA FLOW LEVEL
//////////////////////////////////////////////////////////////////////////////////
module xcess3_to_bcd_data(y,b);
output [3:0]y;
//4 bit output
input [3:0]b;
//4 bit input
//Y0--////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[0]= ~b[0];
// Y0 = (~B0);
//Y1--////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[1]= b[1]^b[0];
// Y1 = B1^B0
//Y2--////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[2]= ((~b[2])&(~b[1]))|(b[1]&((b[2]&b[0])|(b[3]&(~b[0]))));// Y2 = (~B2).(~B1) + B1.(B2.B0 + B3.(~B0))
//Y3--////////////////////////////////////////////////////////////////////////////////////////////////////
assign y[3]= b[3]&(b[2]|(b[1]&b[0]));
// Y3 = B3.(B2 + B1.B0)
//////////////////////////////////////////////////////////////////////////////////////////////////////////
Endmodule
29
Behavioral
//////////////////////////////////////////////////////////////////////////////////////////////////////////
// Company:
KLNCE-ECE-B
// Engineer:
Praveen Kumar K K
// Create Date:
16:49:54 02/19/2012
// Design Name:
Excess3 to BCD(packed) Convertor)
// Module Name:
xcess3_to_bcd_behavioral
// Project Name:
Digital Conversion
// Target Devices:
Spartan3
// Tool versions:
Xilinx 9.2i
// Description:
// Model:
BEHAVIORAL LEVEL
//////////////////////////////////////////////////////////////////////////////////////////////////////////
module exccess3_bcd_behavioral(y,b);
output [3:0]y;
//4 bit output
input [3:0]b;
//4 bit input
reg
[3:0]y;
//////////////////////////////////////////////////////////////////////////////////////////////////////////
always@(b[3],b[2],b[1],b[0])
case({b[3],b[2],b[1],b[0]})
4'b0011:{y[3],y[2],y[1],y[0]}= 4'b0000;
4'b0100:{y[3],y[2],y[1],y[0]}= 4'b0001;
4'b0101:{y[3],y[2],y[1],y[0]}= 4'b0010;
4'b0110:{y[3],y[2],y[1],y[0]}= 4'b0011;
4'b0111:{y[3],y[2],y[1],y[0]}= 4'b0100;
4'b1000:{y[3],y[2],y[1],y[0]}= 4'b0101;
4'b1001:{y[3],y[2],y[1],y[0]}= 4'b0110;
4'b1010:{y[3],y[2],y[1],y[0]}= 4'b0111;
4'b1011:{y[3],y[2],y[1],y[0]}= 4'b1000;
4'b1100:{y[3],y[2],y[1],y[0]}= 4'b1001;
endcase
//////////////////////////////////////////////////////////////////////////////////////////////////////////
endmodule
30
BIBLIOGRAPHY
Reference for Verilog (General):
1. Verilog HDL 2nd Edition - Unit 3,5,6,7
- Samir Palnitkar
For K-Map Reduction Techniques (Brief)
2. Electronic Devices and Circiuts 2nd Edition p870 p883
-S Salhivahanan, N Suresh Kumar, A Vallavraj
World Wide Web

Wikipedia
http://en.wikipedia.org/wiki/Logic_gate
Boolean Expression Checker
http://turner.faculty.swau.edu/mathematics/materialslibrary/truth/
All DIGITAL Information
http://www.teahlab.com/
This document including the programs written under various abstraction, the truth tables etc. was
authored by
Praveen Kumar K K (093115)
Feedback @ (kk.1821@gmail.com)
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Digital Conversiona Using FPGA

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DIGITAL

DIGITAL CONVERSION 2012

For KLNCE-ECE (2013 Batch)

This is not a compilation of Truth tables, Boolean

DIGITAL CONVERSION 2012

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DIGITAL CONVERSION 2012

For KLNCE-ECE (2013 Batch)

Before You Proceed..

Check the comments before proceeding, it provides useful information.

BCD wherever used means PACKED BCD.

Knowledge of K-Map reeduction, General Digital Electronic knowledge and

Check Comments before proceeding to avoid redundant doubts.

All the programs are written in VERILOG.

All programs are tested & simulated using XILINX 9.2i.

Dyslexic Warning : due to close position of operators & operands it is highly

DIGITAL CONVERSION 2012

For KLNCE-ECE (2013 Batch)

For KLNCE-ECE (2013 Batch)

What is Excess -3?

DIGITAL CONVERSION 2012

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DIGITAL CONVERSION 2012

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DIGITAL CONVERSION 2012

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DATA FLOW LEVEL

DIGITAL CONVERSION 2012

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BINARY TO GRAY CONVERTOR

DIGITAL CONVERSION 2012

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DIGITAL CONVERSION 2012

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DIGITAL CONVERSION 2012

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For KLNCE-ECE (2013 Batch)

DIGITAL CONVERSION 2012

For KLNCE-ECE (2013 Batch)

DIGITAL CONVERSION 2012

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DATA FLOW LEVEL

DIGITAL CONVERSION 2012

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BCD (Packed) to GRAY

*The rest of the inputs/output from 10d 15d X ( Dont Care)

For KLNCE-ECE (2013 Batch)

DIGITAL CONVERSION 2012

For KLNCE-ECE (2013 Batch)

DIGITAL CONVERSION 2012

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DIGITAL CONVERSION 2012

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The rest of the inputs/output from 10d 15d X ( Dont Care)

For KLNCE-ECE (2013 Batch)

For KLNCE-ECE (2013 Batch)

DIGITAL CONVERSION 2012

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DIGITAL CONVERSION 2012

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Excess-3 to BCD (Packed)