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Topics p
Programmable Logic PLAs, PLDs PLAs PLDs, FPGAs Design Description Languages Introduction t I t d ti to VHDL Logic Value System of VHDL Entity E tit Architecture Concurrent S C Statements
Programmable Logic g g
Programmable Logic Arrays (PLAs) and PALs Two-level AND-OR array with True and Complemented inputs
Primarily used in large chip designs
Programmable Logic Devices (PLDs) A variety of proprietary designs consisting of several PLA lik bl k and programmable l like blocks d bl switches to interconnect them Field Programmable Gate Arrays (FPGAs) Thousands of identical macro-cells that can be interconnected by programmable switches yp g Each macro-cell is a Programmable Logic Gate
Truth Table is stored in a RAM, called the Look-up Table T bl (LUT)
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VHDL
VHSIC Hardware Description Language VHSIC - Very High Speed Integrated Circuits Follows the structure of ADA programming Language Originally intended as a Simulation Language for very large systems Very Strongly Typed Language, for example, bit vector 0011 and i t t d integer 3 are not easily t il interchangeable
Verilog and VHDL each have about 50% share of the commercial user base
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VHDL
Uses 9 Signal Values (IEEE standard) A Signal Val e m st be enclosed in single q otes Value must quotes
0 -- Forcing 0 1 -- Forcing 1 1 X -- Forcing Unknown - -- Dont Care Don t Z -- High Impedance U -- Uninitialized U L -- Weak 0 H -- Weak 1
Bit Vectors are enclosed in double quotes An example of VHDL assignment statement p g Y <=1 when STATE =0101 else 0;
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4 Din 2 sel
ENTITY
mux Dout
ARCHITECTURE
sel(1) sel(0) architecture structure of mux is signal s0bar, s1bar; std_logic; -- internal signals begin b i s0bar <= not(sel(0)); s1bar <= not(sel(1)); Dout <= (Din(3) and sel(1) and sel(0)) or (Din(2) and sel(1) and s0bar) or (Din(1) and s1bar and sel(0)) or (Din(0) and s1bar and s0bar); end architecture structure;
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A_in A in B_in
B_out entity compute is Port ( F : in std logic vector(2 downto 0); std_logic_vector(2 A_In, B_In : in std_logic; A_Out, B_Out : out std_logic; F_A_B F A B : o t std logic) out std_logic); end entity compute;
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Concurrency in VHDL y
Concurrent Signal Assignments (CSA) All statements in a VHDL description are e ec ted executed concurrently unless specified within a process Concurrency is useful in describing combinational logic circuits A concurrent statement is evaluated when any of its arguments change its value A process executes only on specified triggers A process declaration includes a sensitivity list A process executes only when one of the arguments in the sensitivity list changes Processes are useful in describing sequential g q circuits and state transition diagrams
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Q(7) Q(6) . . . . .
Q(1)Q(0)
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Counter Behavior
architecture counter_behavior of up_dn_counter is signal count: std_logic_vector(7 downto 0); Begin -- count is an internal signal to this process process(clk, asynch_reset) -- sensitivity list begin if (asynch reset=1) then count <= 00000000; (asynch_reset= 1 ) 00000000 ; elsif (rising_edge(clk)) then synchronous state transitions if (enable=1) then if (up down=1) then count <= count+00000001; (up_down 1 ) < count+ 00000001 ; else count <= count-00000001; end if; end if; ; -- end if is not permitted here to match elsif end if; end process; p Q <= count; end architecture counter_behavior; Note: We cannot use Q <= Q + 1 since Q is defined as output only
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Counter Behavior-2
architecture counter_behavior of up_dn_counter is begin process(clk, synch_reset) -- sensitivity list begin if (rising_edge(clk) then _ if(synch_reset=1) then Q <= 00000000; elsif (enable=1) then --notice no e in elsif if (up down=1) then Q <= Q + 1 ( p_ ) else Q <= Q - 1; end if; end if elsif -- end if is not permitted here to match the elsif end if; end if; -- notice it is end if not endif end process; end architecture counter_behavior;
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Shift-Register Behavior g
architecture Behavioral of reg_4 is signal reg_value: std_logic_vector(3 downto 0); begin b i operate_reg: process (Load, Shift_En, Clk, Shift_In) begin if (rising_edge(Clk)) then if (Shift_En = '1') then reg value <= Shift_In & reg value(3 downto 1); g_ g_ ( ) -- operator & concatenates two bit-fields elsif (Load = '1') then reg_value < reg value <= D; -- parallel load (lower priority than shift) else reg_value <= reg_value; --keep data unchanged end if; end if; end process;
Data_Out <= D t O t < reg_value; l Shift_Out <= reg_value(0); end architecture Behavioral;
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Control Unit
entity control is Port ( Reset, LoadA, LoadB, Execute : in std_logic; Clk : in std_logic; Shift_En, Ld_A, Ld_B : out std_logic); _ _ _ _ end entity control; Input switches Reset LoadA LoadB Execute Clk Ld_B Control (state machine) Control Bi C l Bits Shift_En Ld_A
0 0
Reset
B
Shift
C
Shift
D
Shift
E
Shift
F
Halt
1
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State Transitions
get_next_state: process (Execute, state) begin case state is when A => if (Execute = '1') then next_state <= B; else next_state <= A; end if; when B => next_state <= C; when C => next_state <= D; when D => next_state <= E; when E => next_state <= F; --wait at state F until 'Execute' = 0 when F => if (Execute = '0') then next_state <= A; else next_state next state <= F; end if; -- when others => default case is not needed here since there are -- only six values for state and we have exhausted them all. end case; end process;
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Using Components g p
entity full_adder is p port (x, y, z : in std_logic); y g x y z s, c : out std_logic); full_adder end entity; c s -- we will use the component full_adder to sum carry -- build a 4-bit ripple carry adder entity ADDER4 is port (A B : in std logic vector (3 down to 0); (A,B std_logic_vector S : out std_logic_vector (3 down to 0); c_in : in std_logic; c_out : out std_logic); t t td l i ) end entity; A3 B3 S3 A2 B2 A1 B1 ADDER4 S2 S1 A0 B0 c_in S0
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c_out
Connecting Components g p
architecture structural of ADDER4 is component full_adder is port(x,y,z: i std_logic; s,c: out std_logic); -- reproduce the entity d t( in td l i t td l i ) d h description end component full_adder; -- omit name full_adder for older simulators signal c0,c1,c2: std_logic; -- internal wires needed to connect full adders begin -- this illustrates how to instantiate and connect components FA0: full_adder port map(x =>A(0), y =>B(0), z =>c_in, s =>S(0), c =>c0); FA1: full_adder port map(x =>A(1), y =>B(1), z =>c0, s =>S(1), c =>c1); p p( ( ), ( ), , ( ), ); FA2: full_adder port map(x =>A(2), y =>B(2), z =>c1, s =>S(2), c =>c2); FA3: full_adder port map(x =>A(3), y =>B(3), z =>c2, s =>S(3), c =>c_out); end architecture structural ADDER4 A3 B3
x y c_out FA3 c z s
A2 B2 c2
x y FA2 c z s
A1 B1 c1
x y FA1 c z s
A0 B0 c0
x y FA0 c z s
c_in
S3
S2
S1
S0
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entity my_system
6
D
3
A
Register Unit Compute Unit 6
F
2
R
LoadA LoadB Execute Reset Clock Routing R ti Unit Control C t l Unit
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Architecture of my_system y_ y
architecture structural of my_system is component compute is -- entity description reproduced F2-F0 port(A_in, B_in: port(A in B in: in std logic; std_logic; A_out A_out, B_out, F_A_B: out std_logic; A_inentity F: in std_logic_vector(2 downto 0)); compute F_A_B end component compute; B_in B in B_out B out component register_unit is ... -- reproduce entity description here component router is ... -- reproduce entity description here component control is ... -- reproduce entity description here p y p end component control; signal ...; - declare all signals needed to interconnect components begin ... -- instantiate and connect all components in main body computation_unit: compute port map(F=>F, A_in=> ..., B_in=>..., F_A_B=>...); ... end architecture structural my_system;
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Summary y
VHDL is a design description language not a language that automatically designs for you! The design process is very similar to the designing with TTL chips and wires, but with much more flexibility d functionality fl ibili and f i li In VHDL you create your own chips (entities) and connect the pins (ports) with wires (signals) pins wires You cannot make bigger TTL chips out of smaller chips, but with VHDL you can make bigger and p , y gg more complex entities out of smaller entities (e.g. a 16-bit ALU out of 16 one-bit ALU slices) You Y must first design on paper using block t fi t d i i bl k diagrams and interconnections, before you can describe it in VHDL!
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