IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 47, NO.

2, MARCH/APRIL 2011

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A New DC-Voltage-Balancing Circuit Including a Single Coupled Inductor for a Five-Level Diode-Clamped PWM Inverter
Kazunori Hasegawa, Student Member, IEEE, and Hirofumi Akagi, Fellow, IEEE
AbstractThis paper proposes a new dc-voltage-balancing circuit for a ve-level diode-clamped inverter intended for a medium-voltage motor drive with a three-phase diode rectier used as the front end. This circuit consists of two unidirectional choppers and a single coupled inductor with two galvanically isolated windings. The inductor produces no net dc magnetic ux because the individual dc magnetic uxes generated by the two windings are canceled out with each other. This makes the inductor compact by a factor of six, compared with the balancing circuit including two noncoupled inductors. Moreover, introducing phase-shift control to the new balancing circuit makes it possible to adjust the midpoint voltage. As a result, the dc mean voltages of all the four split dc capacitors can be balanced, independent of inverter control. Experimental results obtained from a 200-V 5.5-kW downscaled model verify the effectiveness of the new balancing circuit. Index TermsCoupled inductors, motor drives, multilevel inverters, voltage balancing.

I. I NTRODUCTION INCE THE three-level neutral-point-clamped, or diodeclamped, inverter was invented in 1979 [1], it has been applied to steel-mill drives, unied power ow controllers, the Japanese bullet train (the so-called Shinkansen), and so on. Recently, attention has been paid to multilevel (more than three levels) inverters intended for medium-voltage and high-power applications [2][10]. A main motivation of research on a velevel diode-clamped pulsewidth-modulated (PWM) inverter using 3.3-, 4.5-, or 6.5-kV insulated-gate bipolar transistors (IGBTs) is to eliminate bulky line-frequency transformers from medium-voltage motor drives. However, four split dc-capacitor voltages tend to be unequal even in an ideal operating condition as long as active power ows into, or out of, the ve-level PWM inverter [2], [4]. The authors of [5] had a theoretical discussion on a spacevector pulsewidth-modulation method capable of balancing the four dc-capacitor voltages without additional hardware installation. Although this method is based on selecting an appropriate switching state from some redundant switching states, it works only in low-modulation indices. The authors of
Manuscript received May 19, 2010; accepted July 25, 2010. Date of publication December 23, 2010; date of current version March 18, 2011. Paper 2010-IPCC-154, presented at the 2009 IEEE Energy Conversion Congress and Exposition, San Jose, CA, September 2024, and approved for publication in the IEEE T RANSACTIONS ON I NDUSTRY A PPLICATIONS by the Industrial Power Converter Committee of the IEEE Industry Applications Society. The authors are with Tokyo Institute of Technology, Tokyo 152-8550, Japan (e-mail: hasegawa@akg.ee.titech.ac.jp; akagi@ee.titech.ac.jp). Digital Object Identier 10.1109/TIA.2010.2102327

[6] addressed another pulsewidth-modulation method that does not suffer from these restrictions, without additional hardware installation, but at the expense of increasing the switching losses and output voltage total harmonic distortion. The authors of [7] proposed a sophisticated pulsewidth-modulation method for balancing the dc-capacitor voltages and mitigating lineharmonic currents in a ve-level PWM rectier/inverter system for a motor drive. A three-phase six-pulse diode rectier is lower in cost, higher in power conversion efciency, and much more reliable than a ve-level PWM rectier. Therefore, the diode rectier is applicable to fans, blowers, pumps, and compressors without regenerative braking. As for complying with harmonic guidelines or regulations, a transformerless hybrid active lter has been proposed to devote itself to the diode rectier used as the front end of a medium-voltage motor drive. The hybrid lter is characterized by series connection of a passive lter tuned to the seventh harmonic frequency and an active lter using a three-level diode-clamped PWM converter [11], [12]. This paper proposes a new dc-voltage-balancing circuit integrating a single inductor having two galvanically isolated windings into two unidirectional choppers. Canceling out the individual dc magnetic uxes produced by the two windings makes the coupled inductor signicantly compact and light. Note that a fully coupled inductor without air gap acts as an ideal transformer and not as an energy-storage magnetic device. Moreover, a small amount of leakage inductance inherent in each winding plays an important role in achieving a stable operation of the new balancing circuit. This paper introduces the following two balancing control methods to the new circuit: 1) duty-factor control and 2) phaseshift control. The former is used for voltage balancing between the two dc capacitors at the positive side and between those at the negative side. The latter achieves voltage balancing between a set of the two dc capacitors at the positive side and the other set at the negative side. In other words, it can control the midpoint voltage with respect to the positive or negative dc link. As a result, the new circuit can balance all the four split dccapacitor voltages, independent of the pulsewidth modulation of the inverter. A 200-V 5.5-kW downscaled model is developed, constructed, and tested to conrm the viability and effectiveness of the new balancing circuit. In addition, this paper makes a theoretical comparison in volume between a single coupled inductor and two noncoupled inductors under the same

0093-9994/$26.00 2010 IEEE

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Fig. 1. Previous voltage-balancing circuit equipped with two noncoupled inductors, where 4.5-kV IGBTs and diodes are used [9].

Fig. 2. Proposed voltage-balancing circuit equipped with a single coupled inductor.

operating conditions. This comparison reveals that the new balancing circuit makes a signicant contribution to reducing the inductor volume, for example, by a factor of six, compared with the balancing circuit using two noncoupled inductors. II. VOLTAGE I MBALANCE P HENOMENON Fig. 1 shows the circuit conguration of a medium-voltage motor drive in which a voltage-balancing circuit is installed on the dc link between the three-phase diode rectier and the ve-level inverter. The voltage-balancing circuit consists of two unidirectional buck and boost choppers and two noncoupled inductors. When active power ows from the diode rectier to the induction motor through the inverter with no balancing circuit, two outer capacitors (Cdc1 and Cdc4 ) are always charged to have higher voltages, whereas the two inner capacitors (Cdc2 and Cdc3 ) are always discharged to have lower voltages [2]. Finally, the inner capacitor voltages get zero, thus acting as a three-level inverter. Therefore, a voltage-balancing circuit for charging the inner capacitors and discharging the outer capacitors is indispensable to solve the voltage imbalance phenomenon of the four split dc capacitors.1 The previous balancing circuit shown in Fig. 1 makes the positive-side chopper discharge Cdc1 and charge Cdc2 , while it makes the negativeside chopper discharge Cdc4 and charge Cdc3 . When the ve-level inverter is applied to a static synchronous compensator (STATCOM), the kilovoltampere rating of the balancing circuit is about 1% of that of the ve-level inverter [10]. However, when it is applied to a motor drive, the kilovoltampere rating of the balancing circuit tends to be larger and larger as the active power owing into, or out of, the ve-level inverter gets higher and higher [2], [9]. As a result, the two inductors in the previous balancing circuit would get bulky and heavy. Each of the two inductors operates as an energy-storage element. From a practical point of view, it is desirable for the
1 If the ve-level inverter is operated with regenerative braking, the two inner capacitors are charged to have higher voltage and the two outer capacitors are discharged to have lower voltage. However, this paper does not pay any attention to this phenomenon because it focuses on fans, blowers, pumps, and compressors without regenerative braking.

inductor to be as compact and light as possible, meeting the other constrains on it. In general, the volume of an inductor is proportional to the maximum stored energy. Reducing the stored energy, i.e., reducing the inductance value, can be realized by high-frequency switching. However, a practical switching frequency of 4.5-kV IGBTs is limited to 1 kHz. III. N EW DC-VOLTAGE -BALANCING C IRCUIT I NCLUDING A S INGLE C OUPLED I NDUCTOR A. Circuit Conguration and Basic Operating Principle The basic idea of a coupled inductor intended for cancellation of the dc magnetic ux is not new in a power electronic circuit. For example, two-channel interleaved boost converters with a coupled inductor have been proposed for a power-factorcorrection rectier [13], [14]. Fig. 2 shows a new voltage-balancing circuit including a single coupled inductor LC for a ve-level diode-clamped PWM inverter. The previous balancing circuit consists of two unidirectional independent choppers and two noncoupled inductors. The new circuit consists of two unidirectional complementary choppers and a single coupled inductor in which the positive- and negative-side windings are magnetically coupled through a common core. Thus, the two complementary choppers, as a whole, can be considered as a single chopper with the single coupled inductor. Fig. 3 shows the basic principle of the new voltage-balancing circuit and two switching modes where the positive-side IGBTs (Q1 and Q2 ) and the negative-side IGBTs (Q3 and Q4 ) are complementarily turned on or off.2 Note that the coupled inductor LC is divided into the mutual inductance LM and the two leakage inductances P and N , as shown in Fig. 3. The two leakage inductances are much smaller than the mutual inductance LM .
2 In an actual system, a short period of time exists in which either D or D 1 4 turns on, and the corresponding inductor current circulates through D1 or D4 in Fig. 3. However, this period can be eliminated from this discussion when attention is paid to the basic operating principle.

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Fig. 5. Equivalent circuit to the voltages across the positive- and negative-side windings. Fig. 3. Basic operating modes in the new circuit. (a) Mode A. (b) Mode B.

as shown in Fig. 5(b). In addition, if the two dc-capacitor voltages are equal, i.e., vP2P1 = vMN1 |v
P

+ v N | = VQsum + VDsum .

(1)

Fig. 4. Designations of the four split dc capacitors and their associated voltages.

Fig. 4 shows the dc-link voltage vP2N2 , which is the voltage of node P2 with respect to node N2, and the four dc-capacitor voltages, along with the ve nodes P2, P1, M, N1, and N2. In mode A, the voltage across the positive-side winding vMP is nearly equal to vP2P1 because the positive-side IGBTs remain turned on. The negative-side winding voltage vMN is also nearly equal to vP2P1 because the negative-side winding voltage is the same as the positive-side one. In this case, Cdc3 is being charged by vMN through D3 . As a result, the energy stored in Cdc1 is transferring to Cdc3 . On the other hand, the energy stored in Cdc4 is transferring to Cdc2 in mode B. The two switching modes repeat alternately so as to discharge Cdc1 and Cdc4 and to charge Cdc2 and Cdc3 . Finally, the dc mean voltages of the four split dc capacitors are balanced completely. B. Why Are the Leakage Inductances Necessary? Fig. 5(a) shows an equivalent circuit focusing on the voltages across the positive- and negative-side windings in mode A, where VQsum is the sum of the saturation voltages of Q1 and Q2 and VDsum is a forward voltage of D3 . The voltage across the positive-side winding is slightly lower than that across the dc capacitor Cdc1 , while the voltage across the negative-side winding is a little bit higher than that across the dc capacitor Cdc3 . If the coupled inductor is ideal under a condition of iLP = iLN , Fig. 5(a) results in such a simple equivalent circuit

Thus, the sum of the saturation and forward voltages of the two IGBTs and the two diodes is applied to the two leakage inductances. Unless leakage inductance existed, the sum of VQsum and VDsum would cause an overcurrent. The leakage inductance value produces a signicant effect on current ripples of iLP and iLN . A voltage across a noncoupled inductor in the previous balancing circuit is equal to the voltage across a split dc capacitor. On the other hand, a voltage across a leakage inductance in the new circuit is equal to the sum of the saturation and forward voltages, which is much lower than the voltage across a split dc capacitor. Therefore, this makes the leakage inductance much smaller in inductance value than the noncoupled inductor. Current ripples of iLP and iLN , i.e., ILP and ILN , are given by ILP = ILN = |VQsum + VDsum | P+ N (2)

where is a time interval of mode A or B. Equation (2) makes it possible to determine the required values of P and N . Note that the current ripples tend to increase when the two dc-capacitor voltages are unequal, because a voltage difference vP2P1 vMN1 or vP1M vN1N2 is applied to the corresponding leakage inductance. Moreover, the leakage inductances play an important role in both duty-factor and phase-shift controls as described in the following sections. C. Comparison to the Previous Balancing Circuit Each of two noncoupled inductors acts as an energy-storage element in the previous circuit, whereas the coupled inductor operates as a non-energy-storage element in the new circuit. Fig. 6(a) shows a magnetic ux in one noncoupled inductor, and Fig. 6(b) shows that in the coupled inductor. The magnetic ux in the noncoupled inductor has a dc component because it carries a dc current, whereas the magnetic ux in the coupled inductor has no dc component because the individual dc magnetic uxes caused by iLP and iLN are canceled out with

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Fig. 6. Magnetic ux in an inductor. (a) Noncoupled inductor. (b) Coupled inductor.

the inner capacitor voltages because a small amount of voltage difference remains in the four split dc-capacitor voltages. Thus, additional operating periods 2, 4, 6, and 8 are introduced to charge the inner capacitors and to discharge the outer capacitors. During periods 2 and 8, Cdc1 is discharged because a short circuit is formed by Cdc1 and the two series-connected leakage inductances ( P + N ). During periods 4 and 6, Cdc4 is discharged. The voltage balancing of the four split dc capacitors can be achieved by appropriately adjusting these periods with the help of voltage feedback control of the four dc capacitors. Note that neither charge nor discharge occurs during periods 3 and 7. B. Control Diagram

Fig. 7. Switching sequence of the voltage-balancing circuit.

each other3 [14], [15]. Hence, the maximum magnetic ux in the coupled inductor is much lower than that of the noncoupled inductor. As a result, the coupled inductor has a smaller crosssectional area when the noncoupled and coupled inductors are designed as long as both inductors have the same magnetic ux density and the same turns of windings. IV. D UTY-FACTOR C ONTROL In theory, the new circuit including a single coupled inductor can balance the four split dc-capacitor voltages as long as the positive- and the negative-side IGBTs are complementarily turned on or off. In practice, however, small voltage differences would remain among the four split dc capacitors because saturation and forward voltage drops occur in the IGBTs and diodes.4 The following sections have an intensive discussion on voltage feedback control for mitigating the effect of the voltage drops on voltage-balancing performance. A. Switching Sequence Fig. 7 shows the switching sequence consisting of eight operating periods numbered 18. The negative-side IGBTs (Q3 and Q4 ) are phase-shifted by (in radians) from the positiveside IGBTs (Q1 and Q2 ). Fig. 8 shows the balancing circuit in which ON-state semiconductor devices and the corresponding current loop paths are shown in each period. Period 1 is the same as mode A in Fig. 3, in which Cdc1 is discharged whereas Cdc3 is charged. On the other hand, Cdc4 is discharged whereas Cdc2 is charged in period 5, which is the same as mode B. However, using only periods 1 and 5 makes the outer capacitor voltages higher than
3 The dc components of i LP and iLN are determined by those of the current owing out of node P1 into the inverter, i.e., iP1 , and the current owing into node N1 out of the inverter, i.e., iN1 , respectively. These currents have the same dc component in principle. Therefore, the dc components of iLP and iLN are the same. 4 The voltage drops have an adverse function of decreasing the active power which is transferred from the outer capacitor Cdc1 or Cdc4 to the inner capacitor Cdc2 or Cdc3 . Therefore, the inner capacitor voltages tend to get lower than the outer capacitor voltages.

Fig. 9 shows the control diagram of the voltage-balancing circuit. The negative-side control diagram is independent of the positive-side one. Note that the negative-side carrier signal vtriN is phase-shifted by 180 from the positive-side one vtriP . A proportional-plus-integral controller for voltage regulation has a proportional gain of 0.5 A/V and an integral time constant of 50 ms. A proportional controller for current control has a proportional gain of 0.15 V/A. The circulating period TR corresponds to periods 3 and 4 or 6 and 7 in the positive-side sequence (Q1 and Q2 ) in Fig. 7, or to periods 2 and 3 or 7 and 8 in the negative-side sequence (Q3 and Q4 ). It is dened as a time interval in which the inductor current iLP or iLN circulates through D1 or D4 and Q2 or Q3 on the ON state, respectively. The ratio of the circulating period TR with respect to the carrierwave period TCB is dened as D D 2TR . TCB (3)

The following experiment has a parameter of D = 0.1 at TCB = 800 s. V. P HASE -S HIFT C ONTROL FOR M IDPOINT-VOLTAGE BALANCING In practice, a small amount of dc current would ow into or out of the midpoint (node M), which is produced by unequal conducting and switching losses, as well as signal imbalance inherent in the control circuit including voltage/current sensors. This makes the midpoint voltage imbalanced. The midpoint voltage can be balanced by means of the so-called zerosequence voltage injection [9], [16]. However, it may pose a limitation on the degree-of-freedom of pulsewidth modulation and may cause a saturated ac voltage of the inverter when a modulation index of the inverter is near 1.0. The following sections discuss the modeling of the balancing circuit and reveal that the balancing circuit operates as a bidirectional half-bridge dcdc converter between the positive and the negative side. As a result, the balancing circuit can be used for voltage regulation between the two positive-side capacitors and the negative-side ones. In other words, it can control the midpoint voltage. Moreover, theoretical analysis of the balancing circuit conrms that a power ow between the

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Fig. 8. Eight operating periods in the voltage-balancing circuit. (a) Period 1. (b) Period 2. (c) Period 3. (d) Period 4. (e) Period 5. (f) Period 6. (g) Period 7. (h) Period 8.

Fig. 10. DC-voltage-balancing circuit behaving like a bidirectional halfbridge dcdc converter.

Fig. 9. Control diagram of the voltage-balancing circuit. (a) Positive side. (b) Negative side.

positive and the negative side is in proportion to a phase-shift angle between them. A. Modeling of the DC-Voltage-Balancing Circuit Fig. 10 shows the equivalent circuit of the dc-voltagebalancing circuit where the positive-side circuit is shown in the left and the negative-side circuit is shown in the right. Let the dc component of the current owing out of node P1 be a current source IP1 and the dc component of the current owing into node N1 be a current source IN1 . Currents owing out of or into node P2 or N2 practically exist. However, these currents can be discarded because they are independent of the dc-voltagebalancing circuit. If clamping diodes D1 and D4 are eliminated

and free-wheeling diodes D2 and D3 are regarded as active switches, the circuit looks like a bidirectional half-bridge dcdc converter [17], [18]. Since the positive-side IGBTs (Q1 and Q2 ) and the negative-side IGBTs (Q3 and Q4 ) are complementarily turned on or off, a set of positive-side IGBTs and D3 and the other set of negative-side IGBTs and D2 are alternately turned on or off. Thus, it seems that the bidirectional dcdc converter operates with no phase shift. Phase-shift control can adjust an amount of power ow between the positive and the negative side, which can be used for midpoint-voltage balancing. B. Power Flow Between the Positive and the Negative Side Fig. 11 shows the simplied equivalent circuit of the dcvoltage-balancing circuit with focus on saturation voltages of IGBTs and forward voltages of diodes. Let the saturation voltage of an IGBT be VQ , the forward voltage of a diode be VD , and the capacitor voltage be Vdc . The positive-side leg can be considered as the three-pole switch clamping nodes P2, P1, or M. The negative-side leg is also shown as the three-pole

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C. How to Implement the Phase-Shift Control The phase-shift control should produce no effect on the dutyfactor control. In other words, the phase-shift angle between the positive side and the negative side should give no disturbance to duty factors of Q1 , Q2 , Q3 , and Q4 . Fig. 13 shows the implementation of the phase-shift control, where vref is a reference signal of an IGBT, vtri is a carrier signal which has an amplitude of unity, and is a period during which the IGBT remains turned on. The waveform denoted by vref results from superimposing a square wave on vref . The superimposed square wave has a positive value when the slope of vtri has a positive value, whereas it has a negative value when the slope has a negative value. Thus, an intersection of vtri and vref always lags with respect to that of vtri and vref . No change occurs in even if the phase-shift angle is controlled. A lagging phase-shift angle is in proportion to an amplitude of the square wave vref as = vref . (6)

Fig. 11. Simplied equivalent circuit with focus on saturation and forward voltages of IGBTs and diodes, where = P + N .

switch clamping nodes M, N1, or N2. The coupled inductor is replaced with the sum of the positive-side leakage inductance P and the negative-side leakage N , where the mutual inductance is neglected because it is assumed to be much larger than leakage inductances. Note that v is the voltage across leakage inductance and i is the current owing into the negative side through the leakage inductance. Furthermore, IP1 and IN1 are neglected because they do not produce any effect on the power ow between the positive and the negative side. Fig. 12 shows the switching sequence and the analyzed waveforms, in which is the pulsewidth of Q1 or Q4 , is that of Q2 or Q3 , and n (n = 1, 2, . . . , 8) is the phase angle of the corresponding period. What is most important in Fig. 12 is that the waveforms of iPM and iNM have no dc components when no phase-shift angle occurs between the positive and the negative side.5 Hence, no power ow exists between the positive and the negative side. On the other hand, as shown in Fig. 12(b), the waveforms of iPM and iNM contain dc components when a phase-shift angle is introduced. Therefore, a small amount of power ow occurs from the positive to the negative side when the negative-side switching sequence lags the positive-side one. The dc components of iPM and iNM are given by (see the Appendix) INM = IPM = Vdc 2VQ 1 2 (4)

In addition, in case of vref < 0, a leading phase-shift angle is obtained. Fig. 14 shows the control diagram in which is a lagging phase-shift angle reference of the negative-side leg, vP2M is the voltage of node P2 with respect to node M, and vMN2 is the voltage of node M with respect to node N2. This consists of a low-pass lter with a cutoff frequency of 5 Hz (T = 32 ms) and a proportional gain of 0.05 rad/V. The low-pass lter is used for the ltering of ripple components from the two detected dc-capacitor voltages. VI. E XPERIMENTAL R ESULTS A. Experimental System Conguration Fig. 15 shows the experimental motor drive system that consists of a front-end diode rectier, a new dc-voltage-balancing circuit, a ve-level diode-clamped PWM inverter, and a threephase four-pole induction motor. Table I summarizes the ratings and circuit parameters of the experimental system. The frontend diode rectier is connected to the ac mains through an ac inductor. A permanent-magnet synchronous generator is mechanically coupled with the induction motor, and a three-phase star-connected resistive load is connected to the synchronous generator. The resistive load is adjusted to make the dissipated power proportional to a cubic of the rotating speed of the motor. As a result, the combination of the synchronous generator and the resistive load acts as a fan or a blower. Fig. 16 is a photograph of the coupled inductor designed and constructed by the authors. It uses silicon-steel cut cores. Table II shows the circuit parameters of the inductor. Optimal design would bring a further reduction in volume to the coupled inductor. B. Performance of the Phase-Shift Control

where = 2f and f is the switching frequency. Thus, the power ow between the positive and the negative side, namely, PPN , is given by PPN =
2 2Vdc 4VQ Vdc

(5)

Equation (5) suggests that PPN is in inverse proportion to the leakage inductance and in proportion to the phase-shift angle . This power ow brings a slight increase in the power rating of the coupled inductor LC . However, it is negligible in an actual system because an amount of power to control the midpoint voltage is so small that the phase-shift angle is close to zero.

5 The phase-shift angle is dened as zero in case the negative-side IGBTs are phase-shifted by exactly (in radians) from the positive-side ones.

Fig. 17 shows the voltage difference between the positive and the negative side, VDif = |VP2M VMN2 |, in a modulation

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Fig. 12. Waveforms and the switching sequence. (a) With no phase shift. (b) With a phase shift of .

increased to 10.4 V (7.6% of 135 V) at MI = 0.4 with no control, whereas it decreased to 3 V (2.2%) with control.

C. Experimental Waveforms Fig. 19 shows experimental waveforms when the ve-level inverter was operated at the following conditions: a modulation index of MI = 1.15 with third harmonic injection, an output frequency of f = 57.5 Hz, and an output power of PO = 4.7 kW. The u-phase voltage with respect to the midpoint M, i.e., vuM , was a ve-level PWM waveform, and the line-to-line voltage between the u phase and the v phase, namely, vuv , was a nine-level PWM waveform. The four dc-capacitor voltages were well balanced as expected. Fig. 20 shows experimental waveforms when the ve-level inverter was operated at the following conditions: a modulation index of MI = 0.8, an output frequency of f = 40 Hz, and an output power of PO = 1.6 kW. In this case, the inductor currents iLP and iLN take the same maximum value as 7 A (40%) when a fan or a blower is loaded on the motor [9]. The four dc-capacitor voltages were also well balanced, and both inductor currents were well controlled without magnetic saturation. This means that the leakage inductance inherent in the coupled inductor plays an important role in controlling the inductor current. Table IV summarizes dc mean voltages of the four split dc capacitors in the experimental results, as shown in Figs. 19 and 20. The dc mean voltages are balanced well.

Fig. 13. Implementation of the phase-shift control.

Fig. 14. Control diagram of the phase-shift angle reference , in which T = 32 ms and K = 0.05 rad/V.

index range from 0.4 to 1.15. Table III summarizes the output power of the inverter. When no phase-shift control was applied, the voltage difference VDif increased as the modulation index decreased. It was 1.4 V (1% of 135 V) at MI = 0.4 with no control, whereas it was less than 0.2 V (0.2%) with it. Fig. 18 shows special experimental results where a resistor of 500 (0.7% of the rated power) was intentionally connected between nodes M and N2. The voltage difference VDif

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Fig. 15. Three-phase 200-V 5.5-kW laboratory motor drive system. TABLE I R ATINGS AND C IRCUIT PARAMETERS TABLE II C IRCUIT PARAMETERS OF THE C OUPLED I NDUCTOR

TABLE III O UTPUT P OWER OF THE I NVERTER

A. Area Product The area product is useful for evaluating the volume of an inductor or a transformer, which was introduced in [20]. It is dened by the following equation as the product of a core crosssectional area Acore and a core window area Awindow , as shown in Fig. 21: Ap = Acore Awindow .
Fig. 16. Coupled inductor used for experiment, along with a ballpoint pen.

(7)

VII. C OMPARISON IN I NDUCTOR VOLUME This section makes a theoretical comparison in volume between two noncoupled inductors in the previous circuit and a single coupled inductor in the new circuit. This comparison is based on the so-called area product [20], [21].

Since the core window is perpendicular to the core cross section, the volume of an inductor or a transformer can be specied when the two areas are specied. The volume V is related to the area product Ap as follows: V = KV A3/4 p (8)

where KV is a constant parameter depending on the core geometry.

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Fig. 17. Voltage differences between the positive and the negative side.

Fig. 20. 1.6 kW.

Experimental waveforms at MI = 0.8, f = 40 Hz, and PO = TABLE IV S PLIT DC-C APACITOR VOLTAGES IN F IGS . 19 AND 20

Fig. 18. Voltage difference when a resistor of 500 is connected between nodes M and N2.

Fig. 21. Denition of area product.

The area product of a transformer is given by ApT = 2P 4Ku fS Bm Jw (10)

where P is the rated power capacity of the transformer and fS is a switching or operating frequency. After all, the area product of a transformer is proportional to the rated power capacity. B. Comparison Between the Previous and New Circuits First of all, let us calculate the total volume of the two noncoupled inductors in the previous circuit for the 200-V 5.5-kW downscaled model with the following parameters: 1) rated dc mean inductor current: IL (in amperes); 2) switching frequency: fS (in hertz); 3) dc-capacitor voltage: Vdc (in volts); 4) ripple width of inductor current: IL (in amperes, peak to peak); 5) maximum magnetic ux density: Bm (in teslas); 6) rated current density of winding lead wire: Jw (in amperes per square meter); 7) utilization factor of window: Ku .

Fig. 19. Experimental waveforms at MI = 1.15, f = 57.5 Hz, and PO = 4.7 kW.

The area product of an inductor is given by ApL = 2W Ku Bm Jw (9)

where W is the maximum stored energy, Ku is a utilization factor of the window, Bm is the maximum magnetic ux density of the core, and Jw is the maximum current density of the winding lead wire. Thus, the area product of an inductor is proportional to the maximum stored energy.

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The inductance value of the noncoupled inductor LNC is given by LNC = Vdc (in henry). 2IL fS (11)

Here, the ripple ratio of the inductor current is given by r= IL /2 IL (12)

two noncoupled inductors when the ripple ratio is maximum (r = 1). The ripple factor in the experimental result shown in Fig. 20 is r = 0.14 because the ripple current width is 2 A and the rated inductor current is 7 A. In this case, the volume of the coupled inductor is about 16% of the total volume of the two noncoupled inductors. VIII. C ONCLUSION This paper has proposed a new dc-voltage-balancing circuit for a ve-level diode-clamped PWM inverter intended for a medium-voltage motor drive without regenerative braking. The new circuit is characterized by replacing two noncoupled inductors with a single coupled inductor. Theoretical comparison based on the so-called area product has revealed that the volume of the single coupled inductor can be reduced by a factor of six, compared with the total volume of the two noncoupled inductors. Experimental results obtained from the 200-V downscaled model have conrmed the viability and effectiveness of the new balancing circuit, verifying that the dc mean voltages of the four split dc capacitors are well balanced as expected. A PPENDIX The phases in the eight operating periods 1 8 in Fig. 12 are given by 2 1 + 2 + 2 3 + + 4 + 2 (18) = 2 5 + 6 + 2 + 7 + 8 + 2 + where is the phase-shift angle. In addition, V given by VH VL = Vdc 3VQ VD 2VQ 2VD
L

where the ripple ratio has a range of 0 < r 1 if the inductor current keeps a continuous current mode. The maximum stored energy in the noncoupled inductor WNC is calculated by the following equation: 1 IL WNC = LNC IL + 2 2 Vdc 1 2 = I (1 + r)2 2 4rIL fS L Vdc IL (1 + r)2 (in joules). = 2fS 4r
2

(13)

The maximum stored energy WNC gets a minimum value at the ripple ratio of r = 1 that is the maximum to keep a continuous current mode. Equation (13) gives the area product of the noncoupled inductor ApNC as follows: ApNC = 2 Vdc IL (1 + r)2 Bm Jw Ku 2fS 4r (1 + r)2 Vdc IL = (in m4 ). 4r Bm Jw Ku fS

(14)

Next, let us calculate the area product of the coupled inductor in the new circuit under the same conditions as those in the previous circuit. The area product of the coupled inductor can use that of a transformer because the coupled inductor is the same as a transformer in terms of operating principle. When the leakage inductance is assumed to produce no effect on the volume of the coupled inductor, the area product of the coupled inductor ApC is given as follows: ApC Vdc IL 1 = (in m4 ). 2 Bm Jw Ku fS (15)

and V

are

(19)

Note that the area product of the noncoupled inductor depends on the ripple ratio, whereas that of the coupled inductor does not. Equations (14) and (15) yield the area product ratio of the coupled inductor with respect to the two noncoupled inductors as follows: ApC 2r = . ApNC (1 + r)2 (16)

From the waveform of i , the relations between I n and I n1 , where n equals 1, 2, 3, 4, 5, 6, 7, or 8, are given by the following: I I I I I I I I
1 2 3 4 5 6 7 8

Equations (8) and (16) give the volume ratio of the coupled inductor with respect to the two noncoupled inductors as follows: VC 1 = 2VNC 2 2r (1 + r)2
3/4

(17)

Equation (17) is a monotonically increasing function when the ripple ratio has a range of 0 < r 1. The volume of the coupled inductor is about 30% with respect to that of the

1 1 = 1 = 1 = 1 = 1 = 1 = 1 = =

V V V V V V V V

H L H L H L H L

8 + I 1 + I 2 + I 3 + I 4 + I 5 + I 6 + I

8 1 2 3 4 5 6

(20) (21) (22) (23) (24) (25) (26) (27)

7 + I 7 .

HASEGAWA AND AKAGI: NEW DC-VOLTAGE-BALANCING CIRCUIT INCLUDING INDUCTOR FOR PWM INVERTER

851

Since i has no dc component in a steady state, I 1 is equal to I 6 . Thus, by combining (20), (26), and (27), I 1 is given by I
1

1 (V 1 = (V =

H H

8 + V 8 + V

L L

7 + V 7 + V

H H

6 ) + I

6 ) I 1 .

(28)

Equation (28) results in I

1

1 {V H (8 + 6 ) + V 2

7 } .

(29)

Substituting (29) into (21) gives I

2

1 V

1 +

1 {V H (8 + 6 ) + V 2

7 } .

(30)

The dc component of iNM is given by INM = + I 2 1 2 2 V H (6 + 8 ) + V L (1 + 7 ) 1 . = 2 2 I

1

(31)

Substituting (18) into (31) yields INM = V H (2++ +2) 2 V L (3 ) + 2

. (32)

On the other hand, v has no dc component over a switching period. This makes the following relation valid: V H (2 + 4 + 6 + 8 ) + V L (1 + 3 + 5 + 7 ) = 0. (33) Substituting (18) into (33) gives V H (2 + + ) + V L (3 ) = 0. (34)

Equation (32) can be changed, along with considering (34), into the following: INM = 2V
H

V 2

(35)

Finally, substituting (19) into (35) results in INM = IPM = Vdc 2VQ 1 2 . (36)

[5] M. Saeedifard, R. Iravani, and J. Pou, Analysis and control of DCcapacitor-voltage-drift phenomenon of a passive front-end ve-level converter, IEEE Trans. Ind. Electron., vol. 54, no. 6, pp. 32553266, Dec. 2007. [6] S. Busquets-Monge, S. Alepuz, J. Rocabert, and J. Bordonau, Pulsewidth modulations for the comprehensive capacitor voltage balance of n-level three-leg diode-clamped converters, IEEE Trans. Power Electron., vol. 24, no. 5, pp. 13641375, May 2009. [7] Z. Pan and F. Z. Peng, A sinusoidal PWM method with voltage balancing capability for diode-clamped ve-level converters, IEEE Trans. Ind. Appl., vol. 45, no. 3, pp. 10281034, May/Jun. 2009. [8] N. Hatti, Y. Kondo, and H. Akagi, Five-level diode-clamped PWM converter connected back-to-back for motor drives, IEEE Trans. Ind. Appl., vol. 44, no. 4, pp. 12681276, Jul./Aug. 2008. [9] N. Hatti, K. Hasegawa, and H. Akagi, A 6.6-kV transformerless motor drive using a ve-level diode-clamped PWM inverter for energy savings of pumps and blowers, IEEE Trans. Power Electron., vol. 24, no. 3, pp. 796803, Mar. 2009. [10] H. Akagi, H. Fujita, S. Yonetani, and Y. Kondo, A 6.6-kV transformerless STATCOM based on a ve-level diode-clamped PWM converter: System design and experimentation of a 200-V, 10-kVA laboratory model, IEEE Trans. Ind. Appl., vol. 44, no. 2, pp. 672680, Mar./Apr. 2008. [11] H. Akagi and T. Hatada, Voltage balancing control for a three-level diode-clamped converter in a medium-voltage transformerless hybrid active lter, IEEE Trans. Power Electron., vol. 24, no. 3, pp. 571579, Mar. 2009. [12] H. Akagi and R. Kondo, A transformerless hybrid active lter using a three-level pulsewidth modulation (PWM) converter for a mediumvoltage motor drive, IEEE Trans. Power Electron., vol. 25, no. 6, pp. 13651374, Jun. 2010. [13] G. V. Torrico-Bascope and I. Barbi, A single phase PFC 3 kW converter using a three-state switching cell, in Conf. Rec. IEEE PESC, Jun. 2004, pp. 40374042. [14] W. Wen and Y. Lee, A two-channel interleaved boost converter with reduced core loss and copper loss, in Conf. Rec. IEEE PESC, Jun. 2004, pp. 10031009. [15] M. Hirakawa, M. Nagano, Y. Watanabe, K. Andoh, S. Nakatomi, and S. Hashino, High power density DC/DC converter using the close-coupled inductors, in Conf. Rec. IEEE ECCE, Sep. 2009, pp. 17601767. [16] S. Ogasawara and H. Akagi, Analysis of variation of neutral point potential in neutral-point-clamped voltage source PWM inverters, in Conf. Rec. IEEE IAS Annu. Meeting, Oct. 1993, vol. 2, pp. 965970. [17] H. Li, F. Z. Peng, and J. S. Lawler, A natural ZVS medium-power bidirectional DCDC converter with minimum number of devices, IEEE Trans. Ind. Appl., vol. 39, no. 2, pp. 525535, Mar./Apr. 2003. [18] F. Z. Peng, H. Li, G.-J. Su, and J. S. Lawler, A new ZVS bi-directional DCDC converter for fuel cell and battery application, IEEE Trans. Power Electron., vol. 19, no. 1, pp. 5465, Jan. 2004. [19] H. Fujita, S. Tominaga, and H. Akagi, Analysis and design of a DC voltage-controlled static var compensator using quad-series voltagesource inverters, IEEE Trans. Ind. Appl., vol. 32, no. 4, pp. 970977, Jul./Aug. 1996. [20] W. T. McLyman, Transformer and Inductor Design Handbook. New York: Marcel Dekker, 1988. [21] W.-J. Gu and R. Liu, A study of volume and weight vs. frequency for high-frequency transformers, in Conf. Rec. IEEE PESC, Jun. 1993, pp. 11231129.

The dc component of iPM can be obtained by means of the same procedure, which is equal to INM . R EFERENCES
[1] A. Nabae, I. Takahashi, and H. Akagi, A new neutral-point-clamped PWM inverter, IEEE Trans. Ind. Appl., vol. IA-17, no. 5, pp. 518523, Sep./Oct. 1981. [2] F. Z. Peng, J.-S. Lai, J. McKeever, and J. VanCoevering, A multilevel voltage-source converter system with balanced DC voltages, in Conf. Rec. IEEE PESC, Jun. 1995, pp. 11441150. [3] L. M. Tolbert, F. Z. Peng, and T. G. Habetler, Multilevel converters for large electric drives, IEEE Trans. Ind. Appl., vol. 35, no. 1, pp. 3644, Jan./Feb. 1999. [4] R. W. Menzies, P. Steimer, and J. K. Steinke, Five-level GTO inverters for large induction motor drives, IEEE Trans. Ind. Appl., vol. 30, no. 4, pp. 938944, Aug. 1994. Kazunori Hasegawa (S09) was born in Yokohama, Japan, in 1985. He received the B.S. degree in electrical engineering from Tokyo Metropolitan University, Tokyo, Japan, in 2007, and the M.S. degree in electrical and electronic engineering from Tokyo Institute of Technology, Tokyo, in 2009, where he is currently working toward the Ph.D. degree. Since 2010, he has been a Research Fellow of the Japan Society for the Promotion of Science. His research interests include diode-clamped multilevel converters. Mr. Hasegawa was the recipient of the IEEE International Power Electronics ConferenceSapporo Student Paper Award in 2010.

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IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 47, NO. 2, MARCH/APRIL 2011

Hirofumi Akagi (M87SM94F96) was born in Okayama, Japan, in 1951. He received the B.S. degree in electrical engineering from Nagoya Institute of Technology, Nagoya, Japan, in 1974, and the M.S. and Ph.D. degrees in electrical engineering from Tokyo Institute of Technology, Tokyo, Japan, in 1976 and 1979, respectively. In 1979, he joined Nagaoka University of Technology, Nagaoka, Japan, as an Assistant Professor, then becoming an Associate Professor in the Department of Electrical Engineering. In 1987, he was a Visiting Scientist at the Massachusetts Institute of Technology (MIT), Cambridge, for ten months. From 1991 to 1999, he was a Professor in the Department of Electrical Engineering, Okayama University, Okayama. From March to August of 1996, he was a Visiting Professor at the University of Wisconsin, Madison, and then at MIT. Since January 2000, he has been a Professor in the Department of Electrical and Electronic Engineering, Tokyo Institute of Technology. His research interests include power conversion systems, motor drives, active and passive electromagnetic-interference lters, high-frequency resonant inverters for induction heating and corona discharge treatment processes, and utility applications of power electronics such as active lters, self-commutated backto-back systems, and exible ac transmission systems devices. He has authored or coauthored more than 90 IEEE TRANSACTIONS papers and two invited papers published in the P ROCEEDINGS OF THE IEEE in 2001 and 2004. The total citation index for all his papers in Google Scholar is more than 12000. He has made presentations many times as a keynote or invited speaker internationally. Dr. Akagi was elected as a Distinguished Lecturer of the IEEE Power Electronics and IEEE Industry Applications Societies for 19981999. He was the recipient of ve IEEE TRANSACTIONS Prize Paper Awards and nine IEEE Conference Prize Paper Awards. He is the recipient of the 2001 IEEE William E. Newell Power Electronics Award, the 2004 IEEE Industry Applications Society Outstanding Achievement Award, and the 2008 IEEE Richard H. Kaufmann Technical Field Award. He served as the President of the IEEE Power Electronics Society for 20072008.