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CMOS Comparators CMOS Comparators

Fall 2008 S. Hoyos-ELEN-610 1 Fall 2009 1 S. Hoyos-ELEN-610


Comparator Comparator
i
o
th
Transfer characteristic
(ideal)
Circuit symbol
Detects the polarity of the analog input signal and produces a digital
output (1 or 0) correspondingly zero-crossing detector
Fall 2008 S. Hoyos-ELEN-610 2
output (1 or 0) correspondingly zero-crossing detector
Fall 2009 2 S. Hoyos-ELEN-610
Applications Applications
Voltage/current level comparison (A/D Voltage/current level comparison (A/D
conversion)
Di it l i ti i ( li Digital communication receivers (slicer
or decision circuit)
Memory sense amplifier
DC DC converter with digital control DC-DC converter with digital control
Fall 2008 S. Hoyos-ELEN-610 3 Fall 2009 3 S. Hoyos-ELEN-610
Design Considerations Design Considerations
Accuracy (offset, resolution) Accuracy (offset, resolution)
Sensitivity (gain)
Metastability (gain)
Settling time (small-signal BW, slew rate) g ( g , )
Overdrive recovery (memory)
CMRR CMRR
Power consumption
Fall 2008 S. Hoyos-ELEN-610 4
p
Fall 2009 4 S. Hoyos-ELEN-610
Comparator Comparator
V
th
V
i
V
th
V
o

Amplification Clipping
Precise gain and linearity are unnecessary simple, low-gain, open-loop,
wideband amplifiers + latch (positive feedback). deba d a p e s a c (pos e eedbac )
More gain can be derived by cascading multiple gain stages.
Built-in sampling function with latched comparators.
Fall 2008 S. Hoyos-ELEN-610 5 Fall 2009 5 S. Hoyos-ELEN-610
A Typical CMOS Comparator A Typical CMOS Comparator
V d i f
V
DD
V
os
derives from:
Preamp diff. pair
M
3
M
4
V
DD
M
5
M
6
mismatch (V
th
,W,L)
PMOS loads and
M
1
M
2
V
i
V
os
M
9

V
o
+
V
o
-
current mirror
Latch mismatch
M
8
M
7
V
SS
CI / CF imbalance
of M
9
V
SS
Preamp Latch
Fall 2009 S. Hoyos-ELEN-610 6
Clock routing
Parasitics
Latch Regeneration Latch Regeneration
V
DD
V
DD
M
5
M
6
M
9

V
o
+
V
o
-
C
L
C
L
M
8
M
7
V
SS
L L
Exponential regeneration due to positive feedback of M
7
and M
8
V
SS
Fall 2009 S. Hoyos-ELEN-610 7
p g p
7 8
Reg Speed Linear Model Reg. Speed Linear Model
V
+
V
-

M
8
M
7
C
L
C
L
V
o
+
V
o
M
8
M
7
1 1 | |
| |

+
+
V
V V
( ) l RHP i l C C / 0 1 / A
0
/ 1
1 1
/
=
|
|
.
|

\
|
|
|
.
|

\
|

=
=

+
+
o
o
L m
L o m o
o o
V
V
sC g
sC V g V
V V
( ) ( ) ( ). / exp 0 0
L m o o
C g t t V t V = = >
( ) pole, RHP single ,
L m p L m
C g s sC g s / 0 1 / = = = A
Fall 2009 S. Hoyos-ELEN-610 8
( ) ( ) ( ) p
L m o o
g
Reg Speed Linear Model Reg. Speed Linear Model
V
+
V
-
M
8
M
7
C
L
C
L
V
o
+
V
o
V
o
= 1V
V
o
(t=0)
t
M
8
M
7
o
( )
(
(

= ln
t V C
t
o L
V
o
V
o
(t=0)
t/(C
L
/g
m
)
1V 100mV 2.3
( )
(

=
=
0
ln
t V g
t
o m
1V 10mV 4.6
1V 1mV 6.9
Fall 2009 S. Hoyos-ELEN-610 9
1V 100V 9.2
Reg Speed Linear Model Reg. Speed Linear Model
+
M
5
M
6
=1
V
o
+
V
o
-
V
m
+
V
m
-
x
M
8
M
7
M
9
gain. positive for 2 <

=
9 7 m
9 7 m
9 5 m
2 V
R g
R g 2
R g
A ,
3
1
1
m
m
V
g
g
A =
( ) ( ) ( )
2 V 1 V i V i o
A A 0 V A 0 V 0 V = =
( ) ( ) ( ) C t A A V t V / e p 0
Fall 2009 S. Hoyos-ELEN-610 10
( ) ( ) ( )
L m V V i o
C g t A A V t V / exp 0
2 1
=
Comparator Metastability Comparator Metastability
( ) ( ) ( )
L m V V i o
C g t A A V t V / exp 0
2 1
=
Curve A
V1
A
V2
V
i
(t=0)
10 10mV
10 1mV 10 1mV
10 100V
10 10V
Comparator fails to produce valid logic outputs within T/2 when input falls
i t i th t i ffi i tl l t th t th h ld
Fall 2009 S. Hoyos-ELEN-610 11
into a region that is sufficiently close to the comparator threshold.
Metastability Metastability
LSB 1

BER =
LSB 1
( ) ( ) ( )
L m V V i o
C g t A A V t V / exp 0
2 1
=
Cascade preamp stages (typical flash comparator has 2-3 PA stages).
Use pipelined multi-stage latches; PA can be pipelined too.
Fall 2009 S. Hoyos-ELEN-610 12
Avoid branching off the comparator logic output.
CI and CF in Latches CI and CF in Latches
Charge injection and clock feedthrough introduce CM jump
i V
+
d V
Fall 2009 S. Hoyos-ELEN-610 13
in V
o
+
and V
o
-
.
Dynamic latches are more susceptible to CI and CF errors.
Dynamic Offset of Latches Dynamic Offset of Latches
Dynamic offset derives from: Dynamic offset derives from:
Imbalanced CI and CF
Imbalanced load capacitance Imbalanced load capacitance
Mismatch b/t M
7
and M
8
Mismatch b/t M
5
and M
6
o
+
Clock routing
o
o
-
offset 50mV
imbalance 10%
jump CM 0.5V

)
`

imbalance 10%
)
Dynamic offset is usually the dominant offset in latches
Fall 2009 S. Hoyos-ELEN-610 14
Dynamic offset is usually the dominant offset in latches.
Typical CMOS Comparator Typical CMOS Comparator
Input referred latch
V
DD
Input-referred latch
offset gets divided by
the gain of PA.
V
os
M
3
M
4
M
5
M
6

Preamp introduces
its own offset (mostly
static due to V
th
W
M
1
M
2
V
i
V
os
M M
M
9
V
o
+
V
o
-
static due to V
th
, W,
and L mismatches).
PA also reduces
M
8
M
7
V
SS
kickback noise. Preamp Latch
Kickback noise disturbs the reference voltages, must settle before next T.
Fall 2009 S. Hoyos-ELEN-610 15
g ,
CMOS Preamplifier CMOS Preamplifier
Fall 2009 S. Hoyos-ELEN-610 16
Pull-Up Pull Up
( ) L W
- : up pull diode NMOS
o
+
o
-
( )
( )
L mL
m
V
L W
L W
g
g
A
1 1
= =
- : up pull diode PMOS
M
1
M
2
i
+
i
-
( )
( )
L p
n
mL
m
V
L W
L W
g
g
A
1 1

= =
- : up pull Resistor
NMOS ll ff f b d ff t ff ti i tti
L m V
R g A =
-
1
: up pull Resistor
NMOS pull-up suffers from body effect, affecting gain setting accuracy.
PMOS pull-up has no body effect, but is subject to P/N matching.
Gain accuracy is the worst for resistive pull-up as resistors (poly, diffusion,
Fall 2009 S. Hoyos-ELEN-610 17
well, and etc.) dont track transistors.
To Obtain More Gain To Obtain More Gain
I diverts current away
M
3
M
4
o
+
o
-
p p
I
p
diverts current away
from PMOS diodes (M
3
& M
4
), reducing (W/L)
3
.
M
1
M
2
i
+
i
-
Higher gain, no CMFB
Needs biasing for I
p
M & M t ff f M
3
& M
4
may cut off for
large V
in
, resulting in
long recovery time.
( )
( )
3
1
3
1
2
2
L W
L W
I I
I
g
g
A
p p
n
m
m
V
|
|
.
|

\
|

~ =

Fall 2009 S. Hoyos-ELEN-610 18


( )
3 p p
. \
Bults Preamp Bult s Preamp
NMOS diff pair loaded NMOS diff. pair loaded
with PMOS diodes and
PFB PMOS pair
M
3
M
4
o
+
o
-
M
5
M
6
High DM gain, low CM
gain, good CMRR
Simple no CMFB
M
1
M
2
i
+
i
-
Simple, no CMFB
(W/L)
34
> (W/L)
56
needs
to be ensured for
M
7
stability.
Ref: K. Bult and A. Buchwald, "An embedded 240-mW 10-b 50-MS/s CMOS ADC in
Fall 2009 S. Hoyos-ELEN-610 19
Ref: K. Bult and A. Buchwald, An embedded 240 mW 10 b 50 MS/s CMOS ADC in
1-mm
2
," IEEE Journal of Solid-State Circuits, vol. 32, pp. 1887-1895, issue 12,
1997.
Bults Preamp (DM) Bult s Preamp (DM)

M
3
M
4
V
o
+
V
o
-
M
5
M
6
M
1
M
2
M
7
V
i
+
V
i
-
M
7
3
// // //
1
//
1
1 1
5 3 1
5 3
1
o m
o o o
m m
m
dm
V
r g
r r r
g g
g A ~
(

|
|
.
|

\
|
= : gain DM
Fall 2009 S. Hoyos-ELEN-610 20
Bults Preamp (CM) Bult s Preamp (CM)

1
g
m3
1
g
m5
M
3
M
4
V
o
+
V
o
-
M
5
M
6
V
ic
g
m1
V
gs1
2r
o7
V
oc
V
gs1
M
1
M
2
M
7
V
i
+
V
i
-
M
7
( )
7 5 3 5 3 7 1
1
2
1 1
//
1
2 1
o m m m m o m
m
cm
V
r g g g g r g
g
A
+
~
|
|
.
|

\
|

+
= : gain CM
Fall 2009 S. Hoyos-ELEN-610 21
Songs Preamp Song s Preamp
NMOS diff. pair loaded
with PMOS diodes and
M
4
M
3
+ -
R
L
R
L
a pair of resistors
High DM gain, low CM
gain good CMRR
M
1
M
2
i
+
i
-
o o
X
gain, good CMRR
Simple, no CMFB
Gain depends on precision
M
5
of R
L
Fall 2009 S. Hoyos-ELEN-610 22
Ref: B.-S. Song et al., "A 1 V 6 b 50 MHz current- interpolating CMOS ADC," in
Symposium on VLSI Circuits Digest of Technical Papers, 1999, pp. 79-80.
Songs Preamp (CM) Song s Preamp (CM)
1
V
i
g
m1
V
gs1
g
m3
V
V
gs1
V
ic
2r
o5
V
oc
1
1
m
cm
g
A =
DM CM
( )
L o o m
dm
V
R r r g A
3 1 1
// // =
5 3
3 5 1
2
1
2 1
o m
m o m
V
r g
g r g
A
~

+
=
( )
L m
L o o m V
R g
g
1
3 1 1
~
Fall 2009 S. Hoyos-ELEN-610 23
CMOS Latch CMOS Latch
Fall 2009 S. Hoyos-ELEN-610 24
Static Latch Static Latch
Active pull-up and
pull-down full CMOS
logic levels
Very fast! i
+
i
-
M
1
M
2
M
3
M
4
Q
+
and Q
-
are not well
defined in reset mode
( = 1).
+ -

M
1
M
2
( )
Large short-circuit
current in reset mode.
Zero DC current after
M
6
M
5
M
7
+
Zero DC current after
full regeneration
Very noisy
Fall 2009 S. Hoyos-ELEN-610 25
Semi-Dynamic Latch Semi Dynamic Latch
Di d di id di bl d Diode divider disabled
in reset mode less
short-circuit current
M
8
+ -
M
3
M
4
Pull-up not as fast
Q
+
and Q
-
are still not
ll d fi d i t

i i
M
1
M
2
+
well defined in reset
mode ( = 1).
Zero DC current after
M
6
M
5
M
7
+ -
full regeneration
Still very noisy
M
6
M
5
Fall 2009 S. Hoyos-ELEN-610 26
Current-Steering Latch Current Steering Latch
Constant current
very quite
M
7

R
L
R
L
Q
+
Q
-
Higher gain in
tracking mode
Cannot produce
M
1
M
2
V
i
+
V
i
-
M
4
M
3
M
7
Cannot produce
full logic levels
Fast
M
5
M
6
M

Trip point of the
inverters
M
8
Fall 2009 S. Hoyos-ELEN-610 27
Dynamic Latch Dynamic Latch
Zero DC current in
reset mode
Q
+
and Q
-
are both
M
7
M
8
M
5
M
6
Q
+
Q

Q and Q are both
precharged to 0.
Full logic level after

Q
+
Q
-
M
9
M
10

regeneration
stability.
Slow
M
4
M
3
V
i
+
V
i
-
M
1
M
2
Slow
Ref: A. Yukawa, "A CMOS 8-Bit High-Speed A/D Converter IC," IEEE Journal of Solid-
State Circuits, vol. 20, pp. 775-779, issue 3, 1985.
Fall 2009 S. Hoyos-ELEN-610 28
State Circuits, vol. 20, pp. 775 779, issue 3, 1985.
Modified Dynamic Latch Modified Dynamic Latch
Zero DC current in
reset mode
Q
+
and Q
-
are both Q and Q are both
precharged to 0.
Full logic level after
regeneration
stability.
Slow
Ref: T. B. Cho and P. R. Gray, "A 10 b, 20 Msample/s, 35 mW pipeline A/D converter,
Slow
Fall 2009 S. Hoyos-ELEN-610 29
IEEE Journal of Solid-State Circuits, vol. 30, pp. 166-172, issue 3, 1995.
Chos Comparator Cho s Comparator
( ) ( )
( ) ( )
(
(

+ ' =
+
th R
R
th i
i
W W
V V
L
W
V V
L
W
k G
1
M
7
M
8
M
5
M
6
Q
+
Q

( ) ( )
(

+ ' =
+
th R
R
th i
i
V V
L
W
V V
L
W
k G
2

Q
+
Q
-
M
9
M
10

M M
( )
+
=
R R
i
R
V V
W
W
Threshold
M
2R
M
1R V
i
+
V
i
-
M
1
M
2
M
4
M
3
M and M added to set the decision threshold
V
R
-
V
R
+
Fall 2009 S. Hoyos-ELEN-610 30
M
1R
and M
2R
added to set the decision threshold
Regenerative Sense Amplifier (RSA) Regenerative Sense Amplifier (RSA)
Offset cancellation
Fast
AC coupling reduces
signal gain signal gain.
CM feedback?
Ref: J.-T. Wu and B. A. Wooley, "A 100-MHz pipelined CMOS comparator," IEEE
Fall 2009 S. Hoyos-ELEN-610 31
Journal of Solid-State Circuits, vol. 23, pp. 1379-1385, issue 6, 1988.
DM Equivalent Circuit DM Equivalent Circuit
Sensing Resetting
M
1
V
i
+
M
1
g g
M
5
V
o
+
M
5
V
o
+
V
o
+
M
3 X
-1
Y
X
M
3
-1
Y
DM loopgain in resetting mode is less than 1
Fall 2009 S. Hoyos-ELEN-610 32
DM loopgain in resetting mode is less than 1.
CM Equivalent Circuit CM Equivalent Circuit
ic
M
1
M
5
oc
M3 degenerated
Loopgain < 1 ?
X
M
3
Needs CMFB
Fall 2009 S. Hoyos-ELEN-610 33
RSA Common-Mode Feedback RSA Common Mode Feedback
V
i
+
V
i
-
M
1
M
2

M
6
M
5


V
+
V
-
M
4
M
3
M
7
V
o
V
o
M
8 7
M
10
M
9
8
Fall 2009 S. Hoyos-ELEN-610 34
Comparator Offset Comparator Offset
V
DD
M M
V
os
M
3
M
4
M
5
M
6

V
o
+
V
o
-
( )
(
(

|
.
|

\
|
A
+
|
.
|

\
|
A
+ A =
2 2
2 2 2
1 L W
V V V
ov th os
Differential pair mismatch:
M
1
M
2
V
i
M
8
M
7
M
9
( )
(
(

|
.

\
|
.

\
4 L W
ov th os
9 5
2
2 R
R g
A
m
V
=
1
1
m
V
g
A =
V
SS
Preamp Latch
9 7
2
2 R g
m
V

3
1
m
V
g
2
2
2
1
2
,
2
2
2
1
2
78 ,
2
1
2
56 ,
2
34 , 2
12 ,
2
V V
dyn os
V V
os
V
os os
os os
A A
V
A A
V
A
V V
V V + +
+
+ =
Total input-referred
comparator offset:
Fall 2009 S. Hoyos-ELEN-610 35
Matching Properties Matching Properties
The variance of parameter P b/t two rectangular devices:
( ) ,
2
2
2
2
D S
WL
A
P
P
P
+ = A o
The variance of parameter P b/t two rectangular devices:
1
st
term dominates
for small devices.
where, W and L are the effective width and length, D is distance.
2
A
( )
( )
.
,
2
2
2
2
2
2
2
0
0
0
2
D S
WL
A
D S
WL
A
V
VT
VT
T
|
|
|
| o
o
+ =
+ =
: factor Current
: Threshold
Ref: M. J. M. Pelgrom, et al., "Matching properties of MOS transistors," IEEE Journal
2
WL
|
|
Fall 2009 S. Hoyos-ELEN-610 36
of Solid-State Circuits, vol. 24, pp. 1433-1439, issue 5, 1989.
Why Large Devices Match Better? Why Large Devices Match Better?
R
1
R
2
. ,
1 1 R S
W
L
R R o std with = , , 10 10
2 1 2 R S
R
W
L
R R o =
|
.
|

\
|
= std with
. 10 10
1 2
2
1
10
1
2 2
2 R R R
j
R R
j
o o o o o = = =

=
.
1 1
10
1
10
10
1
1
1
1
2
2
WL A
R R R R
R R R R
=
|
|
.
|

\
|
= =
o o o o
Spatial
averaging
Fall 2009 S. Hoyos-ELEN-610 37
ADC Input Capacitance ADC Input Capacitance
( )
2
2
0
2
/ 10 m fF C
A
V
VT
o = = ( )
0
/ 10 m fF C
WL
V
g T
o = =
N = 6 bits 63 comparators
# of
V
FS
= 1V
= LSB/4
1 LSB = 16mV
= 4mV
N (bits)
# of
comp.
C
in
(pF)
6 63 3.9
A
VT0
= 10mVm L = 0.24m,
W = 26m
8 255 250
10 1023 ??!
Small V
os
leads to large device sizes, hence large area and power.
Large comparator leads to large input capacitance, difficult to drive and
Fall 2009 S. Hoyos-ELEN-610 38
Large comparator leads to large input capacitance, difficult to drive and
difficult to maintain bandwidth.
Multi-Stage Preamp Multi Stage Preamp
( ) ,
/ 1
0
0
j
A
A
+
=
e e
e
. /
, / 1
0 0 0
0
L L u
L L
C R A A
C R
= =
=
e e
e
( )
0 0
|
|
|

|
=
|
|
|

|
=
N
N
A A
A e ( )
( )
( ) . 1 2 ,
2
,
/ 1
/ 1
1
0 3
0
3
2
0
0
= = =
|
.

\
+
=
|
|
.

\
+
=

N
dB
N
dB N
N
A
A
j
A
e e e e
e e
e e
e
N stages:
Fall 2009 S. Hoyos-ELEN-610 39
( )
2
0 3 3 dB dB N
Step Response Step Response
( ) e A V V
t
=
t
1
/
( )
( )
C R
t
R g V
t for t A V
e A V V
L m in
in
in
=
<< ~
=
t t , /
1
0
0 1
t
C
g
V
C R
L
m
in
L L
=
Ignore R in all stages:
,
2
1 1
,
1
2
2
1 2 1 in
m
t
m in
m
t
in m
t V
C
g
dt V g
C
V t V
C
g
dt V g
C
V
|
|
.
|

\
|
= = = =
} }
Ignore R
L
in all stages:
.
!
1
,
2
0
1
0 0
in
N
L
m
N
t
N m
L
N N
L L L L
V
C
g
N
t
dt V g
C
V V
C C C C
|
|
.
|

\
|
= =
. \
}

smal for
Fall 2009 S. Hoyos-ELEN-610 40
Optimum N Optimum N
10
2
V
o
/V
i
=10
i
N
L
m
N
o
o
V
C
g
N
t
V
, V
|
|
.
|

\
|
=
!
small For
V
o
/V
i
=100
V
o
/V
i
=1000
L
C N
. \
!
10
1
t
/
(
C
L
/
g
m
)
N
o L
V
N
C
t
1
!
(
(

|
|
|

|
10
0
i
o
m
L
V
N
g
t !
(

|
|
.

\
=
1 2 3 4 5 6 7 8 9 10
10
N
Given A
0
= V
o
/V
i
, N
opt
can be determined with the above equation.
Fall 2009 S. Hoyos-ELEN-610 41
For A
0
< 100, typical N value ranges between 2 and 4.
Comparison Comparison
10
N
o L
V
V
N
g
C
t
1
!
(

|
|
.
|

\
|
=
6
8
|
|
|

|
o L
V C
t l : latch
i m
V g

. \
4
6
t
/
(
C
L
/
g
m
)
|
|
.

\
=
i
o
m
L
V g
t ln : latch
0
2
N=1
N=3
N=5
Latch
A higher A
0
(= V
o
/V
i
) requires a larger N.
10
0
10
1
10
2
10
3
0
V
o
/V
i
Fall 2009 S. Hoyos-ELEN-610 42
In comparison, latches regenerate (PFB) faster than preamp.
Multi-Stage PA Offset Multi Stage PA Offset
Individual stage

Total input-referred

A
V
os
A A A
1
A
2
A
3
A A A A =
.
,
2 1
3
1
2
1
3 2 1
A A
V
A
V
V V
A A A A
os os
os os
T

+ + =
=
Fall 2009 S. Hoyos-ELEN-610 43
Input Offset Cancellation Input Offset Cancellation
AC coupling at input with input-referred offset stored in C.
Two-phase operation, one phase (
2
) is used to store offset.
Fall 2009 S. Hoyos-ELEN-610 44
Offset Storage
2
Offset Storage
2
2

( )
os
os c c
V
A
A
V V A V
=
=
1
os
o
c

os
os
V
A
~
+ 1
2
Closed-loop stability (amplifier in unity-gain feedback)
Ref: J. L. McCreary and P. R. Gray, "All-MOS charge redistribution analog-to-digital
conversion techniques. I," IEEE Journal of Solid-State Circuits, vol. 10, pp. 371-
379 issue 6 1975
Fall 2009 S. Hoyos-ELEN-610 45
379, issue 6, 1975.
Amplifying Phase
1
Amplifying Phase
1

( )
|
.
|

\
|
+
=
+ =
A
V
V A
V V V A V
os
in
os c in o
1
os 1
i
o
c
. \
+ A 1
V
A
V
os
+
=
1
offset referred Input
Offset cancellation is incomplete if A is finite.
AC coupling at input attenuates signal gain
Fall 2009 S. Hoyos-ELEN-610 46
AC coupling at input attenuates signal gain.
CF and CI of Switches CF and CI of Switches
2
os
2
o
c

1
2
o

2
'
2
Whats the optimum phase relationship between
2
and
2
'?
Bottom-plate sampling
2
' switches off slightly before
2
.
Fall 2009 S. Hoyos-ELEN-610 47
2 2
Multi-Stage Input Offset
Cancellation

4
A
1
V
os1

2
V
i
C
1
A
2
V
os2
V
o
C
2
A
2
Multi stage AC coupling Multi-stage AC coupling

3
switches off first
V
1
on C
1
will be
absorbed by C
2
.

4
switches off next,
2
last
Fall 2009 S. Hoyos-ELEN-610 48
last.
Output Offset Cancellation Output Offset Cancellation
AC coupling at output with offset stored in C. AC coupling at output with offset stored in C.
A must be small and well controlled (independent of V
o
).
Does not work for high-gain op-amps
Fall 2009 S. Hoyos-ELEN-610 49
Does not work for high gain op amps.
Offset Storage
2
Offset Storage
2

( )
os os c
AV V A V = =
Closed-loop stability is not required.
CF and CI of
2
' gets divided by A when referred to input.
Ref: R. Poujois and J. Borel, A low drift fully integrated MOSFET operational amplifier,
IEEE Journal of Solid-State Circuits, vol. 13, pp. 499-503, issue 4, 1978.
Fall 2009 S. Hoyos-ELEN-610 50
Amplifying Phase
1
Amplifying Phase
1
1 os 1
i
o
c 1

( )
os os i o
AV
AV V V A V + =
0 = offset referred Input

in
AV =
Cancellation is complete if A is constant (independent of V
o
).
AC coupling at output attenuates signal gain.
Fall 2009 S. Hoyos-ELEN-610 51
AC coupling at output attenuates signal gain.
Multi-Stage Output Offset Cancellation Multi Stage Output Offset Cancellation
M lti t AC li Multi-stage AC coupling

3
switches off first
V on C will be V
1
on C
1
will be
absorbed by C
2
.
switches off next
Fall 2009 S. Hoyos-ELEN-610 52

4
switches off next,
2
last.
Overdrive Recovery Overdrive Recovery
Fall 2009 S. Hoyos-ELEN-610 53
Overdrive Recovery Test Overdrive Recovery Test

V
i
V
i
= V
FS
V
i
= -LSB/2
V
i
V
i
= V
FS
V
i
= LSB/2
V
o
+
V
o
V
o
+
V
o
0 1
V
o
-
V
o
-
0 1
Case I Case II
A small input (0.5 LSB) is applied to the comparator input in a cycle right
after a FS input (the largest possible input) was applied; the comparator
Fall 2009 S. Hoyos-ELEN-610 54
should be able to resolve to the right output in either case.
Passive Clamp Passive Clamp
Limit the output swing
M
3
M
4
+
with diode clamps at
output.
Signal-dependent R
+ -
M
6
M
5
o
+
o
-
Signal-dependent R
o
Clamps add parasitics
to the PA output.
M
1
M
2
i
+
i
-
Fall 2009 S. Hoyos-ELEN-610 55
Active Reset Active Reset
Kill PA gain with a
M
3
M
4
+
g
switch (M
5
).
Time-dependent R
M M
+ -
M
5
o
+
o
-
Time-dependent R
o
M
5
adds parasitics to
th PA t t
M
1
M
2
i
+
i
-
the PA output.
Fall 2009 S. Hoyos-ELEN-610 56
PA Autozeroing PA Autozeroing
M
3
M
4
V
o
+
V
o
-

2
'
M
1
M
2
V
i
+
V
i
-
M
5
M
6
Two-phase operation,
2
phase is used for offset storage.
Autozeroing switch
2
' also resets and removes the memory of PA.
Fall 2009 S. Hoyos-ELEN-610 57
g
2
y

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