CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Data sheet acquired from Harris Semiconductor SCHS189A

January 1998 - Revised May 2000

High Speed CMOS Logic Octal Buffer and Line Drivers, Three-State
Description
The HC540 and CD74HCT540 are Inverting Octal Buffers and Line Drivers with Three-State Outputs and the capability to drive 15 LSTTL loads. The HC541 and HCT541 are NonInverting Octal Buffers and Line Drivers with Three-State Outputs that can drive 15 LSTTL loads. The Output Enables (OE1) and (OE2) control the Three-State Outputs. If either OE1 or OE2 is HIGH the outputs will be in the high impedance state. For data output OE1 and OE2 both must be LOW.

Features
HC540, CD74HCT540 . . . . . . . . . . . . . . . . . . . Inverting

[ /Title (CD74 HC540 , CD74 HCT54 0, CD74 HC541 , CD74 HCT54

HC541, HCT541 . . . . . . . . . . . . . . . . . . . . . . .Non-Inverting Buffered Inputs Three-State Outputs Bus Line Driving Capability Typical Propagation Delay = 9ns at VCC = 5V, CL = 15pF, TA = 25oC Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Signicant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il 1A at VOL, VOH

Ordering Information
PART NUMBER CD54HC540F3A CD74HC540E CD74HC540M CD74HCT540E CD74HCT540M CD54HC541F3A CD74HC541E CD74HC541M CD54HCT541F CD54HCT541F3A CD74HCT541E CD74HCT541M TEMP. RANGE (oC) -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 -55 to 125 PACKAGE 20 Ld CERDIP 20 Ld PDIP 20 Ld SOIC 20 Ld PDIP 20 Ld SOIC 20 Ld CERDIP 20 Ld PDIP 20 Ld SOIC 20 Ld CERDIP 20 Ld CERDIP 20 Ld PDIP 20 Ld SOIC

NOTES: 1. When ordering, use the entire part number. Add the sufx 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all electrical specifications. Please contact your local TI sales office or customer service for ordering information.

Pinouts
CD54HC540 (CERDIP) CD74HC540, CD74HCT540 (PDIP, SOIC) TOP VIEW
OE A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 20 VCC 19 OE2 18 Y0 17 Y1 16 Y2 15 Y3 14 Y4 13 Y5 12 Y6 11 Y7

CD54HC541, CD54HCT541 (CERDIP) CD74HC541, CD74HCT541 (PDIP, SOIC) TOP VIEW

OE1 A0 A1 A2 A3 A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 20 VCC 19 OE2 18 Y0 17 Y1 16 Y2 15 Y3 14 Y4 13 Y5 12 Y6 11 Y7

GND 10

GND 10

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

2000, Texas Instruments Incorporated

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Functional Diagram

OEA OEB 540 D0 Y0 541 Y0

D1

Y1

Y1

D2

Y2

Y2

D3

Y3

Y3

D4

Y4

Y4

D5

Y5

Y5

D6

Y6

Y6

D7

Y7

Y7

TRUTH TABLE INPUTS OE1 L H X L OE2 L X H L An H X X L 540 L Z Z H OUTPUTS 541 H Z Z L

NOTE: H = HIGH Voltage Level L = LOW Voltage Level X = Dont Care Z = High Impedance

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Absolute Maximum Ratings
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .35mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .25mA DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .50mA

Thermal Information
Thermal Resistance (Typical, Note 3) JA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)

Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC Supply Voltage Range, VCC HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC Input Rise and Fall Time 2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max) 4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max) 6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specication is not implied.

NOTE: 3. JA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specications
TEST CONDITIONS PARAMETER HC TYPES High Level Input Voltage VIH 2 4.5 6 Low Level Input Voltage VIL 2 4.5 6 High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current II VCC or GND VOL VIH or VIL VOH VIH or VIL -0.02 -0.02 -0.02 -6 -7.8 0.02 0.02 0.02 6 7.8 2 4.5 6 4.5 6 2 4.5 6 4.5 6 6 1.5 3.15 4.2 1.9 4.4 5.9 3.98 5.48 0.5 1.35 1.8 0.1 0.1 0.1 0.26 0.26 0.1 1.5 3.15 4.2 1.9 4.4 5.9 3.84 5.34 0.5 1.35 1.8 0.1 0.1 0.1 0.33 0.33 1 1.5 3.15 4.2 1.9 4.4 5.9 3.7 5.2 0.5 1.35 1.8 0.1 0.1 0.1 0.4 0.4 1 V V V V V V V V V V V V V V V V V V A SYMBOL VI (V) IO (mA) VCC (V) 25oC MIN TYP MAX -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX UNITS

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

DC Electrical Specications
(Continued) TEST CONDITIONS PARAMETER Quiescent Device Current Three- State Leakage Current HCT TYPES High Level Input Voltage Low Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads Low Level Output Voltage TTL Loads Input Leakage Current Quiescent Device Current Three- State Leakage Current Additional Quiescent Device Current Per Input Pin: 1 Unit Load II ICC IOZ VCC and GND VCC or GND VIL or VIH VOL VIH or VIL VIH VIL VOH VIH or VIL -0.02 4.5 to 5.5 4.5 to 5.5 4.5 2 4.4 0.8 2 4.4 0.8 2 4.4 0.8 V V V SYMBOL ICC IOZ VI (V) VCC or GND VIL or VIH IO (mA) 0 VO = VCC or GND 25oC MIN TYP MAX 8 0.5 -40oC TO 85oC -55oC TO 125oC MIN MAX 80 5.0 MIN MAX 160 10 UNITS A A

VCC (V) 6 6

-6

4.5

3.98

3.84

3.7

0.02

4.5

0.1

0.1

0.1

4.5

0.26

0.33

0.4

0 0 VO = VCC or GND -

5.5 5.5 5.5

0.1 8 0.5

1 80 5.0

1 160 10

A A A

ICC

VCC -2.1

4.5 to 5.5

100

360

450

490

NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specication is 1.8mA.

HCT Input Loading Table

UNIT LOADS INPUT A0 - A7 OE2 OE1 HCT540 1 0.75 1.15 HCT541 0.4 0.75 1.15

NOTE: Unit load is ICC limit specic in DC Electrical Specications Table, e.g., 360A max. at 25oC.

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Switching Specications
CL = 50pF, Input tr, tf = 6ns 25oC VCC (V) MIN TYP MAX -40oC TO 85oC MIN MAX -55oC TO 125oC MIN MAX UNITS

PARAMETER HC TYPES Propagation Delay Data to Outputs (540)

SYMBOL

TEST CONDITIONS

tPLH, tPHL

CL = 50pF 2 4.5 CL = 15pF CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF 5 6 2 4.5 CL = 15pF CL = 50pF 5 6 2 4.5 6 10 20 9 9 13 14 50 48 110 22 19 115 23 20 160 32 27 160 32 23 60 12 10 10 20 140 28 24 145 29 25 200 40 34 200 40 29 75 15 13 10 20 165 33 28 175 35 30 240 48 41 240 48 35 90 18 15 10 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF pF pF pF

Data to Outputs (541)

tPLZ, tPHZ

CL = 50pF

Output Enable and Disable to Outputs (540)

tPLZ, tPHZ

CL = 50pF

Output Enable and Disable to Outputs (541)

tPLZ, tPHZ

CL = 50pF

Output Transition Time

tTHL, tTLH

CL = 50pF

Input Capacitance Three-State Output Capacitance Power Dissipation Capacitance (Notes 4, 5) (540) Power Dissipation Capacitance (Notes 4, 5) (541) HCT TYPES Propagation Delay Data to Outputs (540)

CI CO CPD CPD

CL = 50pF CL = 15pF CL = 15pF

5 5

tPHL, tPLH CL = 50pF CL = 15pF 4.5 5 4.5 5 4.5 5 4.5 10 9 11 14 24 28 35 12 10 30 35 44 15 10 36 42 53 18 10 ns ns ns ns ns ns ns pF

Data to Outputs (541)

tPHL, tPLH

CL = 50pF CL = 15pF

Output Enable and Disable to Outputs (540, 541) Output Transition Time Input Capacitance

tPLZ, tPHZ

CL = 50pF CL = 15pF

tTLH, tTHL CI

CL = 50pF CL = 50pF

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Switching Specications
CL = 50pF, Input tr, tf = 6ns (Continued) 25oC VCC (V) 5 MIN 20 TYP 55 MAX 20 -40oC TO 85oC MIN MAX 20 -55oC TO 125oC MIN MAX 20 UNITS pF pF

PARAMETER Three-State Output Capacitance Power Dissipation Capacitance (Notes 4, 5) (540, 541) NOTES:

SYMBOL CO CPD

TEST CONDITIONS CL = 15pF

4. CPD is used to determine the dynamic power consumption, per channel. 5. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Test Circuits and Waveforms

tr = 6ns INPUT 90% 50% 10% tTLH 90% 50% 10% tPHL tPLH tf = 6ns VCC INPUT GND tTHL tr = 6ns 2.7V 1.3V 0.3V tTLH 90% INVERTING OUTPUT tPHL tPLH 1.3V 10% tf = 6ns 3V

GND

tTHL

INVERTING OUTPUT

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC

6ns OUTPUT DISABLE 90% 50% 10% tPZL 50% 10% tPHZ OUTPUT HIGH TO OFF OUTPUTS ENABLED 90% 50% OUTPUTS DISABLED OUTPUTS ENABLED tPZH 6ns VCC GND

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC
tr OUTPUT DISABLE 6ns tf 2.7 1.3 tPLZ OUTPUT LOW TO OFF tPHZ OUTPUT HIGH TO OFF OUTPUTS ENABLED 90% 6ns 3V 0.3 tPZL GND

tPLZ OUTPUT LOW TO OFF

10% tPZH

1.3V

1.3V OUTPUTS DISABLED OUTPUTS ENABLED

FIGURE 3. HC THREE-STATE PROPAGATION DELAY WAVEFORM

FIGURE 4. HCT THREE-STATE PROPAGATION DELAY WAVEFORM

CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541 Test Circuits and Waveforms

(Continued)

OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE

IC WITH THREESTATE OUTPUT

OUTPUT RL = 1k CL 50pF

VCC FOR tPLZ AND tPZL GND FOR tPHZ AND tPZH

NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1k to VCC, CL = 50pF. FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

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Copyright 2000, Texas Instruments Incorporated