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EL 302
Digital Integrated Circuits

Project
CMOS Static RAM Design

E.Selin Baytok
8088





15.06.2007





Purposes:

Designing a single bit cell that has a row select input, and, BIT and BIT- outputs with smallest
possible transistor sizes.
Making schematic simulations, ensuring that 0 and 1 can be properly written into the cell.
Design oI a rectangularly shaped layout which can be easily cascaded both horizontally and vertically.
Measuring the input capacitance oI the cell seen Irom the bit line, and the column line.
Calculating the cell-to-cell resistance Ior the column and bit lines.
Measuring the time delay Irom the column decoder output to the bit output oI the cell is at the upper
right corner oI a 64 kBit SRAM array which uses a simple 5-transistor diIIerential stage as output
ampliIier.

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1. Introduction

Static Random Access Memory (SRAM) is a semiconductor volatile data storage unit which contains
the data placed as long as the electrical power is supplied. Unlike dynamic memories data inside does not
need to be reIreshed since the leakage Iactor does not aIIect them as it does in dynamic ones. ThereIore
SRAM`s are less power consuming devices besides their speed. But because oI their large area requirements
they can not be arranged in a dense Iormat.



Fig 1 Full CMOS SRAM

2. Schematic Design

2.1. Calculations

Throughout the schematic design oI SRAM cell the main criteria was to be able to properly execute
the read and write operations oI the '0 data. It was required to keep the soIt node capacitance voltage on the
bit line (C )side below the threshold value oI the nmos transistor in the latch conIiguration throughout the
read operation while doing the same Ior the soIt node capacitance voltage on the bit line not (C` )side through
write operation. Also it is required not to destroy the stored value on the soIt node. In order to do that in read
operation aspect ratios oI the nmos transistors are calculated according to the Iollowing Iormula:


(2(3.3-1.5*0.56)0.56)/((3.3-2*0.56)`2)
0.58

In order to be able to write '0 value aIter a '1 value aspect ratios oI the pass transistor and pmos transistor
are calculated according to the Iollowing Iormula:
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(2(3.3-1.5*0.56)0.56)/((3.3-0.73)`2)
1.235

ThereIore:

0.684*M11.2*M3M5

Since the minimum possible transistor values are required ** s W/L is selected as 0.4u /0.35u (minimum
possible transistor value that 0.35u technology allows).

M1 M3 M5
W/L 0.6u /0.35u 0.4u /0.35u 0.5u /0.35u

Table 1 SRAM Cell Transistor Values




Fig 2 Schematic View oI SRAM Cell

2.2. Schematic Simulations

In order to test cells the conIiguration in Fig3 is applied.
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Fig 3 Schematic View oI SRAM Cell Test ConIiguration

The Iollowing waveIorms are observed:


Fig 4 Write Enable , Data In , Data Out WaveIorms respectively

The waveIorms belong to write 0, read 0, write 1 and read 1 operations respectively. Since read and
write enable is low asserted during the Read operation RE0 while WE1 and Data In is blocked by the tri-
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state buIIers. In Write 1 operation RE1, WE0 Data In1 as Data In0 in Write 0 operation. Since WE and
RE are reversed Iorms oI each other RE`s not included in the waveIorm.


W W W
M7 0.6u M12 0.5u M17 12u
M8 0.4u M13 15u
M9 0.5u M14 1u
M10 0.5u M15 25u
M11 0.5u M16 1u

Table 2 Width Sizes oI Transistors(all L`s0.35u)


3. Layout Design

In this part it was tried to achieve minimum area Ior the layout according to the standard cell
procedure. The main design speciIication was to produce a rectangular shape which can be cascaded
according to DRC considerations. Final layout dimension was 8.6u X 7.8u.



Fig 5 Final Layout Design oI SRAM Cell

The cascaded version is tested with the 9 X 9 Iorm in Fig 6.

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Fig 6 Cascaded Version


4. Measurements

4.1. Capacitance Measurements

In order to measure the row and column capacitances 1kO resistances are connected to Row Select and
Bit Lines respectively and pulse signal is applied. Capacitance value is extracted Irom RC time constant
derived Irom the rise times oI the output signals.


Fig 7 Rise Time Ior Row Capacitance Fig 8 Rise Time Ior Column Capacitance
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Fig 9 Measurement Circuit Ior Row Capacitance Fig 10 Measurement Circuit Ior Column
Capacitance


xRC 1k`Crow47.4psec xRC 1k`Ccol255p sec

Crow47.4fF Ccol255fF

For R value calculations the resistance per square Ior met1 and met2, 70 mO is multiplied by the met2 length
*0.5u (met1 width) or *0.6u (met2 width) used Ior row select and column lines.

Rrow70mO`7.2u`0.5 Rcol70mO`8.6`0.6
0.252O 0.36 O


Lumped RC values:

Rcol255` 0.36mO92,1O Rrow255`0.252mO64,5O
Ccol255`255fF65.025pF Crow255`47.4fF12.16pF


RCcol92,1O`65.025pF RCrow64,5O`12.16pF
5.99pF`O 0.78pF`O

xoverall (RCcol+ RCrow)((256+1)/(2`256))
(5.99`0.5)+(0.78`0.5)
2.99+0.39ns
3.38ns


4.2. Delay Measurement

In order to measure time delay Irom the column decoder output to the bit output oI the cell is at the
upper right corner oI a 64 kBit SRAM array, a pulse signal is sent to the column select nmoses over the
lumped Rcol and Ccol values and the output is observed at the right arm oI the diIIerential ampliIier.
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Fig 11 Test Schematic Ior Column Delay




Fig 11 Simulation Results Ior Column Delay
(Data Out, Column In, Data In, Write Enable waves respectively)

5. Discussion

Expected delay on the column line was 2.99ns while the measured value was 3.55ns which is more
than expectation. It may have originated Irom the Iact that the only delay calculated was the delay oI the
column line. When the delay oI the detection circuitry is added delay is expected to increase. It can be
deduced that using non-ideal diIIerential ampliIier slows down the circuitry .