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Abstract In this paper, a ZVS-PWM three-phase current-
fed push-pull DC-DC converter is proposed. When compared to
single-phase topologies, the three-phase DC-DC conversion
increases the power density, uses the magnetic core of the
transformer more efficiently, reduces the stress on switches and
requires smaller filters since the frequency for its design is
higher. The proposed converter employs an active clamping
technique by connecting the primary side of the transformer to a
three-phase full bridge of switches and a clamping capacitor.
This circuit allows the energy from the leakage inductances to be
reused, increasing the efficiency of the converter. If appropriate
parameters are chosen, soft-commutation of the switches (ZVS)
can also be achieved. The soft-commutation improves the
efficiency even further, allows higher switching frequencies to be
used and reduces the electromagnetic interference (EMI)
significantly. Applications such as fuel cell systems,
transportation and uninterruptable power supplies are some
examples that can benefit from the advantages presented by this
converter. The theoretical analysis, a design example and
experimental results for a prototype implementing this topology
are presented. The prototype was designed to process 4 kW at
full load with an input voltage of 120 V, an output voltage of 400
V and a switching frequency of 40 kHz.

Index Terms DCDC power conversion, multiphase, active
clamping, soft-commutation.

I. INTRODUCTION
HREE-PHASE systems are well known by their use in
electric power generation transmission and distribution.
The cost saving they provide by employing less material than
single-phase systems assured success in these areas and led to
three-phase rectifiers, inverters and also DC-DC converters.
Industrial environments have an increasing need for
high-efficiency DC-DC converters. Applications including
distributed generation and uninterruptable power supplies
generally count on single-phase DC-DC converters with big
and heavy transformers. The high volume associated with
these converters makes them an expensive choice and their


Manuscript received May 24, 2011. Accepted for publication February 13,
2012.
Copyright (c) 2009 IEEE. Personal use of this material is permitted.
However, permission to use this material for any other purposes must be
obtained from the IEEE by sending a request to pubs-permissions@ieee.org.
The authors are with the Power Electronics Institute, Department of the
Electrical Engineering, Federal University of Santa Catarina, Florianpolis
88040-970, Brazil (e-mail: romero@inep.ufsc.br).
use in the transportation area is sometimes impossible.
The introduction of high-frequency three-phase
transformers on DC-DC converters brought the possibility of
increasing power density, using the magnetic cores more
efficiently and reducing the current stress on power switches.
In addition, the increase in the high-frequency component
seen by the filters allowed the use of much smaller inductors
and capacitors [1].
After this, other three-phase DC-DC converter topologies
were developed and compared [2] and techniques to increase
the efficiency even more using soft-commutation [3][5] and
reducing the number of semiconductors in the output rectifier
bridge [6] were studied. Most studies conclude that the three-
phase structures perform better than their single-phase
counterparts [7][9].
However, depending on the topology, the voltage across the
switches is not naturally clamped, requiring passive voltage
clampers that dissipate energy stored in the leakage
inductances [10][13] to prevent overvoltage. This energy
loss reduces the efficiency of the converter. In order to avoid
this problem, active clamping techniques have already been
presented for single-phase converters and successfully reused
the energy that would be dissipated both in non-isolated [14]
and isolated topologies [15]. To sum up, soft-commutation
(ZVS) was also achieved with a correct parametric
combination.
This paper proposes a three-phase current-fed push-pull
DC-DC converter where the active clamping is performed
improving the topology presented in [12] and bringing the
advantages of this technique to the three-phase DC-DC
conversion. In this topology, a full three-phase bridge and a
clamping capacitor on the primary side of the transformer are
responsible for the active clamping without the need for an
extra switch [16]. The switching losses can be significantly
reduced and electromagnetic interference (EMI) minimized as
long as soft-commutation (ZVS) is achieved using appropriate
parameters. As usual in three-phase topologies, the filters are
designed for a frequency that is three times higher than the
switching frequency, allowing size reduction.
In the future, the proposed converter could be applied as a
high-efficiency alternative to many applications such as the
energy processing of photovoltaic arrays and fuel cell systems
[17][20] or automotive devices [21] and fuel cell powered
vehicles [22], where the three-phase DC-DC conversion is
already showing its benefits.
Romero L. Andersen, Member, IEEE and Ivo Barbi, Fellow, IEEE
A ZVS-PWM Three-Phase Current-Fed
Push-Pull DC-DC Converter
T
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2
II. THE PROPOSED ZVS-PWM THREE-PHASE DC-DC
CONVERTER
A. Circuit Description
The circuit of the proposed ZVS-PWM three-phase current-
fed push-pull DC-DC converter is presented in Fig. 1.
Switches S
1
, S
2
and S
3
and the capacitor C
g
were added to
the converter presented in [12] in order to achieve active
clamping. Inductances L
d1
, L
d2
and L
d3
are responsible for
maintaining the current during the commutation intervals.
They represent the sum of the leakage inductance of the
transformer and an external inductance, which is added to
each phase if needed. The addition of capacitors C
1
, C
1
, C
2
,
C
2
, C
3
and C
3
and appropriate dead time between main and
complementary gate signals provide the possibility to operate
with soft-commutation.
B. Simplified Circuit
Despite the complete circuit being the one shown in Fig. 1,
the analysis can be simplified maintaining the same
waveforms using the circuit of Fig. 2. This circuit, which will
be used to describe the operation stages, represents the non-
isolated equivalent version of the proposed converter with
current source input and voltage source output. The
transformer was substituted by a coupled three-phase reactor.
Voltages and currents originally from the secondary side are
referred to the primary side in this circuit. The time intervals
related to the commutations will not be considered during the
description of the operation stages due to being very short and
interfering very little in the voltage gain. The commutation
will be discussed separately in a later section.
C. Modulation
The gate signals are generated by the comparison of the
modulating signal V
M
and three sawtooth carriers 120 degrees
out of phase from each other. Fig. 3 shows the resulting gate
signals. V
G1
, V
G2
and V
G3
are the gate signals of S
1
, S
2
and S
3

respectively, and V
G1
, V
G2
and V
G3
are the gate signals of
switches S
1
, S
2
and S
3
respectively.
The proposed converter presents three different operation
regions depending on the duty cycle D according to Table I.
The topology studied in this paper is capable of operating in
the three regions defined by Table I differently from the
Fig. 2. Simplified non-isolated version of the active-clamped three-phase
current-fed push-pull DC-DC converter.

Fig. 1. Circuit of the proposed ZVS-PWM three-phase current-fed push-pull DC-DC converter.
t
0 120 240
V
M
V
ST1
t
t
V
G1
V
G1

t
V
ST2
t
t
V
G2
V
G2

t
V
ST3
t
t
V
G3
V
G3

V
M
V
M
360
D.T
s
T
s
/3
T
s
(1-D).T
s

Fig. 3. Signals generated by the modulator.
TABLE I
OPERATION REGIONS
Region Duty cycle Switches simultaneously on
R1 0 < D < 1/3 None
R2 1/3 D 2/3 Up to two
R3 2/3 < D < 1 Up to three
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3
converter presented in [12] which could not operate in region
R1 due to the absence of a demagnetizing path for the
inductor. The converter proposed in this paper can transfer
energy stored in the input inductor to the clamping capacitor if
operation in region R1 is desired.
In this paper this converter will be analyzed for operation in
region R3. Operating in region R3 proves the principle of the
active clamping in this topology for the worst case, as the
higher the duty cycle, the higher the voltage across the
switches. A good design for the other regions could achieve
an even better result.
III. PRINCIPLE OF OPERATION AND VOLTAGE GAIN
A. Operation in Region R3
Operating in region R3, the proposed converter has nine
topological stages per switching period that can be described
as follows:
Before the first stage, S
1
, S
2
and S
3
are already conducting.
1) 1
st
stage (t
0
, t
1
) Starts when switch S
1
is turned on.
Before this stage, S
1
was conducting and capacitor C
g
was
delivering energy. Current i
Ld1
(t), initially negative and equal
to I
L
/3, increases linearly through the intrinsic diode of S
1
as
shown in Fig. 4(a), becoming positive and increasing its value
though S
1
until reaching I
L
/3 as shown in Fig. 4(b). Currents
i
Ld2
(t) and i
Ld3
(t) decrease linearly from 2I
L
/3 to I
L
/3 through
switches S
2
and S
3
respectively. The load receives energy
from the commutation inductances through diodes D
1
, D
5
and
D
6
. The source does not transfer energy to the load during this
stage.
2) 2
nd
stage (t
1
, t
2
) Starts when currents i
Ld1
(t), i
Ld2
(t) and
i
Ld3
(t) equal I
L
/3. Currents i
Ld1
(t), i
Ld2
(t) and i
Ld3
(t) remain at
I
L
/3 and the diodes of the rectifier bridge remain off. This
stage can be seen in Fig. 4(c). The source does not transfer
energy to the load during this stage.
3) 3
rd
stage (t
2
, t
3
) Starts when switch S
2
is turned off.
Current i
Ld2
(t) decreases linearly from I
L
/3 through the
intrinsic diode of S
2
as shown in Fig. 4(d), then it equals zero
and starts to increase negatively, as shown in Fig. 4(e), until it
reaches I
L
/3. In Fig. 4(d) the clamping capacitor C
g
receives
energy from the commutation inductance and in Fig. 4(e) the
capacitor C
g
returns this energy. Currents i
Ld1
(t) and i
Ld3
(t)
increase linearly from I
L
/3 to 2I
L
/3 through switches S
1
and S
3

respectively. The load receives energy from the source
through diodes D
2
, D
4
and D
6
.
The fourth and the seventh topological stages are similar to
the first stage; the fifth and eighth topological stages are
similar to the second stage; the sixth and ninth stages are
similar to the third stage. The only difference is that other
switches are on. After the ninth stage, the switching period is
complete and a new period starts with the first stage.
The main voltages of the circuit during the described stages
are shown in Table II. The main theoretical waveforms for
region R3 are shown in Fig. 5, whose time intervals are
described by equations as presented in Table III. The
waveforms plotted on Fig. 5 and the voltages presented in
Table II correspond to the symbols presented previously on
Fig.1 and Fig. 2.

B. Voltage Gain
Equation (1) is the average current through the clamping
capacitor C
g
.

(a)


(b)


(c)


(d)


(e)

Fig. 4. Topological Stages: (a) first stage part 1; (b) first stage part 2; (c)
second stage; (d) third stage part 1; (e) third stage part 2.
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4
( ) 1
2
0
3
0
3
s
D T
Ld L
s d
V I
t dt
T L
-

+ =

(1)
Substituting V
Ld2
during the third stage from Table II in (1)
and solving the integral yields (2).
1
o d s L
Cg
V L f I
V
n D

=

(2)
Considering the analysis that there are no losses in the
converter, equation (3) is valid.
i L o o
V I V I = (3)
Substituting I
L
from (3) in (2), (4) is found.
1
1
Cg
o
o
V
I
V D n
= +

(4)
Where
o
I is given by (5).
d s o
o
i
L f I
I
V

= (5)
As the average voltage across the inductors is zero, the
average voltage across the switches S
1
, S
2
and S
3
is the input
voltage V
i
, and (6) can be written.
( ) 1
i Cg
V D V = (6)
Equation (6) leads to the input clamping capacitor voltage
gain shown in (7).
1
1
Cg
i
V
V D
=

(7)
Substituting (4) in (7) leads to the input output voltage
gain (8).
( ) 1
o
i o
V n
q
V D n I
= =
+
(8)
Equation (8) represents the voltage gain of the proposed
three-phase current-fed push-pull DC-DC converter with
active clamping in region R3.
C. Output Characteristic
Equation (8) was used to plot the curves of the output
characteristic of the converter presented in Fig. 6. The output
characteristic shows the voltage gain divided by the turns ratio
/ q n versus normalized output current multiplied by the turns
TABLE III
EQUATIONS FOR TIME INTERVALS OF FIG. 5
First stage 1
d L
o
n L I
t
V

A =
Second Stage
2 1 3
3
s
T
t t t A = A A
Third stage ( )
3
1
s
t D T A =

TABLE II
MAIN VOLTAGES DURING EACH TOPOLOGICAL STAGE
Voltage
1
st
Stage 2
nd
Stage 3
rd
Stage
v
Lr1
(t)
2
3
o
V
n
| |

|
\ .
0
1
3
o
V
n
| |

|
\ .

v
Lr2
(t)
1
3
o
V
n
| |

|
\ .
0
2
3
o
V
n
| |

|
\ .

v
Lr3
(t)
1
3
o
V
n
| |

|
\ .
0
1
3
o
V
n
| |

|
\ .

v
Ld1
(t)
2
3
o
V
n
| |

|
\ .
0
1
3
o
Cg
V
V
n
| |

|
\ .

v
Ld2
(t)
1
3
o
V
n
| |

|
\ .
0
2
3
o
Cg
V
V
n
| |

|
\ .

v
Ld3
(t)
1
3
o
V
n
| |

|
\ .
0
1
3
o
Cg
V
V
n
| |

|
\ .

v
x
(t) 0 0
3
Cg
V

S1 gate
signal
S2 gate
signal
S3 gate
signal
0 120 240 360
1 2 3 4 5
i
L
(t)
t
t
t
t
I
L
6 7 8 9
2I
L
/3
i
Ld1
(t)
t
I
L
/3
-I
L
/3
I
o_max
i
o
(t)
t0 t2 t3
D.Ts
Ts/3
Ts
t
i
Ls1
(t)
t
I
o_max
-I
o_max
/2
2I
L
/3
i
S1
(t)
t
I
L
/3
i
Cg
(t)
t
V
Cg
v
Cg
(t)
t
(1-D).Ts
I
L
/3
t5 t6 t8 t9
-I
L
/3
t1 t4 t7
Stage
t1 t2 t3
Fig. 5. Main theoretical waveforms for region R3.
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5
ratio
o
n I for different duty cycles of region R3. As
expected, the voltage gain is not only dependent on duty
cycle, even in continuous conduction mode; there is also a
voltage drop caused by the inductances L
d1
, L
d2
and L
d3
which
increases with the output current. Fig. 6 is plotted only for
region R3 and considering continuous conduction mode
(CCM), as the input current is considered free of ripple in the
analysis. The theoretical curves show good agreement with
the simulated points obtained by numerical simulation of the
circuit.
IV. COMMUTATION ANALYSIS
The topological stages reveal that both the turning on and
turning off of a switch in region R3 presents a current module
of I
L
/3 available to perform the commutation. Immediately
after switch S
1
is turned off, Fig. 7 shows the situation during
the dead time where capacitor C
1
is charging and capacitor C
1

is discharging. After the complete discharge of C
1
, the
intrinsic diode of S
1
will start to conduct and switch S
1
can be
turned on under ZVS condition.
Voltage on capacitor C
1
and C
1
can be expressed as shown
in (9).
( ) ( )
1 1
'
C C Cg
v t v t V + = (9)
Deriving (9) and considering C
1
=C
1
=C leads to (10).
( ) ( )
1 1
'
0
c c
dv t dv t
C C
dt dt
+ = (10)
Based on Fig. 8 and the equations presented, (11) is
obtained.
1 1
'
6
L
c c
I
i i = = (11)
If the input current I
L
, the clamping voltage V
Cg
and the
maximum commutation interval t A are known, the maximum
commutation capacitance C is given by equation (12).
6
L
Cg
I t
C
V
A
=

(12)
The capacitance C is sum of the intrinsic output capacitance
of the switch C
oss
and the externally connected capacitance
C
ext
.
ZVS operation is intrinsic to this topology. It is the result of
the topology, the modulation and the parameters. If external
capacitors and external inductors are not added, in some
condition the converter can still achieve soft-commutation
because of the intrinsic capacitance of the switch and the
leakage inductances of the transformer. The addition of
external capacitors and inductors is done to guarantee a range
of ZVS operation (e.g., from 40% to 100% load).
V. DESIGN EXAMPLE
A. Specifications
In order to simulate the converter and build a prototype
some specifications were defined as follows:
P
o
= 4 kW (output power);
V
i
= 120 V (input voltage);
V
o
= 400 V (output voltage);
f
s
= 40 kHz (switching frequency);
= 93% (expected efficiency);
I
L
= 0.08I
L
(input current ripple).
B. Clamping Voltage and Duty Cycle
The duty cycle was chosen to guarantee operation in region
R3 and to generate an acceptable clamping voltage. Choosing
a clamping voltage of 450 V, the duty cycle is calculated as
follows.
120
1 1 0.733
450
i
Cg
V
D
V
= = = (13)
C. Turns Ratio of the Transformer, Effective Duty Cycle
and Commutation Inductance
The turns ratio of the transformer is calculated to achieve
the desired output voltage considering the effective duty cycle
reduction
o
n I . If an effective duty cycle reduction of 5% is
chosen, the turns ratio of the transformer is calculated as
follows.
( )
( )
400
1 1 0.733 0.05 1.06
120
o
o
i
V
n D n I
V
= + = + = (14)
The turns ratio n was defined as the number of turns of the
secondary winding divided by the number of turns of the
primary winding.

Fig. 7. Charging of C
1
and discharging of C
1
during the dead time.
Fig. 6. Output Characteristic of the Three-phase Current-Fed Push-Pull DC-DC
Converter with Active Clamping for CCM operation in region R3.
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6
After this, the commutation inductance is calculated as
shown in (15).
3
0.05 120
14.15
40 10 1.06 10
o i
d
s o
n I V
L H
f n I


= = =

(15)
Finally, in the laboratory a 15 H commutation inductance
was used, resulting in an effective duty cycle reduction of
5.3% (
o
n I ), which is still acceptable allowing these values
to be maintained.
D. Duration of Operation Stages
The duration of the operation stages can be calculated as
shown in (16), (17) and (18).
6
1
1.06 15 10 10
1.325
120
d o
i
n L I
t s
V

A = = = (16)
( ) ( )
6
3
1 1 0.733 25 10 6.675
s
t D T s

A = = = (17)
2 1 3
25
1.325 6.675 333.3
3 3
s
T
t t t s ns
| |
A = A A = =
|
\ .
(18)
E. Boost Inductance
Operating in region R3, the boost inductance can be
calculated as shown in (19).
( )
3
3
120 0.733 2 3
2
70
3 4 10
0.08 40 10
0.93 120
i
L s
V
L D H
I f


| |
= = ~
|
A
\ .

(19)
F. Peak Output Current
The peak current
_ max o
I of Fig. 5 is calculated as (20).
( ) ( )
_ max
2 3 2 3 10
21.03
1 0.733 0.05 1
o
o
o
I
I A
D n I

= = =
+ +
(20)
G. RMS Value of the Current through the Output Capacitor
The output capacitor can be chosen by the RMS value of
the current through it
Coef
I , which is calculated by (21).
( )
4 9 4 9
1 10 1 6.34
0.317 1
Coef o
o
I I A
D n I
= = =
+
(21)
Four capacitors of 1000 F/250 V, a pair in series
connected in parallel with the other pair in series were used to
fulfill the voltage and current requirements.
H. External Commutation Capacitance
Considering a maximum commutation interval (dead time)
of 1 s and expecting ZVS from 40% to 100% load range, the
maximum external commutation capacitance to be connected
in parallel with each MOSFET (SPW47N60C3) that allows
complete discharge was calculated as
6
0.4 0.4 35.8 1 10
2.2 3.1
6 6 450
L
ext oss
Cg
I t
C C nF nF
V

A
s = =

(22).
After simulation and laboratory tests, good results were
obtained with external capacitors of 2.2 nF, which were
chosen for the prototype.


If the signals are generated appropriately, the switches are
turned on during the conduction interval of its intrinsic diode,
so the turn on is naturally ZVS.
However, during the turn off, the commutation capacitance
has to ensure that voltage across the switch increases slowly,
so that the current is already in a reduced value near to zero.
Fig 8 shows a simulation result for the rated power where
switch S
1
is turning off. This simulation used the parameters
calculated in this design example and the model of the
MOSFET provided by the manufacturer. As expected, the
voltage across the switch rises slowly and most of the current
is deviated to the external commutation capacitor. The current
through the switch is very low during the rise of the voltage,
resulting in low commutation loss. Soft-commutation was
achieved from approximately 50% to 100% load in
simulation.
VI. PROTOTYPE IMPLEMENTATION AND EXPERIMENTAL
RESULTS
A. Prototype Description
A prototype implementing the proposed converter was built
in order to validate the analysis. The main specifications and
components used are shown in Table IV. A photograph of the
prototype can be seen in Fig. 9.
Three small inductors were externally added to each phase
of the transformer to achieve the total commutation
inductance of 15 H.
On the primary side of the transformer, six MOSFETs
CoolMOS SPW47N60C3 were used due to their fast
switching characteristics and low resistance when turned on.
The gate signals were generated by three PIC18F1330
microcontrollers and the connection to the power switches
was made using three MOSFET drivers SKHI 20opA by
Semikron, one for each leg.
A dead-time duration of 1 s between the gate signals of
switches of the same leg was introduced by the drivers.
Fig. 8. Detail of the turn off of a switch (S
1
).
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7
B. Experimental Results
Relevant waveforms were acquired when the converter was
operating at its rated power of 4 kW. Fig. 10 shows the input
voltage and input current. The input voltage is 120 V and very
low ripple is presented by the input current as specified in the
design example. The output voltage and output current shown
in Fig. 11 are also at rated values of 400 V and 10 A
respectively.
The voltage and current in the primary winding L
p1
and
secondary winding L
s1
are presented in Fig. 12 and Fig. 13
respectively. In both windings, the average voltage is zero as
expected. The average current is zero only for the secondary
winding L
s1
. On the primary side there is a DC component
which is one-third of the average input current of the
converter in this topology.
On the primary side, the waveforms of the voltages across
the MOSFETs are very similar to the theoretical analysis.
These waveforms can be seen in Fig. 14 and Fig. 15 for
complementary switches of the same leg. In addition to the
voltages, the L
p1
current is also presented in both figures.
Active clamping and soft-commutation contribute to
waveforms without voltage overshoot and smoothed
switching slopes. The voltage is clamped at 450 V for both
switches as designed.
The details of the commutation were not obtained
experimentally because the measurement of the current
through the switch would introduce a series inductance and
degrade the commutation. However, it can be noted that
switch S
1
is turned on (its voltage become zero) during the
negative part of L
p1
current, which is while the intrinsic diode
is in conduction, and then ZVS turn on occurs. As for the turn
off, the voltage does not increase very rapidly, as a result of
the charge of the commutation capacitance. Overvoltage is
also not present. This waveform also indicates soft-
commutation during the turn off.
TABLE IV
MAIN SPECIFICATIONS AND COMPONENTS OF THE PROTOTYPE
Description
Quantity Values
Output Power (P
o
) - 4 kW
Input Voltage (V
i
) - 120 V
Output Voltage (V
o
) - 400 V
Switching Frequency (f
s
) - 40 kHz
High-Frequency Three-Phase
Transformer (T
1
)
1 N
s
/N
p
=37/32
Input Inductor (L) 1 70 H
Electrolytic Output Capacitors (C
1

C
4
)
4
1000 F / 250 V
(electrolytic)
Polypropylene Output Capacitor
(C
5
)
1
1 F / 630 V
(polypropylene)
Clamping Capacitors (C
6
C
8
) 3
1.5 F / 1 KV
(polypropylene)
External Commutation Capacitors
(C
9
C
14
)
6
2.2 nF
(polypropylene)
MOSFETs
(S
1
, S
1
, S
2
,

S
2
, S
3
, S
3
)
6 SPW47N60C3
Rectifier Diodes (D
1
D
6
) 6 MUR860

Fig. 9. Photograph of the laboratory prototype.
Fig. 10. Input voltage and input current.
Fig. 11. Output voltage and output current.
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8
On the secondary side, the voltages and currents in the
diodes are also as expected from the design. Fig. 16 and Fig.
17 show the voltage across D
1
and D
4
respectively along with
the current in L
s1
. These voltages are naturally clamped at the
output voltage of 400 V.
Finally, the measured efficiency obtained with the
prototype for different load conditions is shown in Fig. 18.
The peak of efficiency occurred at 50% of the rated output
power reaching 95.3% efficiency. As the power increases, the
ohmic losses cause the efficiency to decrease again. At rated
power the efficiency obtained was around 93.2%.


Fig. 12. Voltage across and current through L
p1
.

Fig. 13. Voltage across and current through L
s1
.

Fig. 14. Voltage across S
1
and current through L
p1
.

Fig. 15. Voltage across S
1
and current through L
p1
.

Fig. 16. Voltage across D
1
and current through L
s1
.

Fig. 17. Voltage across D
4
and current through L
s1
.
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9
VII. CONCLUSION
In this paper, a ZVS-PWM three-phase current-fed push-
pull DC-DC converter was proposed. The operation stages
were described and the main waveforms were plotted. The
equations of voltage gain and equations involving the
commutation parameters were derived to help the design
process.
A prototype was built for a rated power of 4 kW based on
the parameters calculated in the design example. This
prototype was able to operate with active clamping and soft-
commutation (ZVS) of the MOSFETs. The waveforms
acquired validate the theoretical analysis and the measured
efficiency for full load was 93.2%, remaining above 94% for
most of the load range.
As an isolated topology, this converter presents competitive
efficiency and can be applied with good performance as an
energy processing stage for many renewable sources. The
most suitable applications include distributed generation,
uninterruptable power supplies and transportation.

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90
91
92
93
94
95
96
97
0 500 1000 1500 2000 2500 3000 3500 4000 4500
Output Power (W)
E
f
f
i
c
i
e
n
c
y

(
%
)

Fig. 18. Converter efficiency as function of the output power for D=0.733.
Copyright (c) 2011 IEEE. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication.


10
Romero L. Andersen (M11) was born in
Florianpolis, Santa Catarina, Brazil, in 1980. He
received the B.S., M.S. and Ph.D. degrees in
electrical engineering from the Federal University of
Santa Catarina, Florianpolis, Brazil, in 2003, 2006
and 2010 respectively.
He is currently a postdoctoral researcher at the
Power Electronics Institute, Federal University of
Santa Catarina, Brazil. His interests include DC-DC
power conversion, power converter modeling, and
renewable energy sources.

Ivo Barbi (M78-SM90-F11) was born in
Gaspar, Santa Catarina, Brazil, in 1949. He received a
B.S. and a M.S. degree in electrical engineering from
the Federal University of Santa Catarina,
Florianopolis, Brazil, in 1973 and 1976, respectively,
and the Dr.Ing. degree from the Institut National
Polytechnique de Toulouse, France, in 1979.
He founded the Brazilian Power Electronics
Society and the Power Electronics Institute of the
Federal University of Santa Catarina. He is currently a
professor of the Power Electronics Institute, Federal University of Santa
Catarina.